register simulates correctly up to the fake clock generation

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Michele

2022-03-05 20:28:50 +01:00

parent 78a8f72d25

commit aa67bd6168

5 changed files with 1458 additions and 10 deletions

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test/unit_tests/register_write/run/prsim.out Normal file

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1113

test/unit_tests/register_write/run/test.prs

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