bics/actlib_dataflow_neuro
23
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

register simulates correctly up to the fake clock generation

Browse Source
This commit is contained in:
Michele
2022-03-05 20:28:50 +01:00
parent 78a8f72d25
commit aa67bd6168
5 changed files with 1458 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
test/unit_tests/register_write/test.act
View File

@@ -30,13 +30,13 @@ import "../../dataflow_neuro/registers.act";
import globals;
open tmpl::dataflow_neuro;
defproc register_test (avMx1of2<1+2+2> in; d1of<2> data[2<<2]){
// 2 bits encoder, 2 bits long words, 2 delays????
defproc register_test (avMx1of2<1+2+2> in; d1of<2> data[2<<2]; bool? dly_cfg[2]){
register_rw<2,2,2> registers(.in=in,.data = data);
//Low active Reset
bool _reset_B;
power supply;
power _supply;
prs {
Reset => _reset_B-
}
@@ -44,7 +44,8 @@ defproc register_test (avMx1of2<1+2+2> in; d1of<2> data[2<<2]){
_supply.vss = GND;
_supply.vdd = Vdd;
registers.reset_B = _reset_B;
registers.reset_B_mem = _reset_B;
registers.reset_mem_B = _reset_B;
registers.dly_cfg = dly_cfg;
}