register simulates correctly up to the fake clock generation

test/unit_tests/register_write/test.prsim

@@ -1,8 +1,39 @@
 watchall
 system "echo '[0] start test'"
 set Reset 1
-set-qdi-channel-neutral "t.in" 2
+
+
+set-qdi-channel-neutral "t.in" 5
+set t.data[0].d[0] 0
+set t.data[0].d[1] 0
+set t.data[1].d[0] 0
+set t.data[1].d[1] 0
 cycle
 status X
 mode run
+assert-qdi-channel-neutral "t.in" 5
+assert t.data[0].d[0] 0
+assert t.data[0].d[1] 0
+assert t.data[1].d[0] 0
+assert t.data[1].d[1] 0
+set Reset 0
+cycle
 system "echo '[1] reset completed'"
+# Set delay config lines
+set t.dly_cfg[0] 1
+set t.dly_cfg[1] 1
+cycle
+assert-qdi-channel-neutral "t.in" 5
+system "echo '[2] delay line set'"
+set-qdi-channel-valid "t.in" 5 3
+cycle
+assert-qdi-channel-valid "t.in" 5 3
+assert t.registers._clock 1
+assert t.registers._out_encoder[0] 1
+assert t.registers._out_encoder[1] 0
+set-qdi-channel-neutral "t.in" 5
+cycle
+assert t.registers._clock 0
+system "echo '[3] clock checked'"
+
+