register simulates correctly up to the fake clock generation

dataflow_neuro/registers.act

@@ -55,12 +55,11 @@ defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power s
     bool _in_v_temp,_in_a_temp,_clock_temp,_clock;
     pint _nw = 2<<log_nw;
     //Validation of the input 
-    Mx1of2<1+log_nw+wl> in_temp;
+    Mx1of2<1+log_nw+wl> _in_temp;
-    (i:1+log_nw+wl:in_temp.d[i] = in.d.d[i];)
+    (i:1+log_nw+wl:_in_temp.d[i] = in.d.d[i];)
-    vtree<1+log_nw+wl> val_input(.in = in_temp,.out = _in_v_temp, .supply = supply);
+    vtree<1+log_nw+wl> val_input(.in = _in_temp,.out = _in_v_temp, .supply = supply);
     sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
-    in.v = _in_v_temp;
+    // Generation of the fake clock pulse
-    // Generation of the clock pulse
     delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp, .out = _clock_temp,.s = dly_cfg, .supply = supply);
     sigbuf_1output<4> clk_X(.in = _clock_temp,.out = _clock,.supply = supply);
     // Sending back to the ackowledge

test/unit_tests/register_write/run/prsim.out

@@ -0,0 +1,304 @@
+t.registers.ff[4].q t.registers._clock_word_temp[0] t.registers.ff[15].reset_B t.registers.atree[0].in[0] t.registers._clock_temp t.registers.ack_dly._a[1] t.dly_cfg[1] t.registers.ff[5].reset_B t.registers.ff[8].d t.registers._clock t.registers.clk_dly.and2[0]._y t.in.d.d[0].t t.registers.ff[2].reset_B t.registers.ff[7].clk t.registers.ff[12]._sqib t.registers.ack_dly.dly[1].__y t.registers.clock_buffer[2].out[0] t.registers.val_input.ct.in[1] t.registers.ff[1].clk t.registers.ff[5]._mqi t.registers.clock_buffer[5].out[0] t.registers.ff[8]._clk t.registers.ff[7]._mqib t.registers.ff[15].q t.in.d.d[4].f t.registers._clock_word_temp[2] t.registers.clk_dly.dly[2]._y t.registers.ack_dly.dly[1].___y t.registers.ff[4].reset_B t.registers.ff[13]._clk t.registers._out_encoder[3] t.registers.clock_buffer[1].buf1._y t.registers.ff[11]._mqi t.registers.ff[13]._mqib t.in.d.d[3].t t.dly_cfg[0] t.registers.ff[4].__clk t.registers._in_v_temp t.registers.atree[1].in[0] t.registers._out_encoder[2] t.registers.ff[6].clk t.registers.ff[14]._mqi t.registers._out_encoder[1] t.registers.clk_dly.and2[1]._y t.registers.atree[2].in[1] t.registers.val_input.ct.in[0] t.registers.ack_dly.dly[2]._y t.registers._in_a_temp t.registers.ff[3].__clk t.in.d.d[0].f t.registers.clk_dly.dly[1].y t.registers.ff[1].__clk t.in.v t.registers._clock_word_temp[5] t.registers.clock_buffer[0].out[0] t.registers.clock_buffer[4].out[0] t.registers.clk_dly.dly[2].y t.registers.ff[0].q t.in.d.d[4].t t.registers.ff[0].clk t.registers.ff[14]._clk t.registers.clk_dly.dly[1].a t.registers.ff[10]._mqib t.registers._clock_word_temp[3] t.registers._out_encoder[7] t.registers.ff[6].__clk t.registers.ff[0]._sqib t.registers.ff[9]._clk t.registers.ff[15]._mqib t.registers.ack_dly.dly[0].___y t.registers.ff[11].__clk t.registers._out_encoder[4] t.registers.val_input.ct.in[3] t.registers.ff[7]._mqi t.registers._out_encoder[5] t.registers.ff[5].q t.registers.ff[1]._sqi t.registers.ff[1]._sqib t.registers.ff[7]._clk t.registers._clock_word_temp[4] t.registers.atree[0].in[1] t.registers.clock_buffer[0].buf1._y t.registers._out_encoder[0] t.registers.ack_dly.dly[2].___y t.registers._clock_word_temp[7] t.registers.clock_buffer[6].out[0] t.registers.ff[10].reset_B t.registers.ff[3]._clk t.registers.ff[13]._sqi t.registers.ff[2]._mqi t.registers._clock_word_temp[6] t.registers.ack_dly.mu2[0]._y t.registers.atree[1].and2s[0]._y t.registers.clk_dly._a[1] t.registers.val_input.ct.in[4] t.registers.ff[11]._sqi t.registers.ff[3].reset_B t.registers.ff[6]._mqi t.registers.ff[10].clk t.registers.val_input.OR2_tf[3]._y t.registers.ff[5].__clk t.registers.clk_X.buf1._y t.registers.ff[11]._clk t.registers.ff[0].d t.registers.ff[14]._sqi t.registers.ff[7]._sqib t.registers.clk_dly.dly[0].___y t.registers.ff[8].q t.registers._clock_word_temp[1] t.registers.and_encoder[2]._y t.registers.clk_dly.dly[1].___y t.registers.ff[5]._sqib t.registers._out_encoder[6] t.registers.ff[6].reset_B t.registers.clock_buffer[4].buf1._y t.in.a t.registers.clk_dly.mu2[1]._s t.registers.ff[5].d t.registers.ff[9]._mqib t.registers.clk_dly.dly[0]._y t.registers.ff[4]._mqib t.registers.ff[8]._sqi t.in.d.d[3].f t.registers.val_input.OR2_tf[2]._y t.registers.val_input.ct.in[2] t.registers.ff[14].q t.registers.val_input.ct.tmp[6] t.registers.clk_dly.dly[1]._y t.registers.ff[13].q t.registers.ff[1].d t.registers.ff[2]._clk t.registers.ff[10].__clk t.registers.ff[3]._mqib t.registers.ack_dly.dly[2].y t.registers.atree[6].and2s[0]._y t.registers.atree[0].and2s[0]._y t.registers.clock_buffer[3].out[0] t.registers.ff[2]._sqi t.registers.ff[3].clk t.registers.ff[3].d t.registers.ff[1]._mqi t.registers.ff[12].clk t.registers.clk_dly.mu2[1]._y t.registers.ff[9]._mqi t.registers.ff[8]._mqib t.registers.clk_dly.mu2[0]._s t.registers.ff[10].q t.registers.ack_dly.dly[0]._y t.registers.clk_dly.dly[0].a t.registers.ff[2].q t.registers.ff[4]._sqib t.registers.ack_dly.dly[0].a t.registers.ff[11].reset_B t.registers.clock_buffer[2].buf1._y t.registers.ff[10]._sqi t.registers.ff[15]._clk t.registers.ff[13]._sqib t.registers.ff[9].clk t.registers.ff[14].reset_B t.registers.ff[7].d t.registers.ff[4].d t.registers.ff[7]._sqi t.registers.clk_dly.dly[1].__y t.registers.ff[15].clk t.registers.ff[6]._mqib t.registers.clk_dly.dly[0].y t.registers.ff[2].__clk t.registers.ff[2]._sqib t.registers.clk_dly.mu2[0]._y t.registers.ff[9].reset_B t.registers.ff[10].d t.registers.ff[1].q t.registers.ff[3]._sqi t.registers.ff[5]._mqib t.registers.ff[6].d t.registers.ff[13].clk t.registers.ff[6]._clk t.registers.clock_buffer[7].out[0] t.registers.ff[5]._sqi t.registers.ff[12]._sqi t.registers.ff[9]._sqi t.registers.atree[7].and2s[0]._y t.registers.ff[4]._clk t.registers.clock_buffer[3].buf1._y t.registers.clock_buffer[1].out[0] t.registers.val_input.ct.tmp[5] t.registers.ff[12]._mqi t.registers.atree[4].and2s[0]._y t.registers.ack_dly.dly[1]._y t.registers.ff[9].__clk t.registers.ff[14].d t.registers.and_encoder[0]._y t.registers.ff[13]._mqi t.registLine truncated
+[0] start test
+	     16472 t.in.d.d[0].f : 0
+	     16472 t.data[1].d[1] : 0
+	     16472 t.data[1].d[0] : 0
+	     16472 t.data[0].d[1] : 0
+	     16472 t.data[0].d[0] : 0
+	     16472 t.in.d.d[4].t : 0
+	     16472 t.in.d.d[4].f : 0
+	     16472 t.in.d.d[3].t : 0
+	     16472 t.registers.atree[0].in[0] : 0
+	     16472 t.in.d.d[3].f : 0
+	     16472 t.registers.atree[2].in[1] : 0
+	     16472 t.in.d.d[0].t : 0
+	     16472 t.registers.atree[0].in[1] : 0
+	     16472 t.registers.atree[1].in[0] : 0
+	     16485 t.registers.val_input.OR2_tf[3]._y : 1  [by t.in.d.d[3].f:=0]
+	     16487 t.registers.atree[4].and2s[0]._y : 1  [by t.registers.atree[0].in[0]:=0]
+	     16488 t.registers.atree[5].and2s[0]._y : 1  [by t.registers.atree[0].in[1]:=0]
+	     16491 t.registers._out_encoder[4] : 0  [by t.registers.atree[4].and2s[0]._y:=1]
+	     16492 t.registers.val_input.OR2_tf[0]._y : 1  [by t.in.d.d[0].t:=0]
+	     16506 t.registers.and_encoder[4]._y : 1  [by t.registers._out_encoder[4]:=0]
+	     16511 t.registers.atree[2].and2s[0]._y : 1  [by t.registers.atree[0].in[0]:=0]
+	     16512 t.registers.atree[3].and2s[0]._y : 1  [by t.registers.atree[2].in[1]:=0]
+	     16519 t.registers.atree[1].and2s[0]._y : 1  [by t.registers.atree[0].in[1]:=0]
+	     16566 t.registers._out_encoder[2] : 0  [by t.registers.atree[2].and2s[0]._y:=1]
+	     16887 t.registers.atree[7].and2s[0]._y : 1  [by t.registers.atree[2].in[1]:=0]
+	     16963 t.registers.atree[6].and2s[0]._y : 1  [by t.registers.atree[0].in[0]:=0]
+	     18198 t.registers.atree[0].and2s[0]._y : 1  [by t.registers.atree[0].in[0]:=0]
+	     18620 t.registers._out_encoder[0] : 0  [by t.registers.atree[0].and2s[0]._y:=1]
+	     22533 t.registers.val_input.OR2_tf[2]._y : 1  [by t.registers.atree[0].in[1]:=0]
+	     22534 t.registers.val_input.ct.in[2] : 0  [by t.registers.val_input.OR2_tf[2]._y:=1]
+	     25617 t.registers._out_encoder[5] : 0  [by t.registers.atree[5].and2s[0]._y:=1]
+	     25618 t.registers.and_encoder[5]._y : 1  [by t.registers._out_encoder[5]:=0]
+	     30209 t.registers.val_input.ct.in[3] : 0  [by t.registers.val_input.OR2_tf[3]._y:=1]
+	     30415 t.registers.and_encoder[2]._y : 1  [by t.registers._out_encoder[2]:=0]
+	     30697 t.registers._clock_word_temp[2] : 0  [by t.registers.and_encoder[2]._y:=1]
+	     31306 t.registers._out_encoder[6] : 0  [by t.registers.atree[6].and2s[0]._y:=1]
+	     31309 t.registers.and_encoder[6]._y : 1  [by t.registers._out_encoder[6]:=0]
+	     31465 t.registers.clock_buffer[2].buf1._y : 1  [by t.registers._clock_word_temp[2]:=0]
+	     32016 t.registers.clock_buffer[2].out[0] : 0  [by t.registers.clock_buffer[2].buf1._y:=1]
+	     41699 t.registers._out_encoder[7] : 0  [by t.registers.atree[7].and2s[0]._y:=1]
+	     42770 t.registers.and_encoder[7]._y : 1  [by t.registers._out_encoder[7]:=0]
+	     43724 t.registers._clock_word_temp[7] : 0  [by t.registers.and_encoder[7]._y:=1]
+	     44805 t.registers.clock_buffer[7].buf1._y : 1  [by t.registers._clock_word_temp[7]:=0]
+	     45823 t.registers._clock_word_temp[5] : 0  [by t.registers.and_encoder[5]._y:=1]
+	     46299 t.registers._out_encoder[1] : 0  [by t.registers.atree[1].and2s[0]._y:=1]
+	     46317 t.registers.and_encoder[1]._y : 1  [by t.registers._out_encoder[1]:=0]
+	     46805 t.registers.clock_buffer[5].buf1._y : 1  [by t.registers._clock_word_temp[5]:=0]
+	     50330 t.registers._clock_word_temp[1] : 0  [by t.registers.and_encoder[1]._y:=1]
+	     50808 t.registers.clock_buffer[5].out[0] : 0  [by t.registers.clock_buffer[5].buf1._y:=1]
+	     53437 t.registers._clock_word_temp[4] : 0  [by t.registers.and_encoder[4]._y:=1]
+	     53750 t.registers._clock_word_temp[6] : 0  [by t.registers.and_encoder[6]._y:=1]
+	     58510 t.registers.clock_buffer[6].buf1._y : 1  [by t.registers._clock_word_temp[6]:=0]
+	     59012 t.registers.clock_buffer[6].out[0] : 0  [by t.registers.clock_buffer[6].buf1._y:=1]
+	     59740 t.registers.val_input.ct.in[0] : 0  [by t.registers.val_input.OR2_tf[0]._y:=1]
+	     60570 t.registers.val_input.OR2_tf[1]._y : 1  [by t.registers.atree[1].in[0]:=0]
+	     60773 t.registers.val_input.ct.in[1] : 0  [by t.registers.val_input.OR2_tf[1]._y:=1]
+	     62627 t.registers.val_input.ct.C2Els[0]._y : 1  [by t.registers.val_input.ct.in[1]:=0]
+	     62766 t.registers.val_input.ct.tmp[5] : 0  [by t.registers.val_input.ct.C2Els[0]._y:=1]
+	     67334 t.registers.and_encoder[0]._y : 1  [by t.registers._out_encoder[0]:=0]
+	     68165 t.registers._out_encoder[3] : 0  [by t.registers.atree[3].and2s[0]._y:=1]
+	     68234 t.registers.and_encoder[3]._y : 1  [by t.registers._out_encoder[3]:=0]
+	     68245 t.registers._clock_word_temp[3] : 0  [by t.registers.and_encoder[3]._y:=1]
+	     75021 t.registers.clock_buffer[4].buf1._y : 1  [by t.registers._clock_word_temp[4]:=0]
+	     75225 t.registers.clock_buffer[4].out[0] : 0  [by t.registers.clock_buffer[4].buf1._y:=1]
+	     81838 t.registers.val_input.OR2_tf[4]._y : 1  [by t.in.d.d[4].f:=0]
+	     81853 t.registers.val_input.ct.in[4] : 0  [by t.registers.val_input.OR2_tf[4]._y:=1]
+	     81854 t.registers.val_input.ct.C3Els[0]._y : 1  [by t.registers.val_input.ct.in[4]:=0]
+	     81891 t.registers.val_input.ct.tmp[6] : 0  [by t.registers.val_input.ct.C3Els[0]._y:=1]
+	     82630 t.registers.val_input.ct.C2Els[1]._y : 1  [by t.registers.val_input.ct.tmp[6]:=0]
+	     82742 t.registers._in_v_temp : 0  [by t.registers.val_input.ct.C2Els[1]._y:=1]
+	     82782 t.registers.val_input_X.buf1._y : 1  [by t.registers._in_v_temp:=0]
+	     83039 t.in.v : 0  [by t.registers.val_input_X.buf1._y:=1]
+	     95231 t.registers.clock_buffer[1].buf1._y : 1  [by t.registers._clock_word_temp[1]:=0]
+	     95318 t.registers.clock_buffer[1].out[0] : 0  [by t.registers.clock_buffer[1].buf1._y:=1]
+	     99275 t.registers.clock_buffer[7].out[0] : 0  [by t.registers.clock_buffer[7].buf1._y:=1]
+	    103680 t.registers._clock_word_temp[0] : 0  [by t.registers.and_encoder[0]._y:=1]
+	    103974 t.registers.clock_buffer[0].buf1._y : 1  [by t.registers._clock_word_temp[0]:=0]
+	    103975 t.registers.clock_buffer[0].out[0] : 0  [by t.registers.clock_buffer[0].buf1._y:=1]
+	    120031 t.registers.clock_buffer[3].buf1._y : 1  [by t.registers._clock_word_temp[3]:=0]
+	    121837 t.registers.clock_buffer[3].out[0] : 0  [by t.registers.clock_buffer[3].buf1._y:=1]
+	    130254 t.registers.clk_dly.and2[0]._y : 1  [by t.registers._in_v_temp:=0]
+	    132261 t.registers.clk_dly.dly[0].a : 0  [by t.registers.clk_dly.and2[0]._y:=1]
+	    133470 t.registers.clk_dly.dly[0]._y : 1  [by t.registers.clk_dly.dly[0].a:=0]
+	    134060 t.registers.clk_dly.dly[0].__y : 0  [by t.registers.clk_dly.dly[0]._y:=1]
+	    134238 t.registers.clk_dly.dly[0].___y : 1  [by t.registers.clk_dly.dly[0].__y:=0]
+	    135041 t.registers.clk_dly.dly[0].y : 0  [by t.registers.clk_dly.dly[0].___y:=1]
+t.registers.ff[4].q t.registers.ff[15].reset_B t.registers._clock_temp t.registers.ack_dly._a[1] t.dly_cfg[1] t.registers.ff[5].reset_B t.registers.ff[8].d t.registers._clock t.registers.ff[2].reset_B t.registers.ff[7].clk t.registers.ff[12]._sqib t.registers.ack_dly.dly[1].__y t.registers.ff[1].clk t.registers.ff[5]._mqi t.registers.ff[8]._clk t.registers.ff[7]._mqib t.registers.ff[15].q t.registers.clk_dly.dly[2]._y t.registers.ack_dly.dly[1].___y t.registers.ff[4].reset_B t.registers.ff[13]._clk t.registers.ff[11]._mqi t.registers.ff[13]._mqib t.dly_cfg[0] t.registers.ff[4].__clk t.registers.ff[6].clk t.registers.ff[14]._mqi t.registers.clk_dly.and2[1]._y t.registers.ack_dly.dly[2]._y t.registers._in_a_temp t.registers.ff[3].__clk t.registers.clk_dly.dly[1].y t.registers.ff[1].__clk t.registers.clk_dly.dly[2].y t.registers.ff[0].q t.registers.ff[0].clk t.registers.ff[14]._clk t.registers.clk_dly.dly[1].a t.registers.ff[10]._mqib t.registers.ff[6].__clk t.registers.ff[0]._sqib t.registers.ff[9]._clk t.registers.ff[15]._mqib t.registers.ack_dly.dly[0].___y t.registers.ff[11].__clk t.registers.ff[7]._mqi t.registers.ff[5].q t.registers.ff[1]._sqi t.registers.ff[1]._sqib t.registers.ff[7]._clk t.registers.ack_dly.dly[2].___y t.registers.ff[10].reset_B t.registers.ff[3]._clk t.registers.ff[13]._sqi t.registers.ff[2]._mqi t.registers.ack_dly.mu2[0]._y t.registers.clk_dly._a[1] t.registers.ff[11]._sqi t.registers.ff[3].reset_B t.registers.ff[6]._mqi t.registers.ff[10].clk t.registers.ff[5].__clk t.registers.clk_X.buf1._y t.registers.ff[11]._clk t.registers.ff[0].d t.registers.ff[14]._sqi t.registers.ff[7]._sqib t.registers.ff[8].q t.registers.clk_dly.dly[1].___y t.registers.ff[5]._sqib t.registers.ff[6].reset_B t.in.a t.registers.clk_dly.mu2[1]._s t.registers.ff[5].d t.registers.ff[9]._mqib t.registers.ff[4]._mqib t.registers.ff[8]._sqi t.registers.ff[14].q t.registers.clk_dly.dly[1]._y t.registers.ff[13].q t.registers.ff[1].d t.registers.ff[2]._clk t.registers.ff[10].__clk t.registers.ff[3]._mqib t.registers.ack_dly.dly[2].y t.registers.ff[2]._sqi t.registers.ff[3].clk t.registers.ff[3].d t.registers.ff[1]._mqi t.registers.ff[12].clk t.registers.clk_dly.mu2[1]._y t.registers.ff[9]._mqi t.registers.ff[8]._mqib t.registers.clk_dly.mu2[0]._s t.registers.ff[10].q t.registers.ack_dly.dly[0]._y t.registers.ff[2].q t.registers.ff[4]._sqib t.registers.ack_dly.dly[0].a t.registers.ff[11].reset_B t.registers.ff[10]._sqi t.registers.ff[15]._clk t.registers.ff[13]._sqib t.registers.ff[9].clk t.registers.ff[14].reset_B t.registers.ff[7].d t.registers.ff[4].d t.registers.ff[7]._sqi t.registers.clk_dly.dly[1].__y t.registers.ff[15].clk t.registers.ff[6]._mqib t.registers.ff[2].__clk t.registers.ff[2]._sqib t.registers.clk_dly.mu2[0]._y t.registers.ff[9].reset_B t.registers.ff[10].d t.registers.ff[1].q t.registers.ff[3]._sqi t.registers.ff[5]._mqib t.registers.ff[6].d t.registers.ff[13].clk t.registers.ff[6]._clk t.registers.ff[5]._sqi t.registers.ff[12]._sqi t.registers.ff[9]._sqi t.registers.ff[4]._clk t.registers.ff[12]._mqi t.registers.ack_dly.dly[1]._y t.registers.ff[9].__clk t.registers.ff[14].d t.registers.ff[13]._mqi t.registers.ff[8].reset_B t.registers.ack_dly.dly[1].y t.registers.ff[0]._clk t.registers.ff[3]._sqib t.registers.ack_dly.and2[1]._y t.registers.ff[13].d t.registers.ff[1]._mqib t.registers.ff[0].__clk t.registers.ff[4].clk t.registers.ff[9].d t.registers.ack_dly.dly[0].y t.registers.clk_dly.dly[2].__y t.registers.ff[12].q t.registers.ff[10]._mqi t.registers.ff[5]._clk t.registers.ff[12].d t.registers.ff[15].d t.registers.ack_dly.dly[1].a t.registers.ff[9]._sqib t.registers.ff[2].clk t.registers.ff[4]._mqi t.registers.ff[10]._clk t.registers.ff[12]._mqib t.registers.ff[2]._mqib t.registers.ff[8].__clk t.registers.ff[11]._mqib t.registers.ff[1]._clk t.registers.ff[11]._sqib t.registers.ff[9].q t.registers.ff[3].q t.registers.ff[6].q t.registers.ff[10]._sqib t.registers.ff[2].d t.registers.ff[8]._mqi t.registers.ff[1].reset_B t.registers.ff[11].q t.registers.ff[12].reset_B t.registers.ack_dly.dly[2].__y t.registers.ff[6]._sqib t.registers.ff[11].clk t.registers.ff[0]._mqi t.registers.ff[12]._clk t.registers.ff[15]._sqi t.registers.ff[4]._sqi t.registers.ff[8]._sqib t.registers.ff[12].__clk t.registers.ff[6]._sqi t.registers.ff[13].__clk t.registers.ff[14]._mqib t.registers.ff[14].__clk t.registers.ack_dly.and2[0]._y t.registers.ack_dly.mu2[1]._s t.registers.ff[7].__clk t.registers.ff[14]._sqib t.registers.clk_dly.dly[2].___y t.registers.ff[14].clk t.registers.ff[11].d t.registers.ack_input_X.buf1._y t.registers.ff[0]._mqib t.registers.ff[15]._sqib t.registers.ff[0].reset_B t.registers.ack_dly.mu2[1]._y t.registers.ff[5].clk t.registers.ff[7].q t.registers.ff[3]._mqi t.registers.ack_dly.dly[0].__y t.registers.ff[13].reset_B t.registers.ff[8].clk t.registers.ff[15].__clk t.registers.ff[0]._sqi t.registers.ff[15]._mqi t.registers.ack_dly.mu2[0]._s t.registers.ff[7].reset_B 
+	    135041 Reset : 0
+	    135205 t._reset_B : 1  [by Reset:=0]
+	    135227 t.registers.reset_buf_BXX._y : 0  [by t._reset_B:=1]
+	    136074 t.registers._reset_mem_BX : 1  [by t.registers.reset_buf_BXX._y:=0]
+	    137400 t.registers.reset_buf_BX._y : 0  [by t._reset_B:=1]
+	    137533 t.registers._reset_BX : 1  [by t.registers.reset_buf_BX._y:=0]
+	    166202 t.registers.reset_bufarray.buf6._y : 0  [by t.registers._reset_mem_BX:=1]
+	    181864 t.registers._reset_mem_BXX[0] : 1  [by t.registers.reset_bufarray.buf6._y:=0]
+[1] reset completed
+	    181864 t.dly_cfg[0] : 1
+	    181864 t.dly_cfg[1] : 1
+	    181871 t.registers.clk_dly.mu2[1]._s : 0  [by t.dly_cfg[1]:=1]
+	    182085 t.registers.ack_dly.mu2[1]._s : 0  [by t.dly_cfg[1]:=1]
+	    182223 t.registers.ack_dly.mu2[0]._s : 0  [by t.dly_cfg[0]:=1]
+	    195980 t.registers.clk_dly.mu2[0]._s : 0  [by t.dly_cfg[0]:=1]
+	    196010 t.registers.clk_dly.mu2[0]._y : 1  [by t.registers.clk_dly.mu2[0]._s:=0]
+	    202723 t.registers.clk_dly._a[1] : 0  [by t.registers.clk_dly.mu2[0]._y:=1]
+	    260184 t.registers.clk_dly.and2[1]._y : 1  [by t.registers.clk_dly._a[1]:=0]
+	    260275 t.registers.clk_dly.dly[1].a : 0  [by t.registers.clk_dly.and2[1]._y:=1]
+	    262464 t.registers.clk_dly.dly[1]._y : 1  [by t.registers.clk_dly.dly[1].a:=0]
+	    262471 t.registers.clk_dly.dly[1].__y : 0  [by t.registers.clk_dly.dly[1]._y:=1]
+	    265258 t.registers.clk_dly.dly[1].___y : 1  [by t.registers.clk_dly.dly[1].__y:=0]
+	    265364 t.registers.clk_dly.dly[1].y : 0  [by t.registers.clk_dly.dly[1].___y:=1]
+	    265442 t.registers.clk_dly.dly[2]._y : 1  [by t.registers.clk_dly.dly[1].y:=0]
+	    265717 t.registers.clk_dly.dly[2].__y : 0  [by t.registers.clk_dly.dly[2]._y:=1]
+	    284713 t.registers.clk_dly.dly[2].___y : 1  [by t.registers.clk_dly.dly[2].__y:=0]
+	    285168 t.registers.clk_dly.dly[2].y : 0  [by t.registers.clk_dly.dly[2].___y:=1]
+	    285180 t.registers.clk_dly.mu2[1]._y : 1  [by t.registers.clk_dly.dly[2].y:=0]
+	    285584 t.registers._clock_temp : 0  [by t.registers.clk_dly.mu2[1]._y:=1]
+	    285596 t.registers.clk_X.buf1._y : 1  [by t.registers._clock_temp:=0]
+	    291512 t.registers._clock : 0  [by t.registers.clk_X.buf1._y:=1]
+	    295788 t.registers.ack_dly.and2[0]._y : 1  [by t.registers._clock:=0]
+	    298687 t.registers.ack_dly.dly[0].a : 0  [by t.registers.ack_dly.and2[0]._y:=1]
+	    302982 t.registers.ack_dly.dly[0]._y : 1  [by t.registers.ack_dly.dly[0].a:=0]
+	    302984 t.registers.ack_dly.dly[0].__y : 0  [by t.registers.ack_dly.dly[0]._y:=1]
+	    307519 t.registers.ack_dly.dly[0].___y : 1  [by t.registers.ack_dly.dly[0].__y:=0]
+	    308768 t.registers.ack_dly.dly[0].y : 0  [by t.registers.ack_dly.dly[0].___y:=1]
+	    312267 t.registers.ack_dly.mu2[0]._y : 1  [by t.registers.ack_dly.dly[0].y:=0]
+	    312433 t.registers.ack_dly._a[1] : 0  [by t.registers.ack_dly.mu2[0]._y:=1]
+	    312508 t.registers.ack_dly.and2[1]._y : 1  [by t.registers.ack_dly._a[1]:=0]
+	    312853 t.registers.ack_dly.dly[1].a : 0  [by t.registers.ack_dly.and2[1]._y:=1]
+	    312991 t.registers.ack_dly.dly[1]._y : 1  [by t.registers.ack_dly.dly[1].a:=0]
+	    318254 t.registers.ack_dly.dly[1].__y : 0  [by t.registers.ack_dly.dly[1]._y:=1]
+	    318256 t.registers.ack_dly.dly[1].___y : 1  [by t.registers.ack_dly.dly[1].__y:=0]
+	    362173 t.registers.ack_dly.dly[1].y : 0  [by t.registers.ack_dly.dly[1].___y:=1]
+	    362174 t.registers.ack_dly.dly[2]._y : 1  [by t.registers.ack_dly.dly[1].y:=0]
+	    362722 t.registers.ack_dly.dly[2].__y : 0  [by t.registers.ack_dly.dly[2]._y:=1]
+	    362733 t.registers.ack_dly.dly[2].___y : 1  [by t.registers.ack_dly.dly[2].__y:=0]
+	    363103 t.registers.ack_dly.dly[2].y : 0  [by t.registers.ack_dly.dly[2].___y:=1]
+	    363170 t.registers.ack_dly.mu2[1]._y : 1  [by t.registers.ack_dly.dly[2].y:=0]
+	    365811 t.registers._in_a_temp : 0  [by t.registers.ack_dly.mu2[1]._y:=1]
+	    365827 t.registers.ack_input_X.buf1._y : 1  [by t.registers._in_a_temp:=0]
+	    370389 t.in.a : 0  [by t.registers.ack_input_X.buf1._y:=1]
+[2] delay line set
+	    370389 t.in.d.d[0].t : 1
+	    370389 t.in.d.d[4].f : 1
+	    370389 t.registers.atree[0].in[1] : 1
+	    370389 t.registers.atree[1].in[0] : 1
+	    370389 t.in.d.d[3].f : 1
+	    370391 t.registers.atree[5].and2s[0]._y : 0  [by t.registers.atree[1].in[0]:=1]
+	    370394 t.registers._out_encoder[5] : 1  [by t.registers.atree[5].and2s[0]._y:=0]
+	    370917 t.registers.val_input.OR2_tf[0]._y : 0  [by t.in.d.d[0].t:=1]
+	    370946 t.registers.val_input.ct.in[0] : 1  [by t.registers.val_input.OR2_tf[0]._y:=0]
+	    372824 t.registers.val_input.OR2_tf[4]._y : 0  [by t.in.d.d[4].f:=1]
+	    373141 t.registers.val_input.ct.in[4] : 1  [by t.registers.val_input.OR2_tf[4]._y:=0]
+	    383430 t.registers.atree[1].and2s[0]._y : 0  [by t.registers.atree[1].in[0]:=1]
+	    385031 t.registers._out_encoder[1] : 1  [by t.registers.atree[1].and2s[0]._y:=0]
+	    394314 t.registers.val_input.OR2_tf[1]._y : 0  [by t.registers.atree[1].in[0]:=1]
+	    394467 t.registers.val_input.ct.in[1] : 1  [by t.registers.val_input.OR2_tf[1]._y:=0]
+	    394511 t.registers.val_input.ct.C2Els[0]._y : 0  [by t.registers.val_input.ct.in[1]:=1]
+	    397269 t.registers.val_input.OR2_tf[2]._y : 0  [by t.registers.atree[0].in[1]:=1]
+	    397272 t.registers.val_input.ct.tmp[5] : 1  [by t.registers.val_input.ct.C2Els[0]._y:=0]
+	    410952 t.registers.val_input.ct.in[2] : 1  [by t.registers.val_input.OR2_tf[2]._y:=0]
+	    431347 t.registers.val_input.OR2_tf[3]._y : 0  [by t.in.d.d[3].f:=1]
+	    431348 t.registers.val_input.ct.in[3] : 1  [by t.registers.val_input.OR2_tf[3]._y:=0]
+	    431565 t.registers.val_input.ct.C3Els[0]._y : 0  [by t.registers.val_input.ct.in[3]:=1]
+	    431587 t.registers.val_input.ct.tmp[6] : 1  [by t.registers.val_input.ct.C3Els[0]._y:=0]
+	    431588 t.registers.val_input.ct.C2Els[1]._y : 0  [by t.registers.val_input.ct.tmp[6]:=1]
+	    433169 t.registers._in_v_temp : 1  [by t.registers.val_input.ct.C2Els[1]._y:=0]
+	    433328 t.registers.val_input_X.buf1._y : 0  [by t.registers._in_v_temp:=1]
+	    442514 t.registers.clk_dly.and2[0]._y : 0  [by t.registers._in_v_temp:=1]
+	    443801 t.registers.clk_dly.dly[0].a : 1  [by t.registers.clk_dly.and2[0]._y:=0]
+	    446033 t.registers.clk_dly.dly[0]._y : 0  [by t.registers.clk_dly.dly[0].a:=1]
+	    446178 t.registers.clk_dly.dly[0].__y : 1  [by t.registers.clk_dly.dly[0]._y:=0]
+	    449010 t.registers.clk_dly.dly[0].___y : 0  [by t.registers.clk_dly.dly[0].__y:=1]
+	    453004 t.in.v : 1  [by t.registers.val_input_X.buf1._y:=0]
+	    455364 t.registers.clk_dly.dly[0].y : 1  [by t.registers.clk_dly.dly[0].___y:=0]
+	    455365 t.registers.clk_dly.mu2[0]._y : 0  [by t.registers.clk_dly.dly[0].y:=1]
+	    494649 t.registers.clk_dly._a[1] : 1  [by t.registers.clk_dly.mu2[0]._y:=0]
+	    494811 t.registers.clk_dly.and2[1]._y : 0  [by t.registers.clk_dly._a[1]:=1]
+	    502180 t.registers.clk_dly.dly[1].a : 1  [by t.registers.clk_dly.and2[1]._y:=0]
+	    502194 t.registers.clk_dly.dly[1]._y : 0  [by t.registers.clk_dly.dly[1].a:=1]
+	    502201 t.registers.clk_dly.dly[1].__y : 1  [by t.registers.clk_dly.dly[1]._y:=0]
+	    502361 t.registers.clk_dly.dly[1].___y : 0  [by t.registers.clk_dly.dly[1].__y:=1]
+	    523918 t.registers.clk_dly.dly[1].y : 1  [by t.registers.clk_dly.dly[1].___y:=0]
+	    523919 t.registers.clk_dly.dly[2]._y : 0  [by t.registers.clk_dly.dly[1].y:=1]
+	    523920 t.registers.clk_dly.dly[2].__y : 1  [by t.registers.clk_dly.dly[2]._y:=0]
+	    523921 t.registers.clk_dly.dly[2].___y : 0  [by t.registers.clk_dly.dly[2].__y:=1]
+	    526164 t.registers.clk_dly.dly[2].y : 1  [by t.registers.clk_dly.dly[2].___y:=0]
+	    526351 t.registers.clk_dly.mu2[1]._y : 0  [by t.registers.clk_dly.dly[2].y:=1]
+	    526352 t.registers._clock_temp : 1  [by t.registers.clk_dly.mu2[1]._y:=0]
+	    530534 t.registers.clk_X.buf1._y : 0  [by t.registers._clock_temp:=1]
+	    565316 t.registers._clock : 1  [by t.registers.clk_X.buf1._y:=0]
+	    565317 t.registers.and_encoder[5]._y : 0  [by t.registers._clock:=1]
+	    565321 t.registers.ack_dly.and2[0]._y : 0  [by t.registers._clock:=1]
+	    565322 t.registers.ack_dly.dly[0].a : 1  [by t.registers.ack_dly.and2[0]._y:=0]
+	    565339 t.registers.ack_dly.dly[0]._y : 0  [by t.registers.ack_dly.dly[0].a:=1]
+	    566169 t.registers.and_encoder[1]._y : 0  [by t.registers._clock:=1]
+	    566208 t.registers._clock_word_temp[5] : 1  [by t.registers.and_encoder[5]._y:=0]
+	    566211 t.registers.clock_buffer[5].buf1._y : 0  [by t.registers._clock_word_temp[5]:=1]
+	    567152 t.registers.clock_buffer[5].out[0] : 1  [by t.registers.clock_buffer[5].buf1._y:=0]
+	    567912 t.registers.ack_dly.dly[0].__y : 1  [by t.registers.ack_dly.dly[0]._y:=0]
+	    574530 t.registers._clock_word_temp[1] : 1  [by t.registers.and_encoder[1]._y:=0]
+	    574531 t.registers.clock_buffer[1].buf1._y : 0  [by t.registers._clock_word_temp[1]:=1]
+	    574573 t.registers.clock_buffer[1].out[0] : 1  [by t.registers.clock_buffer[1].buf1._y:=0]
+	    626874 t.registers.ack_dly.dly[0].___y : 0  [by t.registers.ack_dly.dly[0].__y:=1]
+	    629691 t.registers.ack_dly.dly[0].y : 1  [by t.registers.ack_dly.dly[0].___y:=0]
+	    643424 t.registers.ack_dly.mu2[0]._y : 0  [by t.registers.ack_dly.dly[0].y:=1]
+	    643519 t.registers.ack_dly._a[1] : 1  [by t.registers.ack_dly.mu2[0]._y:=0]
+	    643854 t.registers.ack_dly.and2[1]._y : 0  [by t.registers.ack_dly._a[1]:=1]
+	    643862 t.registers.ack_dly.dly[1].a : 1  [by t.registers.ack_dly.and2[1]._y:=0]
+	    643896 t.registers.ack_dly.dly[1]._y : 0  [by t.registers.ack_dly.dly[1].a:=1]
+	    657783 t.registers.ack_dly.dly[1].__y : 1  [by t.registers.ack_dly.dly[1]._y:=0]
+	    658701 t.registers.ack_dly.dly[1].___y : 0  [by t.registers.ack_dly.dly[1].__y:=1]
+	    658705 t.registers.ack_dly.dly[1].y : 1  [by t.registers.ack_dly.dly[1].___y:=0]
+	    705083 t.registers.ack_dly.dly[2]._y : 0  [by t.registers.ack_dly.dly[1].y:=1]
+	    707481 t.registers.ack_dly.dly[2].__y : 1  [by t.registers.ack_dly.dly[2]._y:=0]
+	    710696 t.registers.ack_dly.dly[2].___y : 0  [by t.registers.ack_dly.dly[2].__y:=1]
+	    757815 t.registers.ack_dly.dly[2].y : 1  [by t.registers.ack_dly.dly[2].___y:=0]
+	    757863 t.registers.ack_dly.mu2[1]._y : 0  [by t.registers.ack_dly.dly[2].y:=1]
+	    757866 t.registers._in_a_temp : 1  [by t.registers.ack_dly.mu2[1]._y:=0]
+	    758044 t.registers.ack_input_X.buf1._y : 0  [by t.registers._in_a_temp:=1]
+	    779021 t.in.a : 1  [by t.registers.ack_input_X.buf1._y:=0]
+WRONG ASSERT:	"t.registers._out_encoder[0]" has value 0 and not 1.
+WRONG ASSERT:	"t.registers._out_encoder[1]" has value 1 and not 0.
+	    779021 t.in.d.d[0].t : 0
+	    779021 t.in.d.d[4].f : 0
+	    779021 t.registers.atree[0].in[1] : 0
+	    779021 t.registers.atree[1].in[0] : 0
+	    779021 t.in.d.d[3].f : 0
+	    779022 t.registers.val_input.OR2_tf[3]._y : 1  [by t.in.d.d[3].f:=0]
+	    779095 t.registers.val_input.ct.in[3] : 0  [by t.registers.val_input.OR2_tf[3]._y:=1]
+	    779194 t.registers.atree[5].and2s[0]._y : 1  [by t.registers.atree[0].in[1]:=0]
+	    779198 t.registers._out_encoder[5] : 0  [by t.registers.atree[5].and2s[0]._y:=1]
+	    779205 t.registers.val_input.OR2_tf[1]._y : 1  [by t.registers.atree[1].in[0]:=0]
+	    779301 t.registers.val_input.ct.in[1] : 0  [by t.registers.val_input.OR2_tf[1]._y:=1]
+	    779848 t.registers.atree[1].and2s[0]._y : 1  [by t.registers.atree[0].in[1]:=0]
+	    779984 t.registers._out_encoder[1] : 0  [by t.registers.atree[1].and2s[0]._y:=1]
+	    779985 t.registers.and_encoder[1]._y : 1  [by t.registers._out_encoder[1]:=0]
+	    784972 t.registers.val_input.OR2_tf[4]._y : 1  [by t.in.d.d[4].f:=0]
+	    785213 t.registers.val_input.ct.in[4] : 0  [by t.registers.val_input.OR2_tf[4]._y:=1]
+	    790920 t.registers.val_input.OR2_tf[0]._y : 1  [by t.in.d.d[0].t:=0]
+	    794879 t.registers.val_input.ct.in[0] : 0  [by t.registers.val_input.OR2_tf[0]._y:=1]
+	    794891 t.registers.val_input.ct.C2Els[0]._y : 1  [by t.registers.val_input.ct.in[0]:=0]
+	    798791 t.registers.val_input.ct.tmp[5] : 0  [by t.registers.val_input.ct.C2Els[0]._y:=1]
+	    799031 t.registers._clock_word_temp[1] : 0  [by t.registers.and_encoder[1]._y:=1]
+	    800060 t.registers.clock_buffer[1].buf1._y : 1  [by t.registers._clock_word_temp[1]:=0]
+	    800061 t.registers.clock_buffer[1].out[0] : 0  [by t.registers.clock_buffer[1].buf1._y:=1]
+	    816486 t.registers.and_encoder[5]._y : 1  [by t.registers._out_encoder[5]:=0]
+	    816542 t.registers._clock_word_temp[5] : 0  [by t.registers.and_encoder[5]._y:=1]
+	    818506 t.registers.val_input.OR2_tf[2]._y : 1  [by t.registers.atree[0].in[1]:=0]
+	    818507 t.registers.val_input.ct.in[2] : 0  [by t.registers.val_input.OR2_tf[2]._y:=1]
+	    818544 t.registers.val_input.ct.C3Els[0]._y : 1  [by t.registers.val_input.ct.in[2]:=0]
+	    841919 t.registers.val_input.ct.tmp[6] : 0  [by t.registers.val_input.ct.C3Els[0]._y:=1]
+	    841920 t.registers.val_input.ct.C2Els[1]._y : 1  [by t.registers.val_input.ct.tmp[6]:=0]
+	    845484 t.registers._in_v_temp : 0  [by t.registers.val_input.ct.C2Els[1]._y:=1]
+	    845497 t.registers.val_input_X.buf1._y : 1  [by t.registers._in_v_temp:=0]
+	    847176 t.registers.clk_dly.and2[0]._y : 1  [by t.registers._in_v_temp:=0]
+	    847533 t.registers.clk_dly.dly[0].a : 0  [by t.registers.clk_dly.and2[0]._y:=1]
+	    847558 t.registers.clk_dly.dly[0]._y : 1  [by t.registers.clk_dly.dly[0].a:=0]
+	    847579 t.registers.clk_dly.dly[0].__y : 0  [by t.registers.clk_dly.dly[0]._y:=1]
+	    847580 t.registers.clk_dly.dly[0].___y : 1  [by t.registers.clk_dly.dly[0].__y:=0]
+	    857228 t.registers.clk_dly.dly[0].y : 0  [by t.registers.clk_dly.dly[0].___y:=1]
+	    857229 t.registers.clk_dly.mu2[0]._y : 1  [by t.registers.clk_dly.dly[0].y:=0]
+	    857230 t.registers.clk_dly._a[1] : 0  [by t.registers.clk_dly.mu2[0]._y:=1]
+	    857391 t.registers.clk_dly.and2[1]._y : 1  [by t.registers.clk_dly._a[1]:=0]
+	    858428 t.registers.clk_dly.dly[1].a : 0  [by t.registers.clk_dly.and2[1]._y:=1]
+	    858433 t.registers.clk_dly.dly[1]._y : 1  [by t.registers.clk_dly.dly[1].a:=0]
+	    859014 t.registers.clk_dly.dly[1].__y : 0  [by t.registers.clk_dly.dly[1]._y:=1]
+	    859422 t.registers.clk_dly.dly[1].___y : 1  [by t.registers.clk_dly.dly[1].__y:=0]
+	    859433 t.registers.clk_dly.dly[1].y : 0  [by t.registers.clk_dly.dly[1].___y:=1]
+	    860480 t.registers.clk_dly.dly[2]._y : 1  [by t.registers.clk_dly.dly[1].y:=0]
+	    860494 t.registers.clk_dly.dly[2].__y : 0  [by t.registers.clk_dly.dly[2]._y:=1]
+	    860512 t.registers.clk_dly.dly[2].___y : 1  [by t.registers.clk_dly.dly[2].__y:=0]
+	    860516 t.registers.clk_dly.dly[2].y : 0  [by t.registers.clk_dly.dly[2].___y:=1]
+	    860620 t.registers.clk_dly.mu2[1]._y : 1  [by t.registers.clk_dly.dly[2].y:=0]
+	    861548 t.registers.clock_buffer[5].buf1._y : 1  [by t.registers._clock_word_temp[5]:=0]
+	    862481 t.in.v : 0  [by t.registers.val_input_X.buf1._y:=1]
+	    862752 t.registers.clock_buffer[5].out[0] : 0  [by t.registers.clock_buffer[5].buf1._y:=1]
+	    892064 t.registers._clock_temp : 0  [by t.registers.clk_dly.mu2[1]._y:=1]
+	    900519 t.registers.clk_X.buf1._y : 1  [by t.registers._clock_temp:=0]
+	    900747 t.registers._clock : 0  [by t.registers.clk_X.buf1._y:=1]
+	    901590 t.registers.ack_dly.and2[0]._y : 1  [by t.registers._clock:=0]
+	    903049 t.registers.ack_dly.dly[0].a : 0  [by t.registers.ack_dly.and2[0]._y:=1]
+	    903119 t.registers.ack_dly.dly[0]._y : 1  [by t.registers.ack_dly.dly[0].a:=0]
+	    953541 t.registers.ack_dly.dly[0].__y : 0  [by t.registers.ack_dly.dly[0]._y:=1]
+	    953552 t.registers.ack_dly.dly[0].___y : 1  [by t.registers.ack_dly.dly[0].__y:=0]
+	    953555 t.registers.ack_dly.dly[0].y : 0  [by t.registers.ack_dly.dly[0].___y:=1]
+	    953609 t.registers.ack_dly.mu2[0]._y : 1  [by t.registers.ack_dly.dly[0].y:=0]
+	    954757 t.registers.ack_dly._a[1] : 0  [by t.registers.ack_dly.mu2[0]._y:=1]
+	    955918 t.registers.ack_dly.and2[1]._y : 1  [by t.registers.ack_dly._a[1]:=0]
+	    964570 t.registers.ack_dly.dly[1].a : 0  [by t.registers.ack_dly.and2[1]._y:=1]
+	    964651 t.registers.ack_dly.dly[1]._y : 1  [by t.registers.ack_dly.dly[1].a:=0]
+	    975728 t.registers.ack_dly.dly[1].__y : 0  [by t.registers.ack_dly.dly[1]._y:=1]
+	    993711 t.registers.ack_dly.dly[1].___y : 1  [by t.registers.ack_dly.dly[1].__y:=0]
+	    993803 t.registers.ack_dly.dly[1].y : 0  [by t.registers.ack_dly.dly[1].___y:=1]
+	   1002114 t.registers.ack_dly.dly[2]._y : 1  [by t.registers.ack_dly.dly[1].y:=0]
+	   1003858 t.registers.ack_dly.dly[2].__y : 0  [by t.registers.ack_dly.dly[2]._y:=1]
+	   1004471 t.registers.ack_dly.dly[2].___y : 1  [by t.registers.ack_dly.dly[2].__y:=0]
+	   1018493 t.registers.ack_dly.dly[2].y : 0  [by t.registers.ack_dly.dly[2].___y:=1]
+	   1018538 t.registers.ack_dly.mu2[1]._y : 1  [by t.registers.ack_dly.dly[2].y:=0]
+	   1019535 t.registers._in_a_temp : 0  [by t.registers.ack_dly.mu2[1]._y:=1]
+	   1021184 t.registers.ack_input_X.buf1._y : 1  [by t.registers._in_a_temp:=0]
+	   1021709 t.in.a : 0  [by t.registers.ack_input_X.buf1._y:=1]
+[3] clock checked

test/unit_tests/register_write/test.act

@@ -30,13 +30,13 @@ import "../../dataflow_neuro/registers.act";
 import globals;
 
 open tmpl::dataflow_neuro;
-
+// 2 bits encoder, 2 bits long words, 2 delays????
-defproc register_test (avMx1of2<1+2+2> in; d1of<2> data[2<<2]){
+defproc register_test (avMx1of2<1+2+2> in; d1of<2> data[2<<2]; bool? dly_cfg[2]){
 
     register_rw<2,2,2> registers(.in=in,.data = data);
     //Low active Reset 
     bool _reset_B; 
-    power supply;
+    power _supply;
     prs {
     	Reset => _reset_B-
     }
@@ -44,7 +44,8 @@ defproc register_test (avMx1of2<1+2+2> in; d1of<2> data[2<<2]){
     _supply.vss = GND;
     _supply.vdd = Vdd;
     registers.reset_B = _reset_B;
-    registers.reset_B_mem = _reset_B;
+    registers.reset_mem_B = _reset_B;
+    registers.dly_cfg = dly_cfg;
     
 }
 

test/unit_tests/register_write/test.prsim

@@ -1,8 +1,39 @@
 watchall
 system "echo '[0] start test'"
 set Reset 1
-set-qdi-channel-neutral "t.in" 2
+
+
+set-qdi-channel-neutral "t.in" 5
+set t.data[0].d[0] 0
+set t.data[0].d[1] 0
+set t.data[1].d[0] 0
+set t.data[1].d[1] 0
 cycle
 status X
 mode run
+assert-qdi-channel-neutral "t.in" 5
+assert t.data[0].d[0] 0
+assert t.data[0].d[1] 0
+assert t.data[1].d[0] 0
+assert t.data[1].d[1] 0
+set Reset 0
+cycle
 system "echo '[1] reset completed'"
+# Set delay config lines
+set t.dly_cfg[0] 1
+set t.dly_cfg[1] 1
+cycle
+assert-qdi-channel-neutral "t.in" 5
+system "echo '[2] delay line set'"
+set-qdi-channel-valid "t.in" 5 3
+cycle
+assert-qdi-channel-valid "t.in" 5 3
+assert t.registers._clock 1
+assert t.registers._out_encoder[0] 1
+assert t.registers._out_encoder[1] 0
+set-qdi-channel-neutral "t.in" 5
+cycle
+assert t.registers._clock 0
+system "echo '[3] clock checked'"
+
+