Merge remote-tracking branch 'origin/dev' into dev
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@ -99,6 +99,18 @@ namespace tmpl {
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sizing { _y {-6,2}; y {-12,4} }
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}
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/*-- delay cells --*/
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// TODO properly
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export defcell DLY4_X1(bool! y; bool? a, vdd, vss)
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{
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bool _y;
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prs {
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a => _y-
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_y => y-
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}
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}
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/*-- simple gates --*/
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@ -151,6 +151,27 @@ namespace tmpl {
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f_buf_func[i].sr_B = _reset_BXX[i];
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)
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}
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// A template creating a FIFO of M buffers with N bits each
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export template<pint N;pint M>
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defproc fifo(avMx1of2<N> in; avMx1of2<N> out; bool? reset_B; power supply)
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{
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buffer<N> fifo_element[M];
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bool _reset_BXX[M];
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fifo_element[0].in = in ;
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fifo_element[0].supply = supply;
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fifo_element[0].reset_B = _reset_BXX[0];
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(i:1..M-1:
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fifo_element[i].in = fifo_element[i-1].out;
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fifo_element[i].supply = supply;
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fifo_element[i].reset_B = _reset_BXX[i];
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)
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fifo_element[N-1].out = out;
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// reset buffers
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bool _reset_BX;
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BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
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sigbuf<M> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
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}
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/**
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* Buffer_S template.
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@ -489,12 +510,18 @@ namespace tmpl {
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export template<pint N>
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defproc merge (avMx1of2<N> in1; avMx1of2<N> in2; avMx1of2<N> out ; bool? reset_B; power supply) {
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//out acknowledge sigbuffer and inverter
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bool _out_a_B,_out_a_BX[2*N];
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INV_X1 out_a_inverter(.a = out.a, .y = _out_a_B);
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sigbuf<2*N> out_a_buffer(.in = _out_a_B,.out = _out_a_BX,.supply=supply);
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//control
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bool _in1_a_B,_in2_a_B,_en, _reset_BX,_reset_BXX[2*N];
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bool _in1_arb,_in2_arb,_out_a_X[2*N+1];
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bool _in1_a_B,_in2_a_B,_en,_en_X[2*N], _reset_BX,_reset_BXX[2*N];
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bool _in1_arb,_in2_arb,_in1_arb_X[2*N],_in2_arb_X[2*N];
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A_4C_RB_X4 in1ack_ctl(.c1=_in1_arb,.c2=_en,.c3=in1.v,.c4=out.v,.y=in1.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
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A_4C_RB_X4 in2ack_ctl(.c1=_in2_arb,.c2=_en,.c3=in2.v,.c4=out.v,.y=in2.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
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A_4P1N1N_X1 en_ctl(.p1 = in1.a,.p2=in2.a,.p3=_out_a_X[N],.p4 = out.v, .n1 = in1.a,.y = _en,.vdd=supply.vdd,.vss=supply.vss);
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A_4P1N1N_X1 en_ctl(.p1 = in1.a,.p2=in2.a,.p3=out.a,.p4 = out.v, .n1 = in1.a,.n2 = in2.a,.y = _en,.vdd=supply.vdd,.vss=supply.vss);
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sigbuf<2*N> en_buffer(.in = _en,.out = _en_X,.supply=supply);
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INV_X1 in1ack_ctl_inv(.a=in1.a,.y=_in1_a_B,.vdd=supply.vdd,.vss=supply.vss);
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INV_X1 in2ack_ctl_inv(.a=in2.a,.y=_in2_a_B,.vdd=supply.vdd,.vss=supply.vss);
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@ -504,53 +531,47 @@ namespace tmpl {
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//validity
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a1of1 _in1_temp,_in2_temp,_out_temp;
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bool _in1_arb2function,_in2_arb2function;
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bool _in1_arb2function_X[2*N],_in2_arb2function_X[2*N];
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bool _in1_arb_temp,_in2_arb_temp;
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vtree<N> vc1(.in=in1.d,.out=in1.v,.supply=supply);
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vtree<N> vc2(.in=in2.d,.out=in2.v,.supply=supply);
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arbiter_handshake validity_arb(.in1 = _in1_temp,.in2 = _in2_temp,.out =_out_temp);
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arbiter_handshake validity_arb(.in1 = _in1_temp,.in2 = _in2_temp,.out =_out_temp, .supply = supply);
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_in1_temp.r = in1.v;
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_in2_temp.r = in2.v;
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_in1_temp.a = _in1_arb;
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_in1_temp.a = _in2_arb;
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_in1_temp.a = _in1_arb_temp;
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_in2_temp.a = _in2_arb_temp;
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_out_temp.r = _out_temp.a;
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AND2_X1 AND_arb1(.a = _in2_a_B,.b = _in1_arb, .y = _in1_arb2function);
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AND2_X1 AND_arb2(.a = _in1_a_B,.b = _in2_arb, .y = _in2_arb2function);
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sigbuf<2*N> arb2function1(.in = _in1_arb2function,.out = _in1_arb2function_X);
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sigbuf<2*N> arb2function2(.in = _in2_arb2function,.out = _in2_arb2function_X);
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AND2_X1 AND_arb1(.a = _in2_a_B,.b = _in1_arb_temp, .y = _in1_arb);
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AND2_X1 AND_arb2(.a = _in1_a_B,.b = _in2_arb_temp, .y = _in2_arb);
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sigbuf<2*N> arb2function1(.in = _in1_arb,.out = _in1_arb_X,.supply=supply);
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sigbuf<2*N> arb2function2(.in = _in2_arb,.out = _in2_arb_X,.supply=supply);
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//function
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A_2C2N2N_R_X1 merge_func_t[N];
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A_2C2N2N_R_X1 merge_func_f[N];
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sigbuf<N*2+1> buf_out_a(.in = out.a,.out = _out_a_X);
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buf_out_a.supply=supply;
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buf_out_a.supply=supply;
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A_2C2N2N_RB_X1 merge_func_t[N];
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A_2C2N2N_RB_X1 merge_func_f[N];
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(i:N:
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merge_func_t[i].c1 = _en;
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merge_func_t[i].c2 = _out_a_X[i];
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merge_func_t[i].n1 = _in1_arb2function_X[i];
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merge_func_t[i].c1 = _en_X[i];
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merge_func_t[i].c2 = _out_a_BX[i];
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merge_func_t[i].n1 = _in1_arb_X[i];
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merge_func_t[i].n2 = in1.d.d[i].t;
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merge_func_t[i].n3 = _in2_arb2function_X[i];
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merge_func_t[i].n3 = _in2_arb_X[i];
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merge_func_t[i].n4 = in2.d.d[i].t;
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merge_func_t[i].y = out.d.d[i].t;
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merge_func_t[i].vdd=supply.vdd;
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merge_func_t[i].vss=supply.vss;
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merge_func_t[i].pr_B = _reset_BXX[i+N-1];
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merge_func_t[i].sr_B = _reset_BXX[i+N-1];
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merge_func_t[i].pr_B = _reset_BXX[i];
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merge_func_t[i].sr_B = _reset_BXX[i];
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merge_func_f[i].c1 = _en;
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merge_func_f[i].c2 = _out_a_X[i+N-1];
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merge_func_f[i].n1 = _in1_arb2function_X[i+N-1];
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merge_func_f[i].c1 = _en_X[i+N];
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merge_func_f[i].c2 = _out_a_BX[i+N];
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merge_func_f[i].n1 = _in1_arb_X[i+N];
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merge_func_f[i].n2 = in1.d.d[i].f;
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merge_func_f[i].n3 = _in2_arb2function_X[i+N-1];
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merge_func_f[i].n3 = _in2_arb_X[i+N];
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merge_func_f[i].n4 = in2.d.d[i].f;
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merge_func_f[i].y = out.d.d[i].f;
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merge_func_f[i].vdd=supply.vdd;
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merge_func_f[i].vss=supply.vss;
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merge_func_f[i].pr_B = _reset_BXX[i];
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merge_func_f[i].sr_B = _reset_BXX[i];
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merge_func_f[i].pr_B = _reset_BXX[i+N];
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merge_func_f[i].sr_B = _reset_BXX[i+N];
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)
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}
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@ -571,6 +592,7 @@ namespace tmpl {
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//reset buffers
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BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
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}
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// A template creating a FIFO of N buffers tokens
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export template<pint N>
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defproc fifo_t(a1of1 in; a1of1 out; bool? reset_B; power supply)
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{
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@ -594,4 +616,59 @@ namespace tmpl {
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BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
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sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
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}
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// Programmable delay line.
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// N is the number of layers,
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// the longest layer having 2**N DLY elements
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export template<pint N>
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defproc delayprog (bool! y; bool? a, s[N]; power supply)
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{
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{ N >= 0 : "What?" };
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{ N < 9 : "Delay prog size is given in 2**N. Given N is too big." };
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AND2_X1 and2[N];
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MUX2_X1 mu2[N];
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DLY4_X1 dly[(1<<N) -1];
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bool _a[N+1]; // Holds the input to each row
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_a[0] = a;
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pint i_delay;
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i_delay = 0; // Index of the last connected delay element
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(i:0..N-1:
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// For each row
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and2[i].a = _a[i];
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and2[i].b = s[i];
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// Delays
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dly[i_delay].a = and2[i].y;
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i_delay = i_delay + 1;
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(j:1..i-1:
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dly[i_delay].a = dly[i_delay-1].y;
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i_delay = i_delay +1;
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)
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// Mux
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mu2[i].a = _a[i];
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mu2[i].s = s[i];
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dly[i_delay-1].y = mu2[i].b;
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_a[i+1] = mu2[i].y;
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)
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y = mu2[N-1].y;
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// Connect everything to vdd/gnd
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(i:N:and2[i].vdd = supply.vdd;)
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(i:N:mu2[i].vdd = supply.vdd;)
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(i:((1<<N)-1):dly[i].vdd = supply.vdd;)
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(i:N:and2[i].vss = supply.vss;)
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(i:N:mu2[i].vss = supply.vss;)
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(i:((1<<N)-1):dly[i].vss = supply.vss;)
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}
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}}
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