added some watches

test/unit_tests/texel_dualcore_glue_noread/test.prsim

@@ -4,6 +4,55 @@ watch c.c1_synapses[0].a
 watch c.c1_neurons[0].r
 watch c.c1_neurons[0].a
 
+watch c.c1_reg_data[0].d[0].t
+watch c.c1_reg_data[0].d[0].f
+watch c.c1_reg_data[0].d[1].t
+watch c.c1_reg_data[0].d[1].f
+watch c.c1_reg_data[0].d[2].t
+watch c.c1_reg_data[0].d[2].f
+watch c.c1_reg_data[0].d[3].t
+watch c.c1_reg_data[0].d[3].f
+watch c.c1_reg_data[0].d[4].t
+watch c.c1_reg_data[0].d[4].f
+watch c.c1_reg_data[0].d[5].t
+watch c.c1_reg_data[0].d[5].f
+watch c.c1_reg_data[0].d[6].t
+watch c.c1_reg_data[0].d[6].f
+watch c.c1_reg_data[0].d[7].t
+watch c.c1_reg_data[0].d[7].f
+watch c.c1_reg_data[0].d[8].t
+watch c.c1_reg_data[0].d[8].f
+watch c.c1_reg_data[0].d[9].t
+watch c.c1_reg_data[0].d[9].f
+watch c.c1_reg_data[0].d[10].t
+watch c.c1_reg_data[0].d[10].f
+watch c.c1_reg_data[0].d[11].t
+watch c.c1_reg_data[0].d[11].f
+watch c.c1_reg_data[0].d[12].t
+watch c.c1_reg_data[0].d[12].f
+watch c.c1_reg_data[0].d[13].t
+watch c.c1_reg_data[0].d[13].f
+watch c.c1_reg_data[0].d[14].t
+watch c.c1_reg_data[0].d[14].f
+watch c.c1_reg_data[0].d[15].t
+watch c.c1_reg_data[0].d[15].f
+watch c.c1_reg_data[0].d[16].t
+watch c.c1_reg_data[0].d[16].f
+watch c.c1_reg_data[0].d[17].t
+watch c.c1_reg_data[0].d[17].f
+watch c.c1_reg_data[0].d[18].t
+watch c.c1_reg_data[0].d[18].f
+watch c.c1_reg_data[0].d[19].t
+watch c.c1_reg_data[0].d[19].f
+watch c.c1_reg_data[0].d[20].t
+watch c.c1_reg_data[0].d[20].f
+watch c.c1_reg_data[0].d[21].t
+watch c.c1_reg_data[0].d[21].f
+watch c.c1_reg_data[0].d[22].t
+watch c.c1_reg_data[0].d[22].f
+watch c.c1_reg_data[0].d[23].t
+watch c.c1_reg_data[0].d[23].f
+
 
 set c.bd_dly_cfg[0] 1
 set c.bd_dly_cfg[1] 1
@@ -53,8 +102,7 @@ assert c.in.a 0
 
 
     
-# Expect register read packet to arrive
-# Receiving output 0 from register 0
+# loopback arrives
 assert-bd-channel-valid "c.out" 32 1610613058
 set c.out.a 1
 cycle