added keeps to output AMZO lines
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@ -219,6 +219,7 @@ defproc texel_core (avMx1of2<N_IN> in, out;
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// Create TBUFs for each synapse column,
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// Create TBUFs for each synapse column,
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// ctrl wired to mon line (first in each 4).
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// ctrl wired to mon line (first in each 4).
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TBUF_X4 syn_x_AMZI_tbuf[N_SYN_X * N_MON_AMZO_PER_SYN];
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TBUF_X4 syn_x_AMZI_tbuf[N_SYN_X * N_MON_AMZO_PER_SYN];
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KEEP syn_AMZO_keeps[N_MON_AMZO_PER_SYN];
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sigbuf_boolarray<N_MON_AMZO_PER_SYN, 40> syn_mon_AMZO_sb(.out = syn_mon_AMZO, .supply = supply);
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sigbuf_boolarray<N_MON_AMZO_PER_SYN, 40> syn_mon_AMZO_sb(.out = syn_mon_AMZO, .supply = supply);
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(j:N_MON_AMZO_PER_SYN:
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(j:N_MON_AMZO_PER_SYN:
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(i:N_SYN_X:
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(i:N_SYN_X:
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@ -227,12 +228,18 @@ defproc texel_core (avMx1of2<N_IN> in, out;
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syn_x_AMZI_tbuf[index].en = syn_mon_x[i*4];
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syn_x_AMZI_tbuf[index].en = syn_mon_x[i*4];
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syn_x_AMZI_tbuf[index].y = syn_mon_AMZO_sb.in[j];
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syn_x_AMZI_tbuf[index].y = syn_mon_AMZO_sb.in[j];
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)
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)
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syn_AMZO_keeps[j].y = syn_mon_AMZO_sb.in[j];
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syn_AMZO_keeps[j].vdd = supply.vdd;
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syn_AMZO_keeps[j].vss = supply.vss;
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)
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)
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// Create TBUFs for each neuron column,
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// Create TBUFs for each neuron column, and add keeps.
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// ctrl wired to mon line (first in each 4).
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// ctrl wired to mon line (first in each 4).
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TBUF_X4 nrn_x_AMZI_tbuf[N_NRN_X * N_MON_AMZO_PER_NRN];
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TBUF_X4 nrn_x_AMZI_tbuf[N_NRN_X * N_MON_AMZO_PER_NRN];
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KEEP nrn_AMZO_keeps[N_MON_AMZO_PER_NRN];
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sigbuf_boolarray<N_MON_AMZO_PER_NRN, 40> nrn_mon_AMZO_sb(.out = nrn_mon_AMZO, .supply = supply);
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sigbuf_boolarray<N_MON_AMZO_PER_NRN, 40> nrn_mon_AMZO_sb(.out = nrn_mon_AMZO, .supply = supply);
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(j:N_MON_AMZO_PER_NRN:
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(j:N_MON_AMZO_PER_NRN:
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(i:N_NRN_X:
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(i:N_NRN_X:
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@ -241,6 +248,11 @@ defproc texel_core (avMx1of2<N_IN> in, out;
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nrn_x_AMZI_tbuf[index].en = nrn_mon_x[i*2];
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nrn_x_AMZI_tbuf[index].en = nrn_mon_x[i*2];
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nrn_x_AMZI_tbuf[index].y = nrn_mon_AMZO_sb.in[j];
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nrn_x_AMZI_tbuf[index].y = nrn_mon_AMZO_sb.in[j];
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)
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)
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nrn_AMZO_keeps[j].y = nrn_mon_AMZO_sb.in[j];
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nrn_AMZO_keeps[j].vdd = supply.vdd;
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nrn_AMZO_keeps[j].vss = supply.vss;
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)
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)
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// Create NON buffered signals from register to nrns.
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// Create NON buffered signals from register to nrns.
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