buffer_t and fifo_t_15 work

test/unit_tests/buffer_token/run/prsim.out

@@ -0,0 +1,29 @@
+t.a._out_a_B t.in.r t.in.a t.out.r t.a._en t.a.inack_ctl._y t.out.a t.a.buf_func._y 
+[0] code starts
+	      7093 t.in.r : 0
+	      7093 t.out.a : 0
+	     17560 t.a._out_a_B : 1  [by t.out.a:=0]
+	     17560 Reset : 0
+	     17562 t.a.reset_buf._y : 1  [by Reset:=0]
+	     22315 t.a._reset_BX : 0  [by t.a.reset_buf._y:=1]
+	     22429 t.a.inack_ctl._y : 1  [by t.a._reset_BX:=0]
+	     23452 t.a.buf_func._y : 1  [by t.a._reset_BX:=0]
+	     25178 t.out.r : 0  [by t.a.buf_func._y:=1]
+	     87795 t.in.a : 0  [by t.a.inack_ctl._y:=1]
+	     87834 t.a._en : 1  [by t.in.a:=0]
+
+	     87834 Reset : 1
+	     87849 t.a.reset_buf._y : 0  [by Reset:=1]
+	     88340 t.a._reset_BX : 1  [by t.a.reset_buf._y:=0]
+[1] reset done
+----------------------------------------------------------------------------------------------------
+	     88340 t.in.r : 1
+	     88353 t.a.buf_func._y : 0  [by t.in.r:=1]
+	     88393 t.out.r : 1  [by t.a.buf_func._y:=0]
+	     88808 t.a.inack_ctl._y : 0  [by t.out.r:=1]
+	     88828 t.in.a : 1  [by t.a.inack_ctl._y:=0]
+	     94889 t.a._en : 0  [by t.in.a:=1]
+	     94889 t.out.a : 1
+	     94936 t.a._out_a_B : 0  [by t.out.a:=1]
+	     94952 t.a.buf_func._y : 1  [by t.a._out_a_B:=0]
+	    139050 t.out.r : 0  [by t.a.buf_func._y:=1]

test/unit_tests/buffer_token/run/test.prs

@@ -0,0 +1,65 @@
+= "GND" "GND"
+= "Vdd" "Vdd"
+= "Reset" "Reset"
+"t.a.reset_buf.a"->"t.a.reset_buf._y"-
+~("t.a.reset_buf.a")->"t.a.reset_buf._y"+
+"t.a.reset_buf._y"->"t.a.reset_buf.y"-
+~("t.a.reset_buf._y")->"t.a.reset_buf.y"+
+"t.a.inv_outa.a"->"t.a.inv_outa.y"-
+~("t.a.inv_outa.a")->"t.a.inv_outa.y"+
+~"t.a.inack_ctl.c1"&~"t.a.inack_ctl.c2"|~"t.a.inack_ctl.pr_B"->"t.a.inack_ctl._y"+
+"t.a.inack_ctl.c1"&"t.a.inack_ctl.c2"&"t.a.inack_ctl.n1"&"t.a.inack_ctl.sr_B"->"t.a.inack_ctl._y"-
+"t.a.inack_ctl._y"->"t.a.inack_ctl.y"-
+~("t.a.inack_ctl._y")->"t.a.inack_ctl.y"+
+~"t.a.buf_func.c1"&~"t.a.buf_func.c2"|~"t.a.buf_func.pr_B"->"t.a.buf_func._y"+
+"t.a.buf_func.c1"&"t.a.buf_func.c2"&"t.a.buf_func.n1"&"t.a.buf_func.sr_B"->"t.a.buf_func._y"-
+"t.a.buf_func._y"->"t.a.buf_func.y"-
+~("t.a.buf_func._y")->"t.a.buf_func.y"+
+= "t.a.reset_B" "t.a.reset_buf.a"
+= "t.a.supply.vdd" "t.a.reset_buf.vdd"
+= "t.a.supply.vdd" "t.a.buf_func.vdd"
+= "t.a.supply.vdd" "t.a.inv_outa.vdd"
+= "t.a.supply.vdd" "t.a.en_ctl.vdd"
+= "t.a.supply.vdd" "t.a.inack_ctl.vdd"
+= "t.a.supply.vss" "t.a.reset_buf.vss"
+= "t.a.supply.vss" "t.a.buf_func.vss"
+= "t.a.supply.vss" "t.a.inv_outa.vss"
+= "t.a.supply.vss" "t.a.en_ctl.vss"
+= "t.a.supply.vss" "t.a.inack_ctl.vss"
+= "t.a._reset_BX" "t.a.reset_buf.y"
+= "t.a._reset_BX" "t.a.buf_func.sr_B"
+= "t.a._reset_BX" "t.a.buf_func.pr_B"
+= "t.a._reset_BX" "t.a.inack_ctl.sr_B"
+= "t.a._reset_BX" "t.a.inack_ctl.pr_B"
+= "t.a._en" "t.a.buf_func.c1"
+= "t.a._en" "t.a.en_ctl.y"
+= "t.a._en" "t.a.inack_ctl.c1"
+~"t.a.en_ctl.p1"&~"t.a.en_ctl.c1"->"t.a.en_ctl.y"+
+"t.a.en_ctl.c1"->"t.a.en_ctl.y"-
+= "t.a._out_a_B" "t.a.buf_func.c2"
+= "t.a._out_a_B" "t.a.inv_outa.y"
+= "t.a.in.d.d[0]" "t.a.in.r"
+= "t.a.in.a" "t.a.en_ctl.c1"
+= "t.a.in.a" "t.a.inack_ctl.y"
+= "t.a.in.d.d[0]" "t.a.buf_func.n1"
+= "t.a.in.d.d[0]" "t.a.inack_ctl.c2"
+= "t.a.in.d.d[0]" "t.a.in.r"
+= "t.a.out.d.d[0]" "t.a.out.r"
+= "t.a.out.a" "t.a.inv_outa.a"
+= "t.a.out.d.d[0]" "t.a.buf_func.y"
+= "t.a.out.d.d[0]" "t.a.en_ctl.p1"
+= "t.a.out.d.d[0]" "t.a.inack_ctl.n1"
+= "t.a.out.d.d[0]" "t.a.out.r"
+= "Reset" "t.a.reset_B"
+= "Vdd" "t.a.supply.vdd"
+= "GND" "t.a.supply.vss"
+= "t.out.d.d[0]" "t.out.r"
+= "t.out.r" "t.a.out.r"
+= "t.out.a" "t.a.out.a"
+= "t.out.d.d[0]" "t.a.out.d.d[0]"
+= "t.out.d.d[0]" "t.out.r"
+= "t.in.d.d[0]" "t.in.r"
+= "t.in.r" "t.a.in.r"
+= "t.in.a" "t.a.in.a"
+= "t.in.d.d[0]" "t.a.in.d.d[0]"
+= "t.in.d.d[0]" "t.in.r"

test/unit_tests/buffer_token/test.act

@@ -0,0 +1,43 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/primitives.act";
+import globals;
+
+open tmpl::dataflow_neuro;
+
+defproc buffer_token_test(a1of1 in; a1of1 out)
+{
+  buffer_t a(.in = in, .out = out);
+  a.supply.vdd = Vdd;
+  a.supply.vss = GND; 
+  a.reset_B = Reset;
+
+}
+
+buffer_token_test t;

test/unit_tests/buffer_token/test.prsim

@@ -0,0 +1,20 @@
+watchall
+system "echo '[0] code starts'"
+set t.in.r 0
+set t.out.a 0
+cycle
+set Reset 0
+cycle
+status X
+mode run
+set Reset 1
+cycle
+system "echo '[1] reset done'"
+system "echo '----------------------------------------------------------------------------------------------------'"
+set t.in.r 1
+cycle
+assert t.out.r 1
+set t.out.a 1
+cycle
+assert t.in.a 1
+