buffer_t and fifo_t_15 work
This commit is contained in:
29
test/unit_tests/buffer_token/run/prsim.out
Normal file
29
test/unit_tests/buffer_token/run/prsim.out
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@ -0,0 +1,29 @@
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t.a._out_a_B t.in.r t.in.a t.out.r t.a._en t.a.inack_ctl._y t.out.a t.a.buf_func._y
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[0] code starts
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7093 t.in.r : 0
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7093 t.out.a : 0
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17560 t.a._out_a_B : 1 [by t.out.a:=0]
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17560 Reset : 0
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17562 t.a.reset_buf._y : 1 [by Reset:=0]
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22315 t.a._reset_BX : 0 [by t.a.reset_buf._y:=1]
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22429 t.a.inack_ctl._y : 1 [by t.a._reset_BX:=0]
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23452 t.a.buf_func._y : 1 [by t.a._reset_BX:=0]
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25178 t.out.r : 0 [by t.a.buf_func._y:=1]
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87795 t.in.a : 0 [by t.a.inack_ctl._y:=1]
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87834 t.a._en : 1 [by t.in.a:=0]
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87834 Reset : 1
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87849 t.a.reset_buf._y : 0 [by Reset:=1]
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88340 t.a._reset_BX : 1 [by t.a.reset_buf._y:=0]
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[1] reset done
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----------------------------------------------------------------------------------------------------
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88340 t.in.r : 1
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88353 t.a.buf_func._y : 0 [by t.in.r:=1]
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88393 t.out.r : 1 [by t.a.buf_func._y:=0]
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88808 t.a.inack_ctl._y : 0 [by t.out.r:=1]
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88828 t.in.a : 1 [by t.a.inack_ctl._y:=0]
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94889 t.a._en : 0 [by t.in.a:=1]
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94889 t.out.a : 1
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94936 t.a._out_a_B : 0 [by t.out.a:=1]
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94952 t.a.buf_func._y : 1 [by t.a._out_a_B:=0]
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139050 t.out.r : 0 [by t.a.buf_func._y:=1]
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65
test/unit_tests/buffer_token/run/test.prs
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65
test/unit_tests/buffer_token/run/test.prs
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= "GND" "GND"
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= "Vdd" "Vdd"
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= "Reset" "Reset"
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"t.a.reset_buf.a"->"t.a.reset_buf._y"-
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~("t.a.reset_buf.a")->"t.a.reset_buf._y"+
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"t.a.reset_buf._y"->"t.a.reset_buf.y"-
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~("t.a.reset_buf._y")->"t.a.reset_buf.y"+
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"t.a.inv_outa.a"->"t.a.inv_outa.y"-
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~("t.a.inv_outa.a")->"t.a.inv_outa.y"+
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~"t.a.inack_ctl.c1"&~"t.a.inack_ctl.c2"|~"t.a.inack_ctl.pr_B"->"t.a.inack_ctl._y"+
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"t.a.inack_ctl.c1"&"t.a.inack_ctl.c2"&"t.a.inack_ctl.n1"&"t.a.inack_ctl.sr_B"->"t.a.inack_ctl._y"-
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"t.a.inack_ctl._y"->"t.a.inack_ctl.y"-
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~("t.a.inack_ctl._y")->"t.a.inack_ctl.y"+
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~"t.a.buf_func.c1"&~"t.a.buf_func.c2"|~"t.a.buf_func.pr_B"->"t.a.buf_func._y"+
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"t.a.buf_func.c1"&"t.a.buf_func.c2"&"t.a.buf_func.n1"&"t.a.buf_func.sr_B"->"t.a.buf_func._y"-
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"t.a.buf_func._y"->"t.a.buf_func.y"-
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~("t.a.buf_func._y")->"t.a.buf_func.y"+
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= "t.a.reset_B" "t.a.reset_buf.a"
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= "t.a.supply.vdd" "t.a.reset_buf.vdd"
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= "t.a.supply.vdd" "t.a.buf_func.vdd"
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= "t.a.supply.vdd" "t.a.inv_outa.vdd"
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= "t.a.supply.vdd" "t.a.en_ctl.vdd"
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= "t.a.supply.vdd" "t.a.inack_ctl.vdd"
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= "t.a.supply.vss" "t.a.reset_buf.vss"
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= "t.a.supply.vss" "t.a.buf_func.vss"
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= "t.a.supply.vss" "t.a.inv_outa.vss"
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= "t.a.supply.vss" "t.a.en_ctl.vss"
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= "t.a.supply.vss" "t.a.inack_ctl.vss"
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= "t.a._reset_BX" "t.a.reset_buf.y"
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= "t.a._reset_BX" "t.a.buf_func.sr_B"
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= "t.a._reset_BX" "t.a.buf_func.pr_B"
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= "t.a._reset_BX" "t.a.inack_ctl.sr_B"
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= "t.a._reset_BX" "t.a.inack_ctl.pr_B"
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= "t.a._en" "t.a.buf_func.c1"
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= "t.a._en" "t.a.en_ctl.y"
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= "t.a._en" "t.a.inack_ctl.c1"
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~"t.a.en_ctl.p1"&~"t.a.en_ctl.c1"->"t.a.en_ctl.y"+
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"t.a.en_ctl.c1"->"t.a.en_ctl.y"-
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= "t.a._out_a_B" "t.a.buf_func.c2"
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= "t.a._out_a_B" "t.a.inv_outa.y"
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= "t.a.in.d.d[0]" "t.a.in.r"
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= "t.a.in.a" "t.a.en_ctl.c1"
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= "t.a.in.a" "t.a.inack_ctl.y"
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= "t.a.in.d.d[0]" "t.a.buf_func.n1"
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= "t.a.in.d.d[0]" "t.a.inack_ctl.c2"
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= "t.a.in.d.d[0]" "t.a.in.r"
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= "t.a.out.d.d[0]" "t.a.out.r"
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= "t.a.out.a" "t.a.inv_outa.a"
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= "t.a.out.d.d[0]" "t.a.buf_func.y"
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= "t.a.out.d.d[0]" "t.a.en_ctl.p1"
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= "t.a.out.d.d[0]" "t.a.inack_ctl.n1"
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= "t.a.out.d.d[0]" "t.a.out.r"
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= "Reset" "t.a.reset_B"
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= "Vdd" "t.a.supply.vdd"
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= "GND" "t.a.supply.vss"
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= "t.out.d.d[0]" "t.out.r"
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= "t.out.r" "t.a.out.r"
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= "t.out.a" "t.a.out.a"
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= "t.out.d.d[0]" "t.a.out.d.d[0]"
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= "t.out.d.d[0]" "t.out.r"
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= "t.in.d.d[0]" "t.in.r"
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= "t.in.r" "t.a.in.r"
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= "t.in.a" "t.a.in.a"
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= "t.in.d.d[0]" "t.a.in.d.d[0]"
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= "t.in.d.d[0]" "t.in.r"
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43
test/unit_tests/buffer_token/test.act
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43
test/unit_tests/buffer_token/test.act
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/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library.
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* It's the testing facility for cell_lib_std.act
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/primitives.act";
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import globals;
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open tmpl::dataflow_neuro;
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defproc buffer_token_test(a1of1 in; a1of1 out)
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{
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buffer_t a(.in = in, .out = out);
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a.supply.vdd = Vdd;
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a.supply.vss = GND;
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a.reset_B = Reset;
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}
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buffer_token_test t;
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20
test/unit_tests/buffer_token/test.prsim
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20
test/unit_tests/buffer_token/test.prsim
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watchall
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system "echo '[0] code starts'"
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set t.in.r 0
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set t.out.a 0
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cycle
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set Reset 0
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cycle
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status X
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mode run
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set Reset 1
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cycle
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system "echo '[1] reset done'"
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system "echo '----------------------------------------------------------------------------------------------------'"
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set t.in.r 1
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cycle
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assert t.out.r 1
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set t.out.a 1
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cycle
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assert t.in.a 1
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