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minor sigbuf changes

This commit is contained in:
alexmadison 2022-04-11 17:29:15 +02:00
parent 7b2484a8a4
commit c1ea7be83d
2 changed files with 19 additions and 18 deletions
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31
dataflow_neuro/coders.act
View File

@ -810,8 +810,6 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
Yenc.in[i] = iny[i].a; Yenc.in[i] = iny[i].a;
) )
// INV_X2 inv_rx(.a = _r_x, .y _r_x_B, .vdd = supply.vdd, .vss = supply.vss);
// INV_X2 inv_ry(.a = _r_y, .y = _r_y_B, .vdd = supply.vdd, .vss = supply.vss);
INV_X2 inv_buf(.a = buf.in.a, .vdd = supply.vdd, .vss = supply.vss); INV_X2 inv_buf(.a = buf.in.a, .vdd = supply.vdd, .vss = supply.vss);
A_2C_RB_X1 a_x_Cel(.c1 = inv_buf.y, .c2 = _r_x, .y = _a_x, A_2C_RB_X1 a_x_Cel(.c1 = inv_buf.y, .c2 = _r_x, .y = _a_x,
@ -819,11 +817,6 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
A_2C_RB_X1 a_y_Cel(.c1 = inv_buf.y, .c2 = _r_y, .y = _a_y, A_2C_RB_X1 a_y_Cel(.c1 = inv_buf.y, .c2 = _r_y, .y = _a_y,
.sr_B = reset_B, .pr_B = reset_B, .vdd = supply.vdd, .vss = supply.vss); .sr_B = reset_B, .pr_B = reset_B, .vdd = supply.vdd, .vss = supply.vss);
// A_2C_RB_X1 a_x_Cel(.c1 = buf.in.a, .c2 = _r_x_B, .y = _a_x,
// .sr_B = reset_B, .pr_B = reset_B, .vdd = supply.vdd, .vss = supply.vss);
// A_2C_RB_X1 a_y_Cel(.c1 = buf.in.a, .c2 = _r_y_B, .y = _a_y,
// .sr_B = reset_B, .pr_B = reset_B, .vdd = supply.vdd, .vss = supply.vss);
// Wire up encoder to buffer // Wire up encoder to buffer
(i:NxC: (i:NxC:
Xenc.out.d[i] = buf.in.d.d[i]; Xenc.out.d[i] = buf.in.d.d[i];
@ -891,18 +884,26 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
} }
// export
// defproc nrn_line_end_pull_down (bool? in; bool? reset_B; power supply; bool! out)
// {
// bool _out, __out, nand_out;
// BUF_X1 buf1(.a=in, .y=_out, .vdd=supply.vdd,.vss=supply.vss);
// BUF_X1 buf2(.a=_out, .y=__out, .vdd=supply.vdd,.vss=supply.vss);
// INV_X1 inv(.a = __out, .vdd=supply.vdd,.vss =supply.vss);
export // NAND2_X1 aenor(.a=inv.y, .b=reset_B, .y = nand_out, .vdd=supply.vdd,.vss=supply.vss);
// A_1N_U_X4 pull_down(.a=nand_out, .y=out);
// }
export
defproc nrn_line_end_pull_down (bool? in; bool? reset_B; power supply; bool! out) defproc nrn_line_end_pull_down (bool? in; bool? reset_B; power supply; bool! out)
{ {
bool _out, __out, nand_out; INV_X1 inv(.a = reset_B, .vdd=supply.vdd,.vss =supply.vss);
BUF_X1 buf1(.a=in, .y=_out, .vdd=supply.vdd,.vss=supply.vss);
BUF_X1 buf2(.a=_out, .y=__out, .vdd=supply.vdd,.vss=supply.vss);
INV_X1 inv(.a = __out, .vdd=supply.vdd,.vss =supply.vss);
NAND2_X1 aenor(.a=inv.y, .b=reset_B, .y = nand_out, .vdd=supply.vdd,.vss=supply.vss); A_1N_U_X4 pull_down(.a=in, .y=out);
A_1N_U_X4 pull_downR(.a=inv.y, .y=out);
A_1N_U_X4 pull_down(.a=nand_out, .y=out);
} }

6
dataflow_neuro/interfaces.act
View File

@ -62,9 +62,9 @@ namespace tmpl {
sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply); sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
// sig buff the req // sig buff the req
bool _reqX, _reqXX[N]; bool _reqX, _reqXX[N*2];
BUF_X4 req_buf(.a=_req, .y=_reqX,.vdd=supply.vdd,.vss=supply.vss); BUF_X4 req_buf(.a=_req, .y=_reqX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N> req_bufarray(.in=_reqX, .out=_reqXX, .supply=supply); sigbuf<N*2> req_bufarray(.in=_reqX, .out=_reqXX, .supply=supply);
// For reasons of pure spice, the control circuitry // For reasons of pure spice, the control circuitry
// requires a req signal that FALLS SLOWER than the req going to the function block. // requires a req signal that FALLS SLOWER than the req going to the function block.
@ -121,7 +121,7 @@ namespace tmpl {
f_buf_func[i].n1=_inB[i]; f_buf_func[i].n1=_inB[i];
t_buf_func[i].n1=in.d[i]; t_buf_func[i].n1=in.d[i];
f_buf_func[i].n2=_reqXX[i]; f_buf_func[i].n2=_reqXX[i];
t_buf_func[i].n2=_reqXX[i]; t_buf_func[i].n2=_reqXX[i+N];
f_buf_func[i].vdd=supply.vdd; f_buf_func[i].vdd=supply.vdd;
t_buf_func[i].vdd=supply.vdd; t_buf_func[i].vdd=supply.vdd;
f_buf_func[i].vss=supply.vss; f_buf_func[i].vss=supply.vss;