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decoder 2d hybrid unit tests working

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This commit is contained in:
alexmadison
2022-03-31 18:00:08 +02:00
parent 2c491a6e37
commit c840273ae6
6 changed files with 10826 additions and 9 deletions
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20
dataflow_neuro/coders.act
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@ -270,6 +270,9 @@ export template<pint NxC, NyC, Nx, Ny, N_dly_cfg>
defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg[N_dly_cfg], hs_en,
reset_B; power supply) {
bool hs_enB;
INV_X4 hs_inv(.a = hs_en, .y = hs_enB, .vdd = supply.vdd, .vss = supply.vss);
// Buffer to recieve concat(x,y) address packet
buffer<NxC+NyC> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
@ -323,10 +326,11 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
// bc smaller
// and bc the delay that an AND induces means that the pullup could
// end up fighting a synapse pulldown, as both have the correct req sigs.
A_1P_U_X4 pu[Nx]; // TODO probably replace this with variable strength PU
A_2P_U_X4 pu[Nx]; // TODO probably replace this with variable strength PU
A_1P_U_X4 pu_reset[Nx];
(i:Nx:
pu[i].a = d_dr_xX[i].out[Ny];
pu[i].b = hs_enB;
pu[i].y = _out_acksB[i];
pu[i].vdd = supply.vdd;
pu[i].vss = supply.vss;
@ -354,17 +358,15 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
// _only_ once _both_ ackB has been reset, _and_ its output data
// has been fully invalidated.
// Otherwise run into the issue that ack is removed before data is invalid.
A_2C_B_X1 buf_ack_Cel(.c1 = _ortree.out, .c2 = valid_Cel.y, .y = addr_buf.out.a,
A_2C_B_X1 buf_ack_Cel(.c1 = _ortree.out, .c2 = valid_Cel.y,
.vdd = supply.vdd, .vss = supply.vss);
// Mux to switch between acks from handshake or delay
MUX2_X1 ack_mux(.s = hs_en, .a = valid_Cel.y, .b = buf_ack_Cel.y,
.vdd = supply.vdd, .vss = supply.vss);
// Programmable delay
delayprog<N_dly_cfg> dly(.s = dly_cfg, .supply = supply);
dly.out = addr_buf.out.a;
delayprog<N_dly_cfg> dly(.in = ack_mux.y, .out = addr_buf.out.a, .s = dly_cfg, .supply = supply);
}
@ -739,7 +741,7 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
// y_req pull up
NAND2_X1 nand_y(.a = _y_a_B, .b = _req, .vdd = supply.vdd, .vss = supply.vss);
A_1P_U_X4 pu_y(.a = nand_y.y, .y = outy.r, .vdd = supply.vdd, .vss = supply.vss);
// x_req pull up
NAND3_X1 nand_x(.a = _x_a_B, .b = _req, .c = outy.a, .vdd = supply.vdd, .vss = supply.vss);
A_1P_U_X4 pu_x(.a = nand_x.y, .y = outx.r, .vdd = supply.vdd, .vss = supply.vss);