got rid of flip flop reg tests
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alexmadison
parent
627caf1aed
commit
ca3a56572d
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@ -1,55 +0,0 @@
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t.ff.__clk_B t.ff._clk_B t.d t.clk t._clk_B
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[0] start test
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15221 Reset : 0
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15221 t.clk : 0
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15221 t.d : 0
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16947 t._clk_B : 1 [by t.clk:=0]
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16986 t.ff._clk_B : 0 [by t._clk_B:=1]
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17001 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
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80587 t._reset_B : 1 [by Reset:=0]
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[1] reset completed
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[2] tested d = 0, clk rise
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80587 t.clk : 1
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80587 t.d : 1
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80600 t.ff._mqib : 0 [by t.d:=1]
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80640 t.ff._mqi : 1 [by t.ff._mqib:=0]
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81078 t._clk_B : 0 [by t.clk:=1]
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81493 t.ff._clk_B : 1 [by t._clk_B:=0]
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81513 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
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87554 t.ff._sqib : 0 [by t.ff._clk_B:=1]
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87570 t.q : 1 [by t.ff._sqib:=0]
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87601 t.ff._sqi : 1 [by t.ff._sqib:=0]
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131668 t.ff.q_B : 0 [by t.q:=1]
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131668 t.clk : 0
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145392 t._clk_B : 1 [by t.clk:=0]
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145396 t.ff._clk_B : 0 [by t._clk_B:=1]
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154525 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
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154525 t.d : 0
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154540 t.ff._mqib : 1 [by t.d:=0]
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197788 t.ff._mqi : 0 [by t.ff._mqib:=1]
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197788 t.clk : 1
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234719 t._clk_B : 0 [by t.clk:=1]
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234774 t.ff._clk_B : 1 [by t._clk_B:=0]
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286427 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
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316207 t.ff._sqib : 1 [by t.ff.__clk_B:=0]
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330056 t.ff._sqi : 0 [by t.ff._sqib:=1]
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341019 t.q : 0 [by t.ff._sqib:=1]
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355362 t.ff.q_B : 1 [by t.q:=0]
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355362 t.clk : 0
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355784 t._clk_B : 1 [by t.clk:=0]
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404498 t.ff._clk_B : 0 [by t._clk_B:=1]
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404499 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
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404499 t.d : 1
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404500 t.ff._mqib : 0 [by t.d:=1]
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424705 t.ff._mqi : 1 [by t.ff._mqib:=0]
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[3] tested d = 1, clk rise and fall
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424705 t.clk : 1
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424987 t._clk_B : 0 [by t.clk:=1]
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425755 t.ff._clk_B : 1 [by t._clk_B:=0]
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425758 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
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448196 t.ff._sqib : 0 [by t.ff._clk_B:=1]
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448747 t.ff._sqi : 1 [by t.ff._sqib:=0]
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449267 t.q : 1 [by t.ff._sqib:=0]
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450221 t.ff.q_B : 0 [by t.q:=1]
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450221 t.d : 0
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@ -1,29 +0,0 @@
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= "GND" "GND"
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= "Vdd" "Vdd"
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= "Reset" "Reset"
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"Reset"->"t._reset_B"-
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~("Reset")->"t._reset_B"+
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"t.clk"->"t._clk_B"-
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~("t.clk")->"t._clk_B"+
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= "t._reset_B" "t.ff.reset_B"
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"t.ff.clk_B"->"t.ff._clk_B"-
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~("t.ff.clk_B")->"t.ff._clk_B"+
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"t.ff._clk_B"->"t.ff.__clk_B"-
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~("t.ff._clk_B")->"t.ff.__clk_B"+
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~"t.ff.d"&~"t.ff._clk_B"|~"t.ff.reset_B"|~"t.ff.__clk_B"&~"t.ff._mqi"->"t.ff._mqib"+
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("t.ff.d"&"t.ff.__clk_B"|"t.ff._mqi"&"t.ff._clk_B")&"t.ff.reset_B"->"t.ff._mqib"-
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"t.ff._mqib"->"t.ff._mqi"-
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~("t.ff._mqib")->"t.ff._mqi"+
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~"t.ff._mqi"&~"t.ff.__clk_B"|~"t.ff.reset_B"|~"t.ff._sqi"&~"t.ff._clk_B"->"t.ff._sqib"+
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("t.ff._mqi"&"t.ff._clk_B"|"t.ff._sqi"&"t.ff.__clk_B")&"t.ff.reset_B"->"t.ff._sqib"-
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"t.ff._sqib"->"t.ff._sqi"-
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~("t.ff._sqib")->"t.ff._sqi"+
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"t.ff._sqib"->"t.ff.q"-
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~("t.ff._sqib")->"t.ff.q"+
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"t.ff.q"->"t.ff.q_B"-
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~("t.ff.q")->"t.ff.q_B"+
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= "Vdd" "t.ff.vdd"
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= "GND" "t.ff.vss"
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= "t.q" "t.ff.q"
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= "t._clk_B" "t.ff.clk_B"
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= "t.d" "t.ff.d"
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@ -1,50 +0,0 @@
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/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library.
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* It's the testing facility for cell_lib_std.act
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/primitives.act";
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import globals;
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open tmpl::dataflow_neuro;
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defproc flipflop_test (bool! q; bool? d,clk){
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bool _clk_B;
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DFFQ_R_X1 ff(.d=d,.clk_B = _clk_B, .q = q);
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//Low active Reset
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bool _reset_B;
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prs {
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Reset => _reset_B-
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clk => _clk_B-
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}
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ff.vss = GND;
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ff.vdd = Vdd;
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ff.reset_B = _reset_B;
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}
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flipflop_test t;
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@ -1,51 +0,0 @@
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watchall
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system "echo '[0] start test'"
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set Reset 0
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set t.d 0
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set t.clk 0
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cycle
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status X
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mode run
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assert t.q 0
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system "echo '[1] reset completed'"
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system "echo '[2] tested d = 0, clk rise'"
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set t.clk 1
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set t.d 1
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cycle
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set t.clk 0
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cycle
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set t.d 0
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cycle
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assert t.q 1
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set t.clk 1
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cycle
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assert t.q 0
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set t.d 0
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set t.clk 0
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cycle
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assert t.q 0
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set t.d 1
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cycle
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set t.clk 0
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cycle
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assert t.q 0
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system "echo '[3] tested d = 1, clk rise and fall'"
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set t.d 1
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cycle
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set t.clk 1
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cycle
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set t.d 0
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cycle
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assert t.q 1
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