added monitor decoders

test/unit_tests/texel_in30/test.act

@@ -39,6 +39,7 @@ open std::data;
 open tmpl::dataflow_neuro;
 
 defproc chip_texel_in30 (bd<30> in; bd<30> out; Mx1of2<22> reg_data[64];
+    bool? nrn_mon_x[4], nrn_mon_y[8], syn_mon_x[4], syn_mon_y[8];
     bool? bd_dly_cfg[4], bd_dly_cfg2[2], loopback_en){
 
     bool _reset_B; 
@@ -91,6 +92,8 @@ defproc chip_texel_in30 (bd<30> in; bd<30> out; Mx1of2<22> reg_data[64];
     N_LINE_PD_DLY,
     N_BD_DLY_CFG, N_BD_DLY_CFG2,
     REG_NCA, REG_NCW, REG_M> c(.in = in, .out = out, .reg_data = reg_data,
+        .nrn_mon_x = nrn_mon_x, .nrn_mon_y = nrn_mon_y,
+        .syn_mon_x = syn_mon_x, .syn_mon_y = syn_mon_y,
         .bd_dly_cfg = bd_dly_cfg, .bd_dly_cfg2 = bd_dly_cfg2, .loopback_en = loopback_en,
         .reset_B = _reset_B, .supply = supply);
 

test/unit_tests/texel_in30/test.prsim

@@ -45,8 +45,8 @@ set c.out.a 0
 cycle
 
 # Expect register read packet to arrive
-# Receiving output 4194303 from register 0
-assert-bd-channel-valid "c.out" 30 268435392
+# Receiving output 0 from register 0
+assert-bd-channel-valid "c.out" 30 0
 set c.out.a 1
 cycle
 assert-bd-channel-neutral "c.out" 30
@@ -57,13 +57,15 @@ cycle
 set c.loopback_en 0
 cycle
 
-# Writing 1 to address 0 (enables hs, disables synapse delays)
-set-bd-data-valid "c.in" 30 805306432
+# Enables hs, disable synapse delays
+# Writing 255 to address 0
+set-bd-data-valid "c.in" 30 805322688
 cycle
 set c.in.r 1
 cycle
 assert c.in.a 1
 
+
 # Remove input
 set-bd-channel-neutral "c.in" 30
 cycle
@@ -84,88 +86,72 @@ assert-bd-channel-neutral "c.out" 30
 set c.out.a 0
 cycle
 
+# Remove input
+set-bd-channel-neutral "c.in" 30
+cycle
+assert c.in.a 0
 
 
+# Writing 3 to address 1 (enable targeting)
+set-bd-data-valid "c.in" 30 805306561
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
 
+# Remove input
+set-bd-channel-neutral "c.in" 30
+cycle
+assert c.in.a 0
 
+# Writing 511 to address 2 (change nrn targ)
+set-bd-data-valid "c.in" 30 805339074
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
 
+assert c.nrn_mon_x[0] 0
+assert c.nrn_mon_x[1] 0
+assert c.nrn_mon_x[2] 0
+assert c.nrn_mon_x[3] 1
 
-# # Writing 68 to address 1
-# set c.in.d[0] 1
-# set c.in.d[1] 0
-# set c.in.d[2] 0
-# set c.in.d[3] 0
-# set c.in.d[4] 0
-# set c.in.d[5] 0
-# set c.in.d[6] 1
-# set c.in.d[7] 0
-# set c.in.d[8] 0
-# set c.in.d[9] 0
-# set c.in.d[10] 1
-# set c.in.d[11] 0
-# set c.in.d[12] 1
-# set c.in.d[13] 1
-# cycle
-# set c.in.r 1
-# cycle
-# assert c.in.a 1
+assert c.nrn_mon_y[0] 0
+assert c.nrn_mon_y[1] 0
+assert c.nrn_mon_y[2] 0
+assert c.nrn_mon_y[3] 0
+assert c.nrn_mon_y[4] 0
+assert c.nrn_mon_y[5] 0
+assert c.nrn_mon_y[6] 0
+assert c.nrn_mon_y[7] 1
 
-# # Remove input
-# set-bd-channel-neutral "c.in" 14
-# cycle
-# assert c.in.a 0
+# Remove input
+set-bd-channel-neutral "c.in" 30
+cycle
+assert c.in.a 0
 
+# Writing 0 to address 1 (disable targetting)
+set-bd-data-valid "c.in" 30 805306369
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
 
-# # Reading address 1
-# set c.in.d[0] 1
-# set c.in.d[1] 0
-# set c.in.d[2] 0
-# set c.in.d[3] 0
-# set c.in.d[4] 0
-# set c.in.d[5] 0
-# set c.in.d[6] 0
-# set c.in.d[7] 0
-# set c.in.d[8] 0
-# set c.in.d[9] 0
-# set c.in.d[10] 0
-# set c.in.d[11] 0
-# set c.in.d[12] 0
-# set c.in.d[13] 1
-# cycle
-# set c.in.r 1
-# cycle
-# assert c.in.a 1
+assert c.nrn_mon_x[0] 0
+assert c.nrn_mon_x[1] 0
+assert c.nrn_mon_x[2] 0
+assert c.nrn_mon_x[3] 0
 
-#  # Remove input
-# set-bd-channel-neutral "c.in" 14
-# cycle
-# assert c.in.a 0
+assert c.nrn_mon_y[0] 0
+assert c.nrn_mon_y[1] 0
+assert c.nrn_mon_y[2] 0
+assert c.nrn_mon_y[3] 0
+assert c.nrn_mon_y[4] 0
+assert c.nrn_mon_y[5] 0
+assert c.nrn_mon_y[6] 0
+assert c.nrn_mon_y[7] 0
 
-
-# # Receiving output 68 from register 1
-# assert-bd-channel-valid "c.out" 14 1089
-# set c.out.a 1
-# cycle
-# assert-bd-channel-neutral "c.out" 14
-# set c.out.a 0
-# cycle
-
-# # Sending spike to synapse [0,1]
-# set c.in.d[0] 0
-# set c.in.d[1] 1
-# set c.in.d[2] 0
-# set c.in.d[3] 0
-# set c.in.d[4] 0
-# set c.in.d[5] 0
-# set c.in.d[6] 0
-# set c.in.d[7] 0
-# set c.in.d[8] 0
-# set c.in.d[9] 0
-# set c.in.d[10] 0
-# set c.in.d[11] 0
-# set c.in.d[12] 0
-# set c.in.d[13] 0
-# cycle
-# set c.in.r 1
-# cycle
-# assert c.in.a 1
+# Remove input
+set-bd-channel-neutral "c.in" 30
+cycle
+assert c.in.a 0