added monitor decoders
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@ -45,8 +45,8 @@ set c.out.a 0
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cycle
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# Expect register read packet to arrive
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# Receiving output 4194303 from register 0
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assert-bd-channel-valid "c.out" 30 268435392
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# Receiving output 0 from register 0
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assert-bd-channel-valid "c.out" 30 0
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set c.out.a 1
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cycle
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assert-bd-channel-neutral "c.out" 30
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@ -57,13 +57,15 @@ cycle
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set c.loopback_en 0
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cycle
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# Writing 1 to address 0 (enables hs, disables synapse delays)
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set-bd-data-valid "c.in" 30 805306432
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# Enables hs, disable synapse delays
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# Writing 255 to address 0
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set-bd-data-valid "c.in" 30 805322688
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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# Remove input
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set-bd-channel-neutral "c.in" 30
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cycle
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@ -84,88 +86,72 @@ assert-bd-channel-neutral "c.out" 30
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set c.out.a 0
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cycle
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# Remove input
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set-bd-channel-neutral "c.in" 30
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cycle
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assert c.in.a 0
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# Writing 3 to address 1 (enable targeting)
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set-bd-data-valid "c.in" 30 805306561
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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# Remove input
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set-bd-channel-neutral "c.in" 30
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cycle
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assert c.in.a 0
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# Writing 511 to address 2 (change nrn targ)
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set-bd-data-valid "c.in" 30 805339074
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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assert c.nrn_mon_x[0] 0
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assert c.nrn_mon_x[1] 0
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assert c.nrn_mon_x[2] 0
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assert c.nrn_mon_x[3] 1
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# # Writing 68 to address 1
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# set c.in.d[0] 1
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# set c.in.d[1] 0
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# set c.in.d[2] 0
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# set c.in.d[3] 0
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# set c.in.d[4] 0
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# set c.in.d[5] 0
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# set c.in.d[6] 1
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# set c.in.d[7] 0
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# set c.in.d[8] 0
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# set c.in.d[9] 0
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# set c.in.d[10] 1
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# set c.in.d[11] 0
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# set c.in.d[12] 1
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# set c.in.d[13] 1
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# cycle
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# set c.in.r 1
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# cycle
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# assert c.in.a 1
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assert c.nrn_mon_y[0] 0
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assert c.nrn_mon_y[1] 0
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assert c.nrn_mon_y[2] 0
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assert c.nrn_mon_y[3] 0
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assert c.nrn_mon_y[4] 0
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assert c.nrn_mon_y[5] 0
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assert c.nrn_mon_y[6] 0
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assert c.nrn_mon_y[7] 1
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# # Remove input
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# set-bd-channel-neutral "c.in" 14
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# cycle
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# assert c.in.a 0
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# Remove input
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set-bd-channel-neutral "c.in" 30
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cycle
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assert c.in.a 0
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# Writing 0 to address 1 (disable targetting)
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set-bd-data-valid "c.in" 30 805306369
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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# # Reading address 1
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# set c.in.d[0] 1
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# set c.in.d[1] 0
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# set c.in.d[2] 0
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# set c.in.d[3] 0
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# set c.in.d[4] 0
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# set c.in.d[5] 0
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# set c.in.d[6] 0
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# set c.in.d[7] 0
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# set c.in.d[8] 0
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# set c.in.d[9] 0
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# set c.in.d[10] 0
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# set c.in.d[11] 0
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# set c.in.d[12] 0
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# set c.in.d[13] 1
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# cycle
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# set c.in.r 1
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# cycle
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# assert c.in.a 1
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assert c.nrn_mon_x[0] 0
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assert c.nrn_mon_x[1] 0
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assert c.nrn_mon_x[2] 0
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assert c.nrn_mon_x[3] 0
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# # Remove input
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# set-bd-channel-neutral "c.in" 14
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# cycle
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# assert c.in.a 0
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assert c.nrn_mon_y[0] 0
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assert c.nrn_mon_y[1] 0
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assert c.nrn_mon_y[2] 0
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assert c.nrn_mon_y[3] 0
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assert c.nrn_mon_y[4] 0
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assert c.nrn_mon_y[5] 0
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assert c.nrn_mon_y[6] 0
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assert c.nrn_mon_y[7] 0
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# # Receiving output 68 from register 1
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# assert-bd-channel-valid "c.out" 14 1089
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# set c.out.a 1
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# cycle
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# assert-bd-channel-neutral "c.out" 14
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# set c.out.a 0
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# cycle
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# # Sending spike to synapse [0,1]
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# set c.in.d[0] 0
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# set c.in.d[1] 1
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# set c.in.d[2] 0
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# set c.in.d[3] 0
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# set c.in.d[4] 0
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# set c.in.d[5] 0
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# set c.in.d[6] 0
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# set c.in.d[7] 0
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# set c.in.d[8] 0
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# set c.in.d[9] 0
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# set c.in.d[10] 0
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# set c.in.d[11] 0
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# set c.in.d[12] 0
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# set c.in.d[13] 0
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# cycle
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# set c.in.r 1
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# cycle
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# assert c.in.a 1
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# Remove input
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set-bd-channel-neutral "c.in" 30
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cycle
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assert c.in.a 0
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