bics/actlib_dataflow_neuro
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tapeout freeze

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alexmadison
2022-04-14 17:51:34 +02:00
parent f7d2db9ef3
commit cd5900d4dc
7 changed files with 266250 additions and 787873 deletions
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6307
test/unit_tests/texel_dualcore/run/prsim.in
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test/unit_tests/texel_dualcore/run/prsim.out
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test/unit_tests/texel_dualcore/run/test.prs
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94
test/unit_tests/texel_dualcore/test.act
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@ -42,23 +42,15 @@ open tmpl::dataflow_neuro;
pint N_IN = 32;
// pint N_NRN_X = 15;
// pint N_NRN_Y = 6;
// pint NC_NRN_X = 4;
// pint NC_NRN_Y = 3;
pint N_NRN_X = 16;
pint N_NRN_Y = 8;
pint N_NRN_X = 15;
pint N_NRN_Y = 6;
pint NC_NRN_X = 4;
pint NC_NRN_Y = 3;
// pint N_SYN_X = 15;
// pint N_SYN_Y = 348;
// pint NC_SYN_X = 6;
// pint NC_SYN_Y = 9;
pint N_SYN_X = 16;
pint N_SYN_Y = 8;
pint NC_SYN_X = 4;
pint NC_SYN_Y = 3;
pint N_SYN_X = 15;
pint N_SYN_Y = 348;
pint NC_SYN_X = 6;
pint NC_SYN_Y = 9;
pint N_SYN_DLY_CFG = 4;
pint N_BD_DLY_CFG = 4;
@ -73,7 +65,7 @@ pint N_SYN_MON_Y = N_SYN_Y; // [mon]*N
pint N_MON_AMZO_PER_SYN = 5;
pint N_MON_AMZO_PER_NRN = 7;
pint N_FLAGS_PER_SYN = 3; // Syn: Must be at least 3 (since those ones have special safety)
pint N_FLAGS_PER_SYN = 4; // Syn: Must be at least 3 (since those ones have special safety)
pint N_FLAGS_PER_NRN = 9; // and leq than the number of bits in a reg, since have presumed only needs one.
pint N_BUFFERS = 3;
@ -88,12 +80,12 @@ pint REG_NCW = 23;
defproc chip_texel_dualcore (bd<N_IN> in, out;
Mx1of2<REG_NCW> c1_reg_data[REG_M];
// a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
// a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
bool c1_syn_r[N_SYN_X * N_SYN_Y];
bool c1_syn_a[N_SYN_X * N_SYN_Y];
bool c1_nrn_r[N_NRN_X * N_NRN_Y];
bool c1_nrn_a[N_NRN_X * N_NRN_Y];
a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
// bool c1_syn_r[N_SYN_X * N_SYN_Y];
// bool c1_syn_a[N_SYN_X * N_SYN_Y];
// bool c1_nrn_r[N_NRN_X * N_NRN_Y];
// bool c1_nrn_a[N_NRN_X * N_NRN_Y];
bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
@ -102,12 +94,12 @@ defproc chip_texel_dualcore (bd<N_IN> in, out;
bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
Mx1of2<REG_NCW> c2_reg_data[REG_M];
// a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
// a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
bool c2_syn_r[N_SYN_X * N_SYN_Y];
bool c2_syn_a[N_SYN_X * N_SYN_Y];
bool c2_nrn_r[N_NRN_X * N_NRN_Y];
bool c2_nrn_a[N_NRN_X * N_NRN_Y];
a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
// bool c2_syn_r[N_SYN_X * N_SYN_Y];
// bool c2_syn_a[N_SYN_X * N_SYN_Y];
// bool c2_nrn_r[N_NRN_X * N_NRN_Y];
// bool c2_nrn_a[N_NRN_X * N_NRN_Y];
bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
@ -127,22 +119,22 @@ defproc chip_texel_dualcore (bd<N_IN> in, out;
supply.vss = GND;
a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
(i:N_SYN_X * N_SYN_Y:
c1_synapses[i].r = c1_syn_r[i];
c2_synapses[i].r = c2_syn_r[i];
c1_synapses[i].a = c1_syn_a[i];
c2_synapses[i].a = c2_syn_a[i];
)
(i:N_NRN_X * N_NRN_Y:
c1_neurons[i].r = c1_nrn_r[i];
c2_neurons[i].r = c2_nrn_r[i];
c1_neurons[i].a = c1_nrn_a[i];
c2_neurons[i].a = c2_nrn_a[i];
)
// a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
// a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
// a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
// a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
// (i:N_SYN_X * N_SYN_Y:
// c1_synapses[i].r = c1_syn_r[i];
// c2_synapses[i].r = c2_syn_r[i];
// c1_synapses[i].a = c1_syn_a[i];
// c2_synapses[i].a = c2_syn_a[i];
// )
// (i:N_NRN_X * N_NRN_Y:
// c1_neurons[i].r = c1_nrn_r[i];
// c2_neurons[i].r = c2_nrn_r[i];
// c1_neurons[i].a = c1_nrn_a[i];
// c2_neurons[i].a = c2_nrn_a[i];
// )
texel_dualcore<N_IN,
@ -160,22 +152,6 @@ defproc chip_texel_dualcore (bd<N_IN> in, out;
.loopback_en = loopback_en, .supply = supply, .reset_B = _reset_B);
pint N_SYNS = N_SYN_X * N_SYN_Y;
BUF_X4 syn2nrns_r[N_SYNS*2];
BUF_X4 syn2nrns_a[N_SYNS*2];
(i:N_SYNS:
syn2nrns_r[i].a = c1_synapses[i].r;
syn2nrns_r[i].y = c1_neurons[i].r;
syn2nrns_a[i].a = c1_neurons[i].a;
syn2nrns_a[i].y = c1_synapses[i].a;
syn2nrns_r[i+N_SYNS].a = c2_synapses[i].r;
syn2nrns_r[i+N_SYNS].y = c2_neurons[i].r;
syn2nrns_a[i+N_SYNS].a = c2_neurons[i].a;
syn2nrns_a[i+N_SYNS].y = c2_synapses[i].a;
)
}

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test/unit_tests/texel_dualcore/test.prsim
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