bics/actlib_dataflow_neuro
22
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

synapse handshake unit tests working

Browse Source
This commit is contained in:
alexmadison
2022-03-31 11:23:51 +02:00
parent e779ee55b9
commit cd5d41d7f8
6 changed files with 2903 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
dataflow_neuro/cell_lib_async.act
View File

@ -33,11 +33,6 @@ namespace tmpl {
[weak=1] _y -> y-
[weak=1] ~_y -> y+
}
sizing {
leak_adjust <- 1;
p_n_mode <- 1;
y {-1}; _y{-1}
}
}
@ -569,6 +564,7 @@ namespace tmpl {
mk_excllo(_y1, _y2)
}
}
export
defproc PULLDOWN_X4(bool? a; bool! y; bool? vdd, vss)
{
prs{
@ -576,6 +572,7 @@ namespace tmpl {
}
}
export
defproc PULLDOWN2_X4(bool? a, b; bool! y; bool? vdd, vss)
{
prs{
@ -583,6 +580,7 @@ namespace tmpl {
}
}
export
defproc PULLUP_X4(bool? a; bool! y; bool? vdd, vss)
{
prs{

24
dataflow_neuro/coders.act
View File

@ -214,14 +214,20 @@ namespace tmpl {
)
// req-ack buffers
// Delay needed here, since otherwise the pull up of reqB happens too quickly.
// Means that the pull up may start fighting the synapse,
// since the synapse has not yet retracted its ack.
// Also there is the possibility, if really fast, that the line pull up block
// doesn't yet see that the input is valid, and starts pulling up.
// In any case, this delay is important.
sigbuf<Ny> req_bufs[Nx];
delay_fifo<10> more_delays[Nx];
delay_chain<N_dly> ack_delays[Nx];
(i:Nx:
more_delays[i].in = _out_reqsB[i];
more_delays[i].supply = supply;
ack_delays[i].in = _out_reqsB[i];
ack_delays[i].supply = supply;
// req_bufs[i].in = _out_reqsB[i];
req_bufs[i].in = more_delays[i].out;
req_bufs[i].in = ack_delays[i].out;
req_bufs[i].out[0] = _out_acksB[i]; // DANGER DANGER
req_bufs[i].supply = supply;
@ -230,16 +236,12 @@ namespace tmpl {
)
// Line end pull UPs (triggered once synapse reqs removed)
delay_fifo<N_dly> pu_dlys[Nx];
OR2_X1 pu_ORs[Nx];
PULLUP_X4 pu[Nx]; // TODO probably replace this with variable strength PU
AND2_X1 pu_ANDs[Nx];
(i:Nx:
pu_dlys[i].in = d_dr_x.out[i];
pu_dlys[i].supply = supply;
pu_ORs[i].a = _out_acksB[i];
pu_ORs[i].b = pu_dlys[i].out;
pu_ORs[i].b = d_dr_x.out[i];
pu_ORs[i].vdd = supply.vdd;
pu_ORs[i].vss = supply.vss;
@ -737,8 +739,8 @@ namespace tmpl {
// Create delay fifos to emulate the fact that the line pull downs
// are at the end of the line, and thus slow.
// Note that if N_dly = 0, delay fifo is just a pipe.
delay_fifo<N_dly> dly_x[Nx];
delay_fifo<N_dly> dly_y[Ny];
delay_chain<N_dly> dly_x[Nx];
delay_chain<N_dly> dly_y[Ny];
// Create x line req pull downs
nrn_line_end_pull_down pd_x[Nx];