bics/actlib_dataflow_neuro
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Merge remote-tracking branch 'origin/dev' into dev

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Michele
2022-03-03 17:53:40 +01:00
parent ba096bf6b2 382714d11e
commit d64afd8c50
7 changed files with 1446 additions and 5 deletions
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dataflow_neuro/coders.act
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@@ -44,7 +44,7 @@ namespace tmpl {
* Thus NxC should be something like NxC = ceil(log2(Nx))
* but my guess is that we can't do logs...
* N_dly_cfg is the number of config bits in the ACK delay line,
* with all bits high corresponding to 2**N_dly_cfg -1 DLY1_X4 cells.
* with all bits high corresponding to 2**N_dly_cfg -1 DLY4_X1 cells.
*/
export template<pint NxC, NyC, Nx, Ny, N_dly_cfg>
defproc decoder_2d_dly (avMx1of2<NxC+NyC> in; bool? outx[Nx], outy[Ny],
@@ -212,8 +212,22 @@ namespace tmpl {
}
template<pint N, pint M,pint address_size, pint ACK_STRENGTH>
defproc encoder2D(a1of1 x[N]; a1of1 y[M] ;avMx1of2<address_size> addr; power supply; bool reset_B)
export template<pint Nx, Ny>
defproc and_grid(bool! out[Nx*Ny]; bool? inx[Nx], iny[Ny]; power supply) {
AND2_X1 ands[Nx*Ny];
(i:0..Nx*Ny-1:ands[i].vss = supply.vss; ands[i].vdd = supply.vdd;)
(x:0..Nx-1:
(y:0..Ny-1:
ands[x + y*Nx].a = inx[x];
ands[x + y*Nx].b = iny[y];
ands[x + y*Nx].y = out[x + y*Nx];
)
)
}
template<pint N, pint M, pint ACK_STRENGTH>
defproc encoder2D(a1of1 x[N]; a1of1 y[M] ;avMx1of2<X> addr; bool! out_a; power supply)
{
// Reset buffers
bool _reset_BX,_reset_BXX[H];
@@ -345,8 +359,6 @@ namespace tmpl {
}
}
}