added delays to out req-ack buffers, seems to work
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@ -190,7 +190,7 @@ namespace tmpl {
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// Acknowledge pull down time
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// Acknowledge pull down time
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// Pull UPs on the reqB lines by synapses (easier to invert).
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// Pull DOWNs on the reqB lines by synapses (easier to invert).
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bool _out_reqsB[Nx], _out_acksB[Nx]; // The vertical output ack lines from each syn.
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bool _out_reqsB[Nx], _out_acksB[Nx]; // The vertical output ack lines from each syn.
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PULLDOWN2_X4 req_pulldowns[Nx*Ny];
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PULLDOWN2_X4 req_pulldowns[Nx*Ny];
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pint index;
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pint index;
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@ -215,10 +215,18 @@ namespace tmpl {
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// req-ack buffers
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// req-ack buffers
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sigbuf<Ny> req_bufs[Nx];
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sigbuf<Ny> req_bufs[Nx];
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delay_fifo<10> more_delays[Nx];
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(i:Nx:
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(i:Nx:
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req_bufs[i].in = _out_reqsB[i];
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more_delays[i].in = _out_reqsB[i];
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more_delays[i].supply = supply;
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// req_bufs[i].in = _out_reqsB[i];
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req_bufs[i].in = more_delays[i].out;
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req_bufs[i].out[0] = _out_acksB[i]; // DANGER DANGER
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req_bufs[i].out[0] = _out_acksB[i]; // DANGER DANGER
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req_bufs[i].supply = supply;
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req_bufs[i].supply = supply;
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)
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)
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// Line end pull UPs (triggered once synapse reqs removed)
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// Line end pull UPs (triggered once synapse reqs removed)
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@ -227,11 +235,11 @@ namespace tmpl {
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PULLUP_X4 pu[Nx]; // TODO probably replace this with variable strength PU
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PULLUP_X4 pu[Nx]; // TODO probably replace this with variable strength PU
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AND2_X1 pu_ANDs[Nx];
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AND2_X1 pu_ANDs[Nx];
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(i:Nx:
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(i:Nx:
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pu_dlys[i].in = _out_acksB[i];
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pu_dlys[i].in = d_dr_x.out[i];
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pu_dlys[i].supply = supply;
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pu_dlys[i].supply = supply;
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pu_ORs[i].a = pu_dlys[i].out;
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pu_ORs[i].a = _out_acksB[i];
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pu_ORs[i].b = d_dr_x.out[i];
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pu_ORs[i].b = pu_dlys[i].out;
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pu_ORs[i].vdd = supply.vdd;
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pu_ORs[i].vdd = supply.vdd;
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pu_ORs[i].vss = supply.vss;
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pu_ORs[i].vss = supply.vss;
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