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added delays to out req-ack buffers, seems to work

This commit is contained in:
alexmadison 2022-03-30 19:53:27 +02:00
parent a53bd58e29
commit e779ee55b9
1 changed files with 13 additions and 5 deletions
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18
dataflow_neuro/coders.act
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@ -190,7 +190,7 @@ namespace tmpl {
// Acknowledge pull down time
// Pull UPs on the reqB lines by synapses (easier to invert).
// Pull DOWNs on the reqB lines by synapses (easier to invert).
bool _out_reqsB[Nx], _out_acksB[Nx]; // The vertical output ack lines from each syn.
PULLDOWN2_X4 req_pulldowns[Nx*Ny];
pint index;
@ -215,10 +215,18 @@ namespace tmpl {
// req-ack buffers
sigbuf<Ny> req_bufs[Nx];
delay_fifo<10> more_delays[Nx];
(i:Nx:
req_bufs[i].in = _out_reqsB[i];
more_delays[i].in = _out_reqsB[i];
more_delays[i].supply = supply;
// req_bufs[i].in = _out_reqsB[i];
req_bufs[i].in = more_delays[i].out;
req_bufs[i].out[0] = _out_acksB[i]; // DANGER DANGER
req_bufs[i].supply = supply;
)
// Line end pull UPs (triggered once synapse reqs removed)
@ -227,11 +235,11 @@ namespace tmpl {
PULLUP_X4 pu[Nx]; // TODO probably replace this with variable strength PU
AND2_X1 pu_ANDs[Nx];
(i:Nx:
pu_dlys[i].in = _out_acksB[i];
pu_dlys[i].in = d_dr_x.out[i];
pu_dlys[i].supply = supply;
pu_ORs[i].a = pu_dlys[i].out;
pu_ORs[i].b = d_dr_x.out[i];
pu_ORs[i].a = _out_acksB[i];
pu_ORs[i].b = pu_dlys[i].out;
pu_ORs[i].vdd = supply.vdd;
pu_ORs[i].vss = supply.vss;