Changed FF in std. Started test (spoiler: is not working)

dataflow_neuro/cell_lib_std.act

@@ -373,15 +373,48 @@ namespace tmpl {
       }
       sizing { _en{-2}; y{-2,2} }
     }
-
+    export defproc DFFQ_R_X1 (bool? clk, reset, S, d, vdd, vss; bool! q)
-    export defcell DFQ_R_X1 (bool! Q,Q_B; bool? d,clk,vdd,vss,reset_B)
     {
+      bool _clk, __clk, _q_B, _dl;
+      bool _Ro, _So;
+      bool _So2;
+      bool _qb;
+
       prs {
-        reset_B -> Q-
+        _q_B<10> -> q-
-        ~Q => Q_B
+       ~_q_B<20> -> q+
-        reset_B & ~d & clk -> Q+
+
-        reset_B & d & clk -> Q-
+        clk<10> -> _clk-
+       ~clk<20> -> _clk+
+
+        _clk<10> -> __clk-
+       ~_clk<20> -> __clk+
+
+       reset<20>  -> _Ro-
+      ~reset<20>  -> _Ro+
+
+       //  S<20> & _dl -> _So-
+       // ~S<20> | ~_dl -> _So+
+
+       [keeper=0] d<10> & _clk -> _dl-
+                ~d<20> & ~__clk<10> -> _dl+
+
+        reset<20> & _qb -> _q_B-
+       ~reset<20> | ~_qb -> _q_B+
+
+       //  _q_B<20> & S -> _So2-
+       // ~_q_B<20> | ~S -> _So2+
+
+       // input stage feedback
+       transgate<10> (__clk,_clk,_Ro,_dl)
+
+       // input to output
+       transgate<10> (__clk,_clk,reset,_qb)
+
+      // output feedback
+       transgate<10> (_clk,__clk,reset,_qb)
       }
+      sizing { q{-1} }
     }
   }
 }

test/unit_tests/flipflop/run/prsim.out

@@ -0,0 +1,9 @@
+t.clk t.d t.q t.ff._qb t.ff._q_B t.ff.__clk t.ff._dl t.ff._clk 
+[0] start test
+
+[1] reset completed
+WRONG ASSERT:	"t.q" has value 1 and not 0.
+[2] setting d to 1
+WRONG ASSERT:	"t.q" has value 1 and not 0.
+[3] setting clk to 1
+[4] Finished

test/unit_tests/flipflop/run/test.prs

@@ -0,0 +1,29 @@
+= "GND" "GND"
+= "Vdd" "Vdd"
+= "Reset" "Reset"
+"Reset"->"t._reset_B"-
+~("Reset")->"t._reset_B"+
+"t.ff._q_B"->"t.ff.q"-
+~"t.ff._q_B"->"t.ff.q"+
+"t.ff.clk"->"t.ff._clk"-
+~"t.ff.clk"->"t.ff._clk"+
+"t.ff._clk"->"t.ff.__clk"-
+~"t.ff._clk"->"t.ff.__clk"+
+"t.ff.reset"->"t.ff._Ro"-
+~"t.ff.reset"->"t.ff._Ro"+
+"t.ff.d"&"t.ff._clk"->"t.ff._dl"-
+~"t.ff.d"&~"t.ff.__clk"->"t.ff._dl"+
+"t.ff.reset"&"t.ff._qb"->"t.ff._q_B"-
+~"t.ff.reset"|~"t.ff._qb"->"t.ff._q_B"+
+after 0 "t.ff.__clk" & ~"t.ff._Ro" -> "t.ff._dl"-
+~"t.ff._clk" & "t.ff._Ro" -> "t.ff._dl"+
+after 0 "t.ff.__clk" & ~"t.ff.reset" -> "t.ff._qb"-
+~"t.ff._clk" & "t.ff.reset" -> "t.ff._qb"+
+after 0 "t.ff._clk" & ~"t.ff.reset" -> "t.ff._qb"-
+~"t.ff.__clk" & "t.ff.reset" -> "t.ff._qb"+
+= "Reset" "t.ff.reset"
+= "Vdd" "t.ff.vdd"
+= "GND" "t.ff.vss"
+= "t.q" "t.ff.q"
+= "t.clk" "t.ff.clk"
+= "t.d" "t.ff.d"

test/unit_tests/flipflop/test.act

@@ -0,0 +1,48 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/primitives.act";
+import globals;
+
+open tmpl::dataflow_neuro;
+
+defproc flipflop_test (bool! q; bool? d,clk){
+
+    DFFQ_R_X1 ff(.d=d,.clk = clk, .q = q);
+    //Low active Reset 
+    bool _reset_B; 
+    prs {
+    	Reset => _reset_B-
+    }
+    ff.vss = GND;
+    ff.vdd = Vdd;
+    ff.reset = Reset;
+    
+}
+
+flipflop_test t;

test/unit_tests/flipflop/test.prsim

@@ -0,0 +1,21 @@
+
+set t.d 0
+set t.clk 0
+set Reset 0
+cycle
+assert t.q 0
+system "echo '[0] start test'"
+set Reset 1
+cycle
+status X
+mode run
+system "echo '[1] reset completed'"
+system "echo '[2] setting d to 1'"
+set t.clk 1
+cycle
+assert t.q 0
+system "echo '[3] setting clk to 1'"
+set t.clk 1
+cycle
+assert t.q 1
+system "echo '[4] Finished'"