Added Demux

This commit is contained in:
Greatorex 2022-02-25 15:16:38 +01:00
commit e9f0f4ac0f
8 changed files with 158 additions and 54 deletions

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@ -517,11 +517,11 @@ namespace tmpl {
[keeper=0] ~a | ~_y2 -> _y1+ [keeper=0] ~a | ~_y2 -> _y1+
[keeper=0] b & _y1 -> _y2- [keeper=0] b & _y1 -> _y2-
[keeper=0] ~b | ~_y1 -> _y2+ [keeper=0] ~b | ~_y1 -> _y2+
[keeper=0] ~_y1 | ~c => y1+ [keeper=0] _y1 | c => y1-
[keeper=0] ~_y2 | ~d => y2+ [keeper=0] _y2 | d => y2-
} }
spec { spec {
mk_excllo(_y1, _y2) mk_excllo(y1, y2)
} }
} }
}} }}

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@ -326,17 +326,27 @@ namespace tmpl {
// sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX); // sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
// //validity // //validity
// bool _in1_v,_in2_v;
// //function // a1of1 _in1_temp,_in2_temp,_out_temp;
// ctree<N> vc1(.in=in1.d,.out=in1.v,.supply=supply);
// ctree<N> vc2(.in=in2.d,.out=in2.v,.supply=supply);
// arbiter_handshake validity_arb(.in1 = _in1_temp,.in2 = _in2_temp,.out =_out_temp)
// _in1_temp.r = in1.v
// _in2_temp.r = in2.v
// _in1_temp.a =
// _in1_temp.a =
// _out_temp.r = _out_temp.a
//function
// } // }
export
defproc arbiter_handshake(a1of1 in1; a1of1 in2; a1of1 out; power supply)
{
bool _y1_arb,_y2_arb;
// defproc arbiter_handshake(a1of1 in1; a1of1 in2; a1of1 out; power supply) A_2C_B_X1 ack_cell1(.c1 = out.a,.c2 = _y1_arb,.y = in1.a,.vdd = supply.vdd, .vss = supply.vss);
// { A_2C_B_X1 ack_cell2(.c1 = out.a,.c2 = _y2_arb,.y = in2.a,.vdd = supply.vdd, .vss = supply.vss);
// bool _y1_arb,_y2_arb; OR2_X1 or_cell(.a = _y1_arb, .b = _y2_arb, .y = out.r,.vdd = supply.vdd, .vss = supply.vss);
ARBITER arbiter(.a = in1.r, .b = in2.r, .c = in2.a, .d = in1.a, .y1 = _y1_arb, .y2 = _y2_arb, .vdd = supply.vdd, .vss = supply.vss);
// A_2C_B_X1 cel1(.c1 = out.a,.c2 = _y1_arb,.y = in2.a,.vdd = supply.vdd, .vss = supply.vss); }
// A_2C_B_X1 cel2(.c1 = out.a,.c2 = _y2_arb,.y = in1.a,.vdd = supply.vdd, .vss = supply.vss);
// OR2_X1 or_cell(.a = _y1_arb, .b = _y2_arb, .y = out.r,.vdd = supply.vdd, .vss = supply.vss);
// ARBITER arbiter(.a = in1.r, .b = in2.r, .c = in2.a, .d = in1.a, .y1 = _y1_arb, .y2 = _y2_arb, .vdd = supply.vdd, .vss = supply.vss);
// }
}} }}

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@ -107,6 +107,10 @@ Use -exclude='regex' to specify signals to exclude (or -ex).""")
colour_undefined = (255,0,0) colour_undefined = (255,0,0)
colour_high = (252, 186, 3) colour_high = (252, 186, 3)
colour_low = (20, 184, 186) colour_low = (20, 184, 186)
if argv[2] == "-color_Michele":
colour_undefined = (32,32,32)
colour_high = (98, 187, 93)
colour_low = (233, 115, 115)
fig = plt.figure(figsize = (num_sigs/3+4,num_times/3+4), dpi = 100) fig = plt.figure(figsize = (num_sigs/3+4,num_times/3+4), dpi = 100)

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@ -0,0 +1,36 @@
t.in1.r t.in2.r t.out.r t.a.arbiter._y1 t.a.arbiter._y2 t.out.a t.in1.a t.a._y1_arb t.a._y2_arb t.in2.a t.a.or_cell._y t.a.ack_cell1._y t.a.ack_cell2._y
0 t.in1.r : 0
0 t.out.a : 0
0 t.in2.r : 0
1 t.a.arbiter._y1 : 1 [by t.in1.r:=0]
7092 t.a.arbiter._y2 : 1 [by t.in2.r:=0]
10468 t.a._y1_arb : 0 [by t.a.arbiter._y1:=1]
15221 t.a.ack_cell1._y : 1 [by t.a._y1_arb:=0]
16358 t.in1.a : 0 [by t.a.ack_cell1._y:=1]
t.out.r t.a._y2_arb t.in2.a t.a.or_cell._y t.a.ack_cell2._y
[0] reset done
16358 t.in1.r : 1
WARNING: weak-interference `t.a._y1_arb'
>> cause: t.a.arbiter._y1 (val: 0)
>> time: 16472
16472 t.a.arbiter._y1 : 0 [by t.in1.r:=1]
81838 t.a._y1_arb : X [by t.a.arbiter._y1:=0]
WRONG ASSERT: "t.out.r" has value X and not 1.
81838 t.out.a : 1
WARNING: weak-interference `t.in1.a'
>> cause: t.a.ack_cell1._y (val: X)
>> time: 83564
83564 t.a.ack_cell1._y : X [by t.out.a:=1]
83603 t.in1.a : X [by t.a.ack_cell1._y:=X]
WRONG ASSERT: "t.in1.a" has value X and not 1.
[1] test in1 done
----------------------------------------------------------------------------------------------------
83603 t.in1.r : 0
83603 t.out.a : 0
83618 t.a.arbiter._y1 : 1 [by t.in1.r:=0]
84109 t.a._y1_arb : 0 [by t.a.arbiter._y1:=1]
84122 t.a.ack_cell1._y : 1 [by t.a._y1_arb:=0]
84162 t.in1.a : 0 [by t.a.ack_cell1._y:=1]
WRONG ASSERT: "t.out.r" has value X and not 0.
WRONG ASSERT: "t.in2.a" has value X and not 0.
[2] reset done

Binary file not shown.

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@ -1,3 +1,70 @@
= "GND" "GND" = "GND" "GND"
= "Vdd" "Vdd" = "Vdd" "Vdd"
= "Reset" "Reset" = "Reset" "Reset"
= "t.a.in1.d.d[0]" "t.a.in1.r"
= "t.a.in1.a" "t.a.arbiter.d"
= "t.a.in1.a" "t.a.ack_cell1.y"
= "t.a.in1.d.d[0]" "t.a.arbiter.a"
= "t.a.in1.d.d[0]" "t.a.in1.r"
~"t.a.ack_cell1.c1"&~"t.a.ack_cell1.c2"->"t.a.ack_cell1._y"+
"t.a.ack_cell1.c1"&"t.a.ack_cell1.c2"->"t.a.ack_cell1._y"-
"t.a.ack_cell1._y"->"t.a.ack_cell1.y"-
~("t.a.ack_cell1._y")->"t.a.ack_cell1.y"+
= "t.a.in2.d.d[0]" "t.a.in2.r"
= "t.a.in2.a" "t.a.arbiter.c"
= "t.a.in2.a" "t.a.ack_cell2.y"
= "t.a.in2.d.d[0]" "t.a.arbiter.b"
= "t.a.in2.d.d[0]" "t.a.in2.r"
= "t.a.supply.vdd" "t.a.arbiter.vdd"
= "t.a.supply.vdd" "t.a.or_cell.vdd"
= "t.a.supply.vdd" "t.a.ack_cell2.vdd"
= "t.a.supply.vdd" "t.a.ack_cell1.vdd"
= "t.a.supply.vss" "t.a.arbiter.vss"
= "t.a.supply.vss" "t.a.or_cell.vss"
= "t.a.supply.vss" "t.a.ack_cell2.vss"
= "t.a.supply.vss" "t.a.ack_cell1.vss"
"t.a.arbiter.a"&"t.a.arbiter._y2"->"t.a.arbiter._y1"-
~"t.a.arbiter.a"|~"t.a.arbiter._y2"->"t.a.arbiter._y1"+
"t.a.arbiter.b"&"t.a.arbiter._y1"->"t.a.arbiter._y2"-
~"t.a.arbiter.b"|~"t.a.arbiter._y1"->"t.a.arbiter._y2"+
"t.a.arbiter._y1"|"t.a.arbiter.c"->"t.a.arbiter.y1"-
~("t.a.arbiter._y1"|"t.a.arbiter.c")->"t.a.arbiter.y1"+
"t.a.arbiter._y2"|"t.a.arbiter.d"->"t.a.arbiter.y2"-
~("t.a.arbiter._y2"|"t.a.arbiter.d")->"t.a.arbiter.y2"+
mk_excllo("t.a.arbiter.y1","t.a.arbiter.y2")
= "t.a._y1_arb" "t.a.arbiter.y1"
= "t.a._y1_arb" "t.a.or_cell.a"
= "t.a._y1_arb" "t.a.ack_cell1.c2"
~"t.a.ack_cell2.c1"&~"t.a.ack_cell2.c2"->"t.a.ack_cell2._y"+
"t.a.ack_cell2.c1"&"t.a.ack_cell2.c2"->"t.a.ack_cell2._y"-
"t.a.ack_cell2._y"->"t.a.ack_cell2.y"-
~("t.a.ack_cell2._y")->"t.a.ack_cell2.y"+
"t.a.or_cell.a"|"t.a.or_cell.b"->"t.a.or_cell._y"-
~("t.a.or_cell.a"|"t.a.or_cell.b")->"t.a.or_cell._y"+
"t.a.or_cell._y"->"t.a.or_cell.y"-
~("t.a.or_cell._y")->"t.a.or_cell.y"+
= "t.a.out.d.d[0]" "t.a.out.r"
= "t.a.out.a" "t.a.ack_cell2.c1"
= "t.a.out.a" "t.a.ack_cell1.c1"
= "t.a.out.d.d[0]" "t.a.or_cell.y"
= "t.a.out.d.d[0]" "t.a.out.r"
= "t.a._y2_arb" "t.a.arbiter.y2"
= "t.a._y2_arb" "t.a.or_cell.b"
= "t.a._y2_arb" "t.a.ack_cell2.c2"
= "Vdd" "t.a.supply.vdd"
= "GND" "t.a.supply.vss"
= "t.in1.d.d[0]" "t.in1.r"
= "t.in1.r" "t.a.in1.r"
= "t.in1.a" "t.a.in1.a"
= "t.in1.d.d[0]" "t.a.in1.d.d[0]"
= "t.in1.d.d[0]" "t.in1.r"
= "t.out.d.d[0]" "t.out.r"
= "t.out.r" "t.a.out.r"
= "t.out.a" "t.a.out.a"
= "t.out.d.d[0]" "t.a.out.d.d[0]"
= "t.out.d.d[0]" "t.out.r"
= "t.in2.d.d[0]" "t.in2.r"
= "t.in2.r" "t.a.in2.r"
= "t.in2.a" "t.a.in2.a"
= "t.in2.d.d[0]" "t.a.in2.d.d[0]"
= "t.in2.d.d[0]" "t.in2.r"

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@ -33,9 +33,9 @@ open tmpl::dataflow_neuro;
defproc arbiter_test(a1of1 in1; a1of1 in2; a1of1 out) defproc arbiter_test(a1of1 in1; a1of1 in2; a1of1 out)
{ {
arbiter_handshake a(.in1 = in1, .in2 = in, .out = out); arbiter_handshake a(.in1 = in1, .in2 = in2, .out = out);
a.supply.vdd = Vdd; a.supply.vdd = Vdd;
a.supply.vss = Gnd; a.supply.vss = GND;
} }
arbiter_test t; arbiter_test t;

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@ -1,42 +1,29 @@
watchall watchall
cycle cycle
system "echo 'reset done'" set t.in1.r 0
t.in1.d 0 set t.in2.r 0
t.in2.d 0 set t.out.a 0
t.in1.v 0
t.in2.v 0
t.out.a 0
cycle cycle
status X status X
mode run mode run
system "echo 'step 1.1 finished'" system "echo '[0] reset done'"
set a.a 1
set a.b 1 set t.in1.r 1
advance 1000000 cycle
status X assert t.out.r 1
mode run set t.out.a 1
system "echo 'step 1.2 finished'" cycle
set a.a 0 assert t.in1.a 1
set a.b 0 system "echo '[1] test in1 done'"
advance 1000000 system "echo '----------------------------------------------------------------------------------------------------'"
status X set t.in1.r 0
mode run set t.in2.r 0
system "echo 'step 2.1 finished'" set t.out.a 0
set a.a 1 cycle
set a.b 1 assert t.out.r 0
advance 1000000 assert t.in1.a 0
status X assert t.in2.a 0
mode run system "echo '[2] reset done'"
system "echo 'step 2.2 finished'"
set a.a 0
set a.b 0
advance 1000000
status X
mode run
system "echo 'step 3.1 finished'"
set a.a 0
set a.b 1
advance 1000000
status X
mode run
system "echo 'step 3.2 finished'"