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register write array unit tests working

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This commit is contained in:
alexmadison
2022-04-02 17:16:20 +02:00
parent e995a78efb
commit eda9e2a98b
5 changed files with 11533 additions and 6 deletions
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9
dataflow_neuro/registers.act
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@ -418,6 +418,7 @@ defproc registerA_w_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M];
// Input valid tree
// Note that I may need to check the validity of other downstream stuff,
// to be ultra careful about delays.
// e.g. TODO add validity checking on the selector signals.
vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
.supply = supply);
@ -454,10 +455,10 @@ TIELO_X1 tielow_writebit_f[M];
)
// Connect the (selected) write bit
registers[i].in.d.d[NcA + NcW].t = write_selectors[i].y;
registers[i].in.d.d[NcW].t = write_selectors[i].y;
tielow_writebit_f[i].vdd = supply.vdd;
tielow_writebit_f[i].vss = supply.vss;
registers[i].in.d.d[NcA + NcW].f = tielow_writebit_f[i].y;
registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y;
// Connect to ack ortree
registers[i].in.a = ack_ortree.in[i];
@ -469,10 +470,6 @@ TIELO_X1 tielow_writebit_f[M];
registers[i].reset_B = reset_B;
)
}