created demultiplexer and tests, not working yet

dataflow_neuro/coders.act

@@ -1041,6 +1041,99 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; bool! out_req_x[Nx], out_req_y[
 		}
 
 
+	/**
+	 * 2D decoder which uses either synapse handshaking, or just a delay.
+	 * Controlled by the "hs_en" (handshake_enable) config bit.
+	 * hs_en = 0 -> use delayed version.
+	 * hs_en = 1 -> use synapse handshaking.
+	 * Regardless of which version is used, the final ack going to the buffer
+	 * goes through the prog_delay block.
+	 * Thus, for the handshaking version to be used "correctly", 
+	 * dly_cfg should be set to all zeros.
+	 * ack_disable blocks the ack being returned to the buffer.
+	 * Is needed in case there are instabilities while we fiddle with delays.
+	 */
+	 // @TODO : think hard about the fact that the line end pullups are not placed manually,
+	 // and write argumentation about whether this is fine
+	export template<pint N>
+	defproc decoder_1d (avMx1of2<std::ceil_log2(N)> in; a1of1 out[N];
+	bool? reset_B; power supply) {
+
+
+	// Buffer to recieve concat address packet
+	buffer<std::ceil_log2(N)> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
+
+	// Decoder And tree
+	decoder_dualrail_refresh<std::ceil_log2(N),N> d_dr(.supply = supply);
+	(i:0..std::ceil_log2(N)-1:d_dr.in.d[i] = addr_buf.out.d.d[i];)
+	(i:0..N-1: d_dr.out[i] = out[i].r;)
+
+
+	// Validity 
+	vtree<std::ceil_log2(N)> vtree (.in = d_dr.final_refresh, .supply = supply);
+	vtree.out = addr_buf.out.v;
+
+
+	// ORtree from all output acks, back to the buffer ack.
+	// This is instead of the ack that came from the delayed validity trees,
+	// in decoder_2d_dly.
+	ortree<N>  _ortree(.supply = supply);
+	(i:N:
+		_ortree.in[i] = out[i].a;
+	)
+	_ortree.out = addr_buf.out.a;
+
+
+	}
+
+	export template<pint N, W>
+	defproc demux_qdi2bd_1d (avMx1of2<std::ceil_log2(N)+W> in; rbd<W> out[N];
+	bool? reset_B; power supply) {
+
+	sigbuf<N+1> data_t[W];
+	(0..W-1:i:
+		data_t[i].in = addr_buf.out.d.d[std::ceil_log2(N)+i].t;
+		(0..N-1:j: 
+			data_t[i].out[j] = out[j].d.d[0];
+		)
+		data_t.supply = supply;
+	)
+
+
+	// Buffer to recieve concat address packet
+	buffer<std::ceil_log2(N)+W> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
+
+	// Decoder And tree
+	decoder_dualrail_refresh<std::ceil_log2(N),N> d_dr(.supply = supply);
+	(i:0..std::ceil_log2(N)-1:d_dr.in.d[i] = addr_buf.out.d.d[i];)
+	(i:0..N-1: d_dr.out[i] = out[i].r;)
+
+
+	// Validity 
+	vtree<std::ceil_log2(N)> vtree (.in = d_dr.final_refresh, .supply = supply);
+	vtree<W> vtree_data (.supply = supply);
+	(0..W-1:i: 
+		vtree_data.in[i].t = addr_buf.d.d[i+std::ceil_log2(N)].t;
+		vtree_data.in[i].f = data_t[i].out[N]
+
+	)
+	A_2C_B_X1 valid_Cel(.c1 = vtree.out, .c2 = vtree_data.out, .y = addr_buf.out.v,
+		.vdd = supply.vdd, .vss = supply.vss);
+
+	// ORtree from all output acks, back to the buffer ack.
+	// This is instead of the ack that came from the delayed validity trees,
+	// in decoder_2d_dly.
+	ortree<N>  _ortree(.supply = supply);
+	(i:N:
+		_ortree.in[i] = out[i].a;
+	)
+	_ortree.out = addr_buf.out.a;
+
+
+	}
+
+
+
 	}
 
 }

test/unit_tests/demux_qdi2bd_1d/test.act

@@ -0,0 +1,54 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2024 University of Groningen - Ole Richter  
+ *  Copyright (c) 2024 University of Groningen - Paolo Gibertini
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/primitives.act";
+import "../../dataflow_neuro/cell_lib_async.act";
+import "../../dataflow_neuro/cell_lib_std.act";
+
+
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc demux_qdi2bd_1d_test (avMx1of2<4> in; rbd<4> out[15]){
+
+    demux_qdi2bd_1d<15, 4> decoder_test(.in=in, .out=out);
+    //Low active Reset 
+    bool _reset_B; 
+    prs {
+    	Reset => _reset_B-
+    }
+    decoder_test.supply.vss = GND;
+    decoder_test.supply.vdd = Vdd;
+    decoder_test.reset_B = _reset_B;
+    
+}
+
+demux_qdi2bd_1d_test t;

test/unit_tests/demux_qdi2bd_1d/test.prsim

@@ -0,0 +1,73 @@
+
+set-qdi-channel-neutral "t.in" 4
+set t.out[0].a 0
+set t.out[1].a 0
+set t.out[2].a 0
+set t.out[3].a 0
+set t.out[4].a 0
+set t.out[5].a 0
+set t.out[6].a 0
+set t.out[7].a 0
+set t.out[8].a 0
+set t.out[9].a 0
+set t.out[10].a 0
+set t.out[11].a 0
+set t.out[12].a 0
+set t.out[13].a 0
+set t.out[14].a 0
+
+cycle
+system "echo 'reset start'"
+
+set Reset 0
+
+cycle
+system "echo 'reset completed'"
+status X
+mode run
+
+assert-bd-channel-neutral "t.out[0]" 4
+assert-bd-channel-neutral "t.out[1]" 4
+assert-bd-channel-neutral "t.out[2]" 4
+assert-bd-channel-neutral "t.out[3]" 4
+assert-bd-channel-neutral "t.out[4]" 4
+assert-bd-channel-neutral "t.out[5]" 4
+assert-bd-channel-neutral "t.out[6]" 4
+assert-bd-channel-neutral "t.out[7]" 4
+assert-bd-channel-neutral "t.out[8]" 4
+assert-bd-channel-neutral "t.out[9]" 4
+assert-bd-channel-neutral "t.out[10]" 4
+assert-bd-channel-neutral "t.out[11]" 4
+assert-bd-channel-neutral "t.out[12]" 4
+assert-bd-channel-neutral "t.out[13]" 4
+assert-bd-channel-neutral "t.out[14]" 4
+cycle
+
+set-qdi-channel-valid "t.in" 4 5
+cycle
+assert t.in.v 1
+assert-bd-channel-valid "t.out[0]" 4 0
+set t.out[5].a 1
+cycle
+assert t.in.a 1
+set-qdi-channel-neutral "t.in" 4
+cycle
+assert t.out[5].r 0
+set t.in.a 0
+cycle
+assert-bd-channel-neutral "t.out[0]" 4
+assert-bd-channel-neutral "t.out[1]" 4
+assert-bd-channel-neutral "t.out[2]" 4
+assert-bd-channel-neutral "t.out[3]" 4
+assert-bd-channel-neutral "t.out[4]" 4
+assert-bd-channel-neutral "t.out[5]" 4
+assert-bd-channel-neutral "t.out[6]" 4
+assert-bd-channel-neutral "t.out[7]" 4
+assert-bd-channel-neutral "t.out[8]" 4
+assert-bd-channel-neutral "t.out[9]" 4
+assert-bd-channel-neutral "t.out[10]" 4
+assert-bd-channel-neutral "t.out[11]" 4
+assert-bd-channel-neutral "t.out[12]" 4
+assert-bd-channel-neutral "t.out[13]" 4
+assert-bd-channel-neutral "t.out[14]" 4
+system "echo 'Finished'"