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flipflop updated

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This commit is contained in:
M. Mastella 2022-03-30 16:03:01 +02:00
parent 4cbe8cb3d1
commit f468913472
4 changed files with 63 additions and 53 deletions
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94
test/unit_tests/flipflop/run/prsim.out
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@ -1,49 +1,55 @@
t.ff.__clk_B t.ff._clk_B t.d t.clk t.ff.__clk_B t.ff._clk_B t.d t.clk t._clk_B
[0] start test [0] start test
61021 Reset : 0 15221 Reset : 0
61021 t.clk : 1 15221 t.clk : 0
61021 t.d : 0 15221 t.d : 0
61022 t.ff._clk_B : 0 [by t.clk:=1] 16947 t._clk_B : 1 [by t.clk:=0]
61023 t.ff.__clk_B : 1 [by t.ff._clk_B:=0] 16986 t.ff._clk_B : 0 [by t._clk_B:=1]
65875 t._reset_B : 1 [by Reset:=0] 17001 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
80587 t._reset_B : 1 [by Reset:=0]
[1] reset completed [1] reset completed
[2] tested d = 0, clk rise [2] tested d = 0, clk rise
65875 t.clk : 0 80587 t.clk : 1
65875 t.d : 1 80587 t.d : 1
84773 t.ff._mqib : 0 [by t.d:=1] 80600 t.ff._mqib : 0 [by t.d:=1]
85476 t.ff._mqi : 1 [by t.ff._mqib:=0] 80640 t.ff._mqi : 1 [by t.ff._mqib:=0]
96922 t.ff._clk_B : 1 [by t.clk:=0] 81078 t._clk_B : 0 [by t.clk:=1]
97123 t.ff.__clk_B : 0 [by t.ff._clk_B:=1] 81493 t.ff._clk_B : 1 [by t._clk_B:=0]
107244 t.ff._sqib : 0 [by t.ff._clk_B:=1] 81513 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
107250 t.ff._sqi : 1 [by t.ff._sqib:=0] 87554 t.ff._sqib : 0 [by t.ff._clk_B:=1]
110736 t.q : 1 [by t.ff._sqib:=0] 87570 t.q : 1 [by t.ff._sqib:=0]
110738 t.ff.q_B : 0 [by t.q:=1] 87601 t.ff._sqi : 1 [by t.ff._sqib:=0]
110738 t.clk : 1 131668 t.ff.q_B : 0 [by t.q:=1]
113054 t.ff._clk_B : 0 [by t.clk:=1] 131668 t.clk : 0
113104 t.ff.__clk_B : 1 [by t.ff._clk_B:=0] 145392 t._clk_B : 1 [by t.clk:=0]
113104 t.d : 0 145396 t.ff._clk_B : 0 [by t._clk_B:=1]
114289 t.ff._mqib : 1 [by t.d:=0] 154525 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
137967 t.ff._mqi : 0 [by t.ff._mqib:=1] 154525 t.d : 0
137967 t.clk : 0 154540 t.ff._mqib : 1 [by t.d:=0]
137992 t.ff._clk_B : 1 [by t.clk:=0] 197788 t.ff._mqi : 0 [by t.ff._mqib:=1]
138009 t.ff.__clk_B : 0 [by t.ff._clk_B:=1] 197788 t.clk : 1
138073 t.ff._sqib : 1 [by t.ff.__clk_B:=0] 234719 t._clk_B : 0 [by t.clk:=1]
138074 t.q : 0 [by t.ff._sqib:=1] 234774 t.ff._clk_B : 1 [by t._clk_B:=0]
138478 t.ff._sqi : 0 [by t.ff._sqib:=1] 286427 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
203221 t.ff.q_B : 1 [by t.q:=0] 316207 t.ff._sqib : 1 [by t.ff.__clk_B:=0]
203221 t.d : 1 330056 t.ff._sqi : 0 [by t.ff._sqib:=1]
203221 t.clk : 1 341019 t.q : 0 [by t.ff._sqib:=1]
203222 t.ff._clk_B : 0 [by t.clk:=1] 355362 t.ff.q_B : 1 [by t.q:=0]
214646 t.ff.__clk_B : 1 [by t.ff._clk_B:=0] 355362 t.clk : 0
227406 t.ff._mqib : 0 [by t.ff.__clk_B:=1] 355784 t._clk_B : 1 [by t.clk:=0]
227582 t.ff._mqi : 1 [by t.ff._mqib:=0] 404498 t.ff._clk_B : 0 [by t._clk_B:=1]
404499 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
404499 t.d : 1
404500 t.ff._mqib : 0 [by t.d:=1]
424705 t.ff._mqi : 1 [by t.ff._mqib:=0]
[3] tested d = 1, clk rise and fall [3] tested d = 1, clk rise and fall
227582 t.clk : 0 424705 t.clk : 1
227583 t.ff._clk_B : 1 [by t.clk:=0] 424987 t._clk_B : 0 [by t.clk:=1]
227590 t.ff._sqib : 0 [by t.ff._clk_B:=1] 425755 t.ff._clk_B : 1 [by t._clk_B:=0]
227593 t.q : 1 [by t.ff._sqib:=0] 425758 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
234776 t.ff.q_B : 0 [by t.q:=1] 448196 t.ff._sqib : 0 [by t.ff._clk_B:=1]
241004 t.ff._sqi : 1 [by t.ff._sqib:=0] 448747 t.ff._sqi : 1 [by t.ff._sqib:=0]
278221 t.ff.__clk_B : 0 [by t.ff._clk_B:=1] 449267 t.q : 1 [by t.ff._sqib:=0]
278221 t.d : 0 450221 t.ff.q_B : 0 [by t.q:=1]
450221 t.d : 0

4
test/unit_tests/flipflop/run/test.prs
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@ -3,6 +3,8 @@
= "Reset" "Reset" = "Reset" "Reset"
"Reset"->"t._reset_B"- "Reset"->"t._reset_B"-
~("Reset")->"t._reset_B"+ ~("Reset")->"t._reset_B"+
"t.clk"->"t._clk_B"-
~("t.clk")->"t._clk_B"+
= "t._reset_B" "t.ff.reset_B" = "t._reset_B" "t.ff.reset_B"
"t.ff.clk_B"->"t.ff._clk_B"- "t.ff.clk_B"->"t.ff._clk_B"-
~("t.ff.clk_B")->"t.ff._clk_B"+ ~("t.ff.clk_B")->"t.ff._clk_B"+
@ -23,5 +25,5 @@
= "Vdd" "t.ff.vdd" = "Vdd" "t.ff.vdd"
= "GND" "t.ff.vss" = "GND" "t.ff.vss"
= "t.q" "t.ff.q" = "t.q" "t.ff.q"
= "t.clk" "t.ff.clk_B" = "t._clk_B" "t.ff.clk_B"
= "t.d" "t.ff.d" = "t.d" "t.ff.d"

6
test/unit_tests/flipflop/test.act
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@ -32,13 +32,15 @@ import globals;
open tmpl::dataflow_neuro; open tmpl::dataflow_neuro;
defproc flipflop_test (bool! q; bool? d,clk){ defproc flipflop_test (bool! q; bool? d,clk){
bool _clk_B;
DFFQ_R_X1 ff(.d=d,.clk_B = clk, .q = q); DFFQ_R_X1 ff(.d=d,.clk_B = _clk_B, .q = q);
//Low active Reset //Low active Reset
bool _reset_B; bool _reset_B;
prs { prs {
Reset => _reset_B- Reset => _reset_B-
clk => _clk_B-
} }
ff.vss = GND; ff.vss = GND;
ff.vdd = Vdd; ff.vdd = Vdd;
ff.reset_B = _reset_B; ff.reset_B = _reset_B;

12
test/unit_tests/flipflop/test.prsim
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@ -3,7 +3,7 @@ system "echo '[0] start test'"
set Reset 0 set Reset 0
set t.d 0 set t.d 0
set t.clk 1 set t.clk 0
cycle cycle
status X status X
mode run mode run
@ -12,18 +12,18 @@ assert t.q 0
system "echo '[1] reset completed'" system "echo '[1] reset completed'"
system "echo '[2] tested d = 0, clk rise'" system "echo '[2] tested d = 0, clk rise'"
set t.clk 0 set t.clk 1
set t.d 1 set t.d 1
cycle cycle
set t.clk 1 set t.clk 0
cycle cycle
set t.d 0 set t.d 0
cycle cycle
assert t.q 1 assert t.q 1
set t.clk 0 set t.clk 1
cycle cycle
assert t.q 0 assert t.q 0
@ -35,7 +35,7 @@ assert t.q 0
set t.d 1 set t.d 1
cycle cycle
set t.clk 1 set t.clk 0
cycle cycle
assert t.q 0 assert t.q 0
@ -43,7 +43,7 @@ system "echo '[3] tested d = 1, clk rise and fall'"
set t.d 1 set t.d 1
cycle cycle
set t.clk 0 set t.clk 1
cycle cycle
set t.d 0 set t.d 0
cycle cycle