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alexmadison
2022-03-01 12:22:36 +01:00
parent c947b28b03
commit fc4ccea3c0
11 changed files with 698 additions and 2 deletions
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40
test/unit_tests/andtree_5/run/prsim.out Normal file
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t.in[0] t.in[2] t.at.tmp[5] t.in[3] t.at.C2Els[0]._y t.in[4] t.at.C3Els[0]._y t.at.tmp[6] t.in[1] t.out t.at.C2Els[1]._y
0
1
0 t.in[0] : 0
0 t.in[4] : 0
0 t.in[2] : 0
0 t.in[1] : 0
0 t.in[3] : 0
1 t.at.C2Els[0]._y : 1 [by t.in[0]:=0]
7092 t.at.C3Els[0]._y : 1 [by t.in[4]:=0]
7094 t.at.tmp[6] : 0 [by t.at.C3Els[0]._y:=1]
10468 t.at.tmp[5] : 0 [by t.at.C2Els[0]._y:=1]
11847 t.at.C2Els[1]._y : 1 [by t.at.tmp[6]:=0]
12984 t.out : 0 [by t.at.C2Els[1]._y:=1]
[] setting some bits high
12984 t.in[0] : 1
12984 t.in[2] : 1
12984 t.in[1] : 1
13098 t.at.C2Els[0]._y : 0 [by t.in[1]:=1]
78464 t.at.tmp[5] : 1 [by t.at.C2Els[0]._y:=0]
[] setting all bits high
78464 t.in[3] : 1
78464 t.in[4] : 1
80190 t.at.C3Els[0]._y : 0 [by t.in[4]:=1]
80229 t.at.tmp[6] : 1 [by t.at.C3Els[0]._y:=0]
80244 t.at.C2Els[1]._y : 0 [by t.at.tmp[6]:=1]
80735 t.out : 1 [by t.at.C2Els[1]._y:=0]
[] setting some low
80735 t.in[0] : 0
80735 t.in[1] : 0
80748 t.at.C2Els[0]._y : 1 [by t.in[0]:=0]
80788 t.at.tmp[5] : 0 [by t.at.C2Els[0]._y:=1]
81203 t.at.C2Els[1]._y : 1 [by t.at.tmp[5]:=0]
81223 t.out : 0 [by t.at.C2Els[1]._y:=1]
[] setting all low
81223 t.in[2] : 0
81223 t.in[4] : 0
81223 t.in[3] : 0
87284 t.at.C3Els[0]._y : 1 [by t.in[2]:=0]
87331 t.at.tmp[6] : 0 [by t.at.C3Els[0]._y:=1]

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test/unit_tests/andtree_5/run/prsim.pdf Normal file
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test/unit_tests/andtree_5/run/test.prs Normal file
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= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"t.at.C2Els[0].a"&"t.at.C2Els[0].b"->"t.at.C2Els[0]._y"-
~("t.at.C2Els[0].a"&"t.at.C2Els[0].b")->"t.at.C2Els[0]._y"+
"t.at.C2Els[0]._y"->"t.at.C2Els[0].y"-
~("t.at.C2Els[0]._y")->"t.at.C2Els[0].y"+
"t.at.C2Els[1].a"&"t.at.C2Els[1].b"->"t.at.C2Els[1]._y"-
~("t.at.C2Els[1].a"&"t.at.C2Els[1].b")->"t.at.C2Els[1]._y"+
"t.at.C2Els[1]._y"->"t.at.C2Els[1].y"-
~("t.at.C2Els[1]._y")->"t.at.C2Els[1].y"+
"t.at.C3Els[0].a"&"t.at.C3Els[0].b"&"t.at.C3Els[0].c"->"t.at.C3Els[0]._y"-
~("t.at.C3Els[0].a"&"t.at.C3Els[0].b"&"t.at.C3Els[0].c")->"t.at.C3Els[0]._y"+
"t.at.C3Els[0]._y"->"t.at.C3Els[0].y"-
~("t.at.C3Els[0]._y")->"t.at.C3Els[0].y"+
= "t.at.tmp[5]" "t.at.C2Els[1].a"
= "t.at.tmp[5]" "t.at.C2Els[0].y"
= "t.at.tmp[6]" "t.at.C2Els[1].b"
= "t.at.tmp[6]" "t.at.C3Els[0].y"
= "t.at.supply.vdd" "t.at.C3Els[0].vdd"
= "t.at.supply.vdd" "t.at.C2Els[1].vdd"
= "t.at.supply.vdd" "t.at.C2Els[0].vdd"
= "t.at.supply.vss" "t.at.C3Els[0].vss"
= "t.at.supply.vss" "t.at.C2Els[1].vss"
= "t.at.supply.vss" "t.at.C2Els[0].vss"
= "t.at.in[0]" "t.at.C2Els[0].a"
= "t.at.in[0]" "t.at.tmp[0]"
= "t.at.in[1]" "t.at.C2Els[0].b"
= "t.at.in[1]" "t.at.tmp[1]"
= "t.at.in[2]" "t.at.C3Els[0].a"
= "t.at.in[2]" "t.at.tmp[2]"
= "t.at.in[3]" "t.at.C3Els[0].b"
= "t.at.in[3]" "t.at.tmp[3]"
= "t.at.in[4]" "t.at.C3Els[0].c"
= "t.at.in[4]" "t.at.tmp[4]"
= "t.at.out" "t.at.C2Els[1].y"
= "t.at.out" "t.at.tmp[7]"
= "Vdd" "t.at.supply.vdd"
= "GND" "t.at.supply.vss"
= "t.out" "t.at.out"
= "t.in[0]" "t.at.in[0]"
= "t.in[1]" "t.at.in[1]"
= "t.in[2]" "t.at.in[2]"
= "t.in[3]" "t.at.in[3]"
= "t.in[4]" "t.at.in[4]"

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test/unit_tests/andtree_5/test.act Normal file
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/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/treegates.act";
import globals;
open tmpl::dataflow_neuro;
defproc andtree_5 (bool? in[5]; bool! out){
andtree<5> at(.in=in, .out=out);
at.supply.vss = GND;
at.supply.vdd = Vdd;
}
andtree_5 t;

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test/unit_tests/andtree_5/test.prsim Normal file
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watchall
system "echo '0'"
set t.in[0] 0
set t.in[1] 0
set t.in[2] 0
set t.in[3] 0
set t.in[4] 0
system "echo '1'"
cycle
mode run
assert t.out 0
system "echo '[] setting some bits high'"
set t.in[0] 1
set t.in[1] 1
set t.in[2] 1
cycle
assert t.out 0
system "echo '[] setting all bits high'"
set t.in[3] 1
set t.in[4] 1
cycle
assert t.out 1
system "echo '[] setting some low'"
set t.in[0] 0
set t.in[1] 0
cycle
assert t.out 0
system "echo '[] setting all low'"
set t.in[2] 0
set t.in[3] 0
set t.in[4] 0
cycle
assert t.out 0