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40
test/unit_tests/andtree_5/run/prsim.out
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40
test/unit_tests/andtree_5/run/prsim.out
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t.in[0] t.in[2] t.at.tmp[5] t.in[3] t.at.C2Els[0]._y t.in[4] t.at.C3Els[0]._y t.at.tmp[6] t.in[1] t.out t.at.C2Els[1]._y
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0
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1
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0 t.in[0] : 0
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0 t.in[4] : 0
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0 t.in[2] : 0
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0 t.in[1] : 0
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0 t.in[3] : 0
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1 t.at.C2Els[0]._y : 1 [by t.in[0]:=0]
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7092 t.at.C3Els[0]._y : 1 [by t.in[4]:=0]
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7094 t.at.tmp[6] : 0 [by t.at.C3Els[0]._y:=1]
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10468 t.at.tmp[5] : 0 [by t.at.C2Els[0]._y:=1]
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11847 t.at.C2Els[1]._y : 1 [by t.at.tmp[6]:=0]
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12984 t.out : 0 [by t.at.C2Els[1]._y:=1]
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[] setting some bits high
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12984 t.in[0] : 1
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12984 t.in[2] : 1
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12984 t.in[1] : 1
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13098 t.at.C2Els[0]._y : 0 [by t.in[1]:=1]
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78464 t.at.tmp[5] : 1 [by t.at.C2Els[0]._y:=0]
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[] setting all bits high
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78464 t.in[3] : 1
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78464 t.in[4] : 1
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80190 t.at.C3Els[0]._y : 0 [by t.in[4]:=1]
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80229 t.at.tmp[6] : 1 [by t.at.C3Els[0]._y:=0]
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80244 t.at.C2Els[1]._y : 0 [by t.at.tmp[6]:=1]
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80735 t.out : 1 [by t.at.C2Els[1]._y:=0]
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[] setting some low
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80735 t.in[0] : 0
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80735 t.in[1] : 0
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80748 t.at.C2Els[0]._y : 1 [by t.in[0]:=0]
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80788 t.at.tmp[5] : 0 [by t.at.C2Els[0]._y:=1]
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81203 t.at.C2Els[1]._y : 1 [by t.at.tmp[5]:=0]
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81223 t.out : 0 [by t.at.C2Els[1]._y:=1]
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[] setting all low
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81223 t.in[2] : 0
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81223 t.in[4] : 0
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81223 t.in[3] : 0
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87284 t.at.C3Els[0]._y : 1 [by t.in[2]:=0]
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87331 t.at.tmp[6] : 0 [by t.at.C3Els[0]._y:=1]
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BIN
test/unit_tests/andtree_5/run/prsim.pdf
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BIN
test/unit_tests/andtree_5/run/prsim.pdf
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Binary file not shown.
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test/unit_tests/andtree_5/run/test.prs
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test/unit_tests/andtree_5/run/test.prs
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= "GND" "GND"
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= "Vdd" "Vdd"
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= "Reset" "Reset"
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"t.at.C2Els[0].a"&"t.at.C2Els[0].b"->"t.at.C2Els[0]._y"-
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~("t.at.C2Els[0].a"&"t.at.C2Els[0].b")->"t.at.C2Els[0]._y"+
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"t.at.C2Els[0]._y"->"t.at.C2Els[0].y"-
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~("t.at.C2Els[0]._y")->"t.at.C2Els[0].y"+
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"t.at.C2Els[1].a"&"t.at.C2Els[1].b"->"t.at.C2Els[1]._y"-
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~("t.at.C2Els[1].a"&"t.at.C2Els[1].b")->"t.at.C2Els[1]._y"+
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"t.at.C2Els[1]._y"->"t.at.C2Els[1].y"-
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~("t.at.C2Els[1]._y")->"t.at.C2Els[1].y"+
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"t.at.C3Els[0].a"&"t.at.C3Els[0].b"&"t.at.C3Els[0].c"->"t.at.C3Els[0]._y"-
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~("t.at.C3Els[0].a"&"t.at.C3Els[0].b"&"t.at.C3Els[0].c")->"t.at.C3Els[0]._y"+
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"t.at.C3Els[0]._y"->"t.at.C3Els[0].y"-
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~("t.at.C3Els[0]._y")->"t.at.C3Els[0].y"+
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= "t.at.tmp[5]" "t.at.C2Els[1].a"
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= "t.at.tmp[5]" "t.at.C2Els[0].y"
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= "t.at.tmp[6]" "t.at.C2Els[1].b"
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= "t.at.tmp[6]" "t.at.C3Els[0].y"
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= "t.at.supply.vdd" "t.at.C3Els[0].vdd"
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= "t.at.supply.vdd" "t.at.C2Els[1].vdd"
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= "t.at.supply.vdd" "t.at.C2Els[0].vdd"
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= "t.at.supply.vss" "t.at.C3Els[0].vss"
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= "t.at.supply.vss" "t.at.C2Els[1].vss"
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= "t.at.supply.vss" "t.at.C2Els[0].vss"
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= "t.at.in[0]" "t.at.C2Els[0].a"
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= "t.at.in[0]" "t.at.tmp[0]"
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= "t.at.in[1]" "t.at.C2Els[0].b"
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= "t.at.in[1]" "t.at.tmp[1]"
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= "t.at.in[2]" "t.at.C3Els[0].a"
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= "t.at.in[2]" "t.at.tmp[2]"
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= "t.at.in[3]" "t.at.C3Els[0].b"
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= "t.at.in[3]" "t.at.tmp[3]"
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= "t.at.in[4]" "t.at.C3Els[0].c"
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= "t.at.in[4]" "t.at.tmp[4]"
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= "t.at.out" "t.at.C2Els[1].y"
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= "t.at.out" "t.at.tmp[7]"
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= "Vdd" "t.at.supply.vdd"
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= "GND" "t.at.supply.vss"
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= "t.out" "t.at.out"
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= "t.in[0]" "t.at.in[0]"
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= "t.in[1]" "t.at.in[1]"
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= "t.in[2]" "t.at.in[2]"
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= "t.in[3]" "t.at.in[3]"
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= "t.in[4]" "t.at.in[4]"
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