added and tree
This commit is contained in:
alexmadison
parent
c947b28b03
commit
fc4ccea3c0
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@ -3,6 +3,9 @@
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* This file is part of ACT dataflow neuro library
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* This file is part of ACT dataflow neuro library
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*
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2021 Rajit Manohar
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* Copyright (c) 2021 Rajit Manohar
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*
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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@ -79,12 +82,121 @@ defproc ortree (bool? in[N]; bool! out; power supply)
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/* array to hold the actual C-elments, either A2C or A3C */
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/* array to hold the actual C-elments, either A2C or A3C */
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[lenTree2Count > 0 ->
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[lenTree2Count > 0 ->
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OR2_X1 C2Els[lenTree2Count];
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OR2_X1 C2Els[lenTree2Count];
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]
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]
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[lenTree3Count > 0 ->
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[lenTree3Count > 0 ->
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OR3_X1 C3Els[lenTree3Count];
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OR3_X1 C3Els[lenTree3Count];
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]
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(h:lenTree2Count:C2Els[h].vdd = supply.vdd;)
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(h:lenTree3Count:C3Els[h].vdd = supply.vdd;)
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(h:lenTree2Count:C2Els[h].vss = supply.vss;)
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(h:lenTree3Count:C3Els[h].vss = supply.vss;)
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/* Reset the variables we just stole lol */
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i = 0;
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end = N-1;
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j = 0;
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pint tree2Index = 0;
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pint tree3Index = 0;
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/* Invariant: i <= end */
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*[ i != end ->
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/*
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* Invariant: tmp[i..end] has the current signals that need to be
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* combined together, and "isinv" specifies if they are the inverted
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* sense or not
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*/
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j = 0;
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*[ i < end ->
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/*-- there are still signals that need to be combined --*/
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j = j + 1;
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[ i+1 >= end ->
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/*-- last piece: use either a 2 input C-element --*/
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C2Els[tree2Index].a = tmp[i];
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C2Els[tree2Index].b = tmp[i+1];
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C2Els[tree2Index].y = tmp[end+j];
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tree2Index = tree2Index +1;
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i = end;
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[] i+2 >= end ->
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/*-- last piece: use either a 3 input C-element --*/
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C3Els[tree3Index].a = tmp[i];
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C3Els[tree3Index].b = tmp[i+1];
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C3Els[tree3Index].c = tmp[i+2];
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C3Els[tree3Index].y = tmp[end+j];
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tree3Index = tree3Index +1;
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i = end;
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[] else ->
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/*-- more to come; so use a two input C-element --*/
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C2Els[tree2Index].a = tmp[i];
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C2Els[tree2Index].b = tmp[i+1];
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C2Els[tree2Index].y = tmp[end+j];
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tree2Index = tree2Index +1;
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i = i + 2;
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]
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]
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/*-- update range that has to be combined --*/
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i = end+1;
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end = end+j;
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j = 0;
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]
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out = tmp[end];
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}
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export template<pint N>
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defproc andtree (bool? in[N]; bool! out; power supply)
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{
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bool tout;
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{ N > 0 : "What?" };
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pint i, end, j;
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i = 0;
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end = N-1;
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pint lenTree2Count, lenTree3Count;
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lenTree2Count = 0;
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lenTree3Count = 0;
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/* Pre"calculate" the number of C cells required, look below if confused */
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*[ i != end ->
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j = 0;
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*[ i < end ->
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j = j + 1;
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[ i+1 >= end ->
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i = end;
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lenTree2Count = lenTree2Count +1;
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[] i+2 >= end ->
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i = end;
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lenTree3Count = lenTree3Count +1;
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[] else ->
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i = i + 2;
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lenTree2Count = lenTree2Count +1;
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]
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]
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/*-- update range that has to be combined --*/
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i = end+1;
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end = end+j;
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j = 0;
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]
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/* array that holds ALL the nodes in the completion tree */
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bool tmp[end+1];
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(k:N:tmp[k] = in[k];)
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/* array to hold the actual C-elments, either A2C or A3C */
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[lenTree2Count > 0 ->
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AND2_X1 C2Els[lenTree2Count];
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]
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[lenTree3Count > 0 ->
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AND3_X1 C3Els[lenTree3Count];
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]
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]
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(h:lenTree2Count:C2Els[h].vdd = supply.vdd;)
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(h:lenTree2Count:C2Els[h].vdd = supply.vdd;)
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@ -0,0 +1,118 @@
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t.in[0] t.at.tmp[22] t.in[5] t.in[2] t.at.tmp[15] t.in[3] t.at.tmp[23] t.at.C2Els[0]._y t.in[7] t.in[6] t.at.C2Els[3]._y t.in[4] t.at.C3Els[0]._y t.in[12] t.out t.at.tmp[21] t.at.C2Els[6]._y t.in[11] t.at.tmp[17] t.in[14] t.in[1] t.in[10] t.in[9] t.at.C2Els[5]._y t.at.tmp[19] t.at.tmp[20] t.at.tmp[24] t.in[13] t.at.tmp[16] t.at.C2Els[4]._y t.in[8] t.at.tmp[18] t.at.C2Els[2]._y t.at.C3Els[2]._y t.at.C2Els[1]._y t.at.C2Els[7]._y t.at.C3Els[1]._y
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0
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1
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0 t.in[0] : 0
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0 t.in[14] : 0
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0 t.in[2] : 0
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0 t.in[6] : 0
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0 t.in[13] : 0
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0 t.in[5] : 0
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0 t.in[12] : 0
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0 t.in[11] : 0
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0 t.in[1] : 0
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0 t.in[4] : 0
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0 t.in[10] : 0
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0 t.in[9] : 0
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0 t.in[3] : 0
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0 t.in[8] : 0
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0 t.in[7] : 0
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1 t.at.C2Els[0]._y : 1 [by t.in[0]:=0]
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2 t.at.C2Els[3]._y : 1 [by t.in[6]:=0]
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114 t.at.C2Els[4]._y : 1 [by t.in[9]:=0]
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153 t.at.tmp[19] : 0 [by t.at.C2Els[4]._y:=1]
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168 t.at.C3Els[1]._y : 1 [by t.at.tmp[19]:=0]
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659 t.at.tmp[24] : 0 [by t.at.C3Els[1]._y:=1]
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672 t.at.C3Els[2]._y : 1 [by t.at.tmp[24]:=0]
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712 t.out : 0 [by t.at.C3Els[2]._y:=1]
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1137 t.at.C2Els[5]._y : 1 [by t.in[11]:=0]
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1552 t.at.tmp[20] : 0 [by t.at.C2Els[5]._y:=1]
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1728 t.at.tmp[18] : 0 [by t.at.C2Els[3]._y:=1]
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1748 t.at.C2Els[7]._y : 1 [by t.at.tmp[18]:=0]
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4753 t.at.C2Els[2]._y : 1 [by t.in[5]:=0]
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4800 t.at.tmp[17] : 0 [by t.at.C2Els[2]._y:=1]
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7092 t.at.C3Els[0]._y : 1 [by t.in[14]:=0]
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7108 t.at.tmp[21] : 0 [by t.at.C3Els[0]._y:=1]
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7809 t.at.tmp[23] : 0 [by t.at.C2Els[7]._y:=1]
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10467 t.at.C2Els[1]._y : 1 [by t.in[2]:=0]
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54565 t.at.tmp[16] : 0 [by t.at.C2Els[1]._y:=1]
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65367 t.at.tmp[15] : 0 [by t.at.C2Els[0]._y:=1]
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68289 t.at.C2Els[6]._y : 1 [by t.at.tmp[16]:=0]
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68293 t.at.tmp[22] : 0 [by t.at.C2Els[6]._y:=1]
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[] setting some bits high
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68293 t.in[0] : 1
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68293 t.in[11] : 1
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68293 t.in[10] : 1
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68293 t.in[9] : 1
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68293 t.in[2] : 1
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68293 t.in[8] : 1
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68293 t.in[7] : 1
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68293 t.in[6] : 1
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68293 t.in[5] : 1
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68293 t.in[1] : 1
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68293 t.in[4] : 1
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68293 t.in[3] : 1
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68308 t.at.C2Els[4]._y : 0 [by t.in[8]:=1]
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68348 t.at.C2Els[2]._y : 0 [by t.in[4]:=1]
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77422 t.at.C2Els[5]._y : 0 [by t.in[10]:=1]
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82197 t.at.tmp[17] : 1 [by t.at.C2Els[2]._y:=0]
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98088 t.at.tmp[19] : 1 [by t.at.C2Els[4]._y:=0]
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102234 t.at.tmp[20] : 1 [by t.at.C2Els[5]._y:=0]
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105224 t.at.C2Els[0]._y : 0 [by t.in[1]:=1]
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111541 t.at.C2Els[3]._y : 0 [by t.in[6]:=1]
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111963 t.at.tmp[18] : 1 [by t.at.C2Els[3]._y:=0]
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119567 t.at.tmp[15] : 1 [by t.at.C2Els[0]._y:=0]
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119946 t.at.C2Els[1]._y : 0 [by t.in[3]:=1]
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119947 t.at.tmp[16] : 1 [by t.at.C2Els[1]._y:=0]
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119948 t.at.C2Els[6]._y : 0 [by t.at.tmp[16]:=1]
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140153 t.at.tmp[22] : 1 [by t.at.C2Els[6]._y:=0]
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160677 t.at.C2Els[7]._y : 0 [by t.at.tmp[18]:=1]
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160959 t.at.tmp[23] : 1 [by t.at.C2Els[7]._y:=0]
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[] setting all bits high
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160959 t.in[12] : 1
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160959 t.in[14] : 1
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160959 t.in[13] : 1
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161727 t.at.C3Els[0]._y : 0 [by t.in[13]:=1]
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161730 t.at.tmp[21] : 1 [by t.at.C3Els[0]._y:=0]
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184171 t.at.C3Els[1]._y : 0 [by t.at.tmp[21]:=1]
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184722 t.at.tmp[24] : 1 [by t.at.C3Els[1]._y:=0]
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185793 t.at.C3Els[2]._y : 0 [by t.at.tmp[24]:=1]
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186747 t.out : 1 [by t.at.C3Els[2]._y:=0]
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[] setting some low
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186747 t.in[10] : 0
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187828 t.at.C2Els[5]._y : 1 [by t.in[10]:=0]
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242298 t.at.tmp[20] : 0 [by t.at.C2Els[5]._y:=1]
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243280 t.at.C3Els[1]._y : 1 [by t.at.tmp[20]:=0]
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243298 t.at.tmp[24] : 0 [by t.at.C3Els[1]._y:=1]
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247311 t.at.C3Els[2]._y : 1 [by t.at.tmp[24]:=0]
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251314 t.out : 0 [by t.at.C3Els[2]._y:=1]
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[] setting all low
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251314 t.in[0] : 0
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251314 t.in[14] : 0
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251314 t.in[2] : 0
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251314 t.in[6] : 0
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251314 t.in[5] : 0
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251314 t.in[13] : 0
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251314 t.in[12] : 0
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251314 t.in[1] : 0
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251314 t.in[4] : 0
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251314 t.in[11] : 0
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251314 t.in[9] : 0
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251314 t.in[3] : 0
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251314 t.in[8] : 0
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251314 t.in[7] : 0
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251517 t.at.C2Els[2]._y : 1 [by t.in[5]:=0]
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251656 t.at.tmp[17] : 0 [by t.at.C2Els[2]._y:=1]
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251816 t.at.C2Els[3]._y : 1 [by t.in[6]:=0]
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251885 t.at.tmp[18] : 0 [by t.at.C2Els[3]._y:=1]
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253168 t.at.C2Els[4]._y : 1 [by t.in[9]:=0]
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253179 t.at.tmp[19] : 0 [by t.at.C2Els[4]._y:=1]
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256074 t.at.C2Els[1]._y : 1 [by t.in[2]:=0]
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272898 t.at.C3Els[0]._y : 1 [by t.in[14]:=0]
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273102 t.at.tmp[21] : 0 [by t.at.C3Els[0]._y:=1]
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288002 t.at.C2Els[7]._y : 1 [by t.at.tmp[17]:=0]
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288017 t.at.tmp[23] : 0 [by t.at.C2Els[7]._y:=1]
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296215 t.at.C2Els[0]._y : 1 [by t.in[0]:=0]
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296216 t.at.tmp[15] : 0 [by t.at.C2Els[0]._y:=1]
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296253 t.at.C2Els[6]._y : 1 [by t.at.tmp[15]:=0]
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296992 t.at.tmp[22] : 0 [by t.at.C2Els[6]._y:=1]
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307860 t.at.tmp[16] : 0 [by t.at.C2Els[1]._y:=1]
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Binary file not shown.
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@ -0,0 +1,139 @@
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= "GND" "GND"
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= "Vdd" "Vdd"
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= "Reset" "Reset"
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"t.at.C2Els[0].a"&"t.at.C2Els[0].b"->"t.at.C2Els[0]._y"-
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~("t.at.C2Els[0].a"&"t.at.C2Els[0].b")->"t.at.C2Els[0]._y"+
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"t.at.C2Els[0]._y"->"t.at.C2Els[0].y"-
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~("t.at.C2Els[0]._y")->"t.at.C2Els[0].y"+
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"t.at.C2Els[1].a"&"t.at.C2Els[1].b"->"t.at.C2Els[1]._y"-
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~("t.at.C2Els[1].a"&"t.at.C2Els[1].b")->"t.at.C2Els[1]._y"+
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"t.at.C2Els[1]._y"->"t.at.C2Els[1].y"-
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~("t.at.C2Els[1]._y")->"t.at.C2Els[1].y"+
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"t.at.C2Els[2].a"&"t.at.C2Els[2].b"->"t.at.C2Els[2]._y"-
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~("t.at.C2Els[2].a"&"t.at.C2Els[2].b")->"t.at.C2Els[2]._y"+
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"t.at.C2Els[2]._y"->"t.at.C2Els[2].y"-
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~("t.at.C2Els[2]._y")->"t.at.C2Els[2].y"+
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"t.at.C2Els[3].a"&"t.at.C2Els[3].b"->"t.at.C2Els[3]._y"-
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~("t.at.C2Els[3].a"&"t.at.C2Els[3].b")->"t.at.C2Els[3]._y"+
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"t.at.C2Els[3]._y"->"t.at.C2Els[3].y"-
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||||||
|
~("t.at.C2Els[3]._y")->"t.at.C2Els[3].y"+
|
||||||
|
"t.at.C2Els[4].a"&"t.at.C2Els[4].b"->"t.at.C2Els[4]._y"-
|
||||||
|
~("t.at.C2Els[4].a"&"t.at.C2Els[4].b")->"t.at.C2Els[4]._y"+
|
||||||
|
"t.at.C2Els[4]._y"->"t.at.C2Els[4].y"-
|
||||||
|
~("t.at.C2Els[4]._y")->"t.at.C2Els[4].y"+
|
||||||
|
"t.at.C2Els[5].a"&"t.at.C2Els[5].b"->"t.at.C2Els[5]._y"-
|
||||||
|
~("t.at.C2Els[5].a"&"t.at.C2Els[5].b")->"t.at.C2Els[5]._y"+
|
||||||
|
"t.at.C2Els[5]._y"->"t.at.C2Els[5].y"-
|
||||||
|
~("t.at.C2Els[5]._y")->"t.at.C2Els[5].y"+
|
||||||
|
"t.at.C2Els[6].a"&"t.at.C2Els[6].b"->"t.at.C2Els[6]._y"-
|
||||||
|
~("t.at.C2Els[6].a"&"t.at.C2Els[6].b")->"t.at.C2Els[6]._y"+
|
||||||
|
"t.at.C2Els[6]._y"->"t.at.C2Els[6].y"-
|
||||||
|
~("t.at.C2Els[6]._y")->"t.at.C2Els[6].y"+
|
||||||
|
"t.at.C2Els[7].a"&"t.at.C2Els[7].b"->"t.at.C2Els[7]._y"-
|
||||||
|
~("t.at.C2Els[7].a"&"t.at.C2Els[7].b")->"t.at.C2Els[7]._y"+
|
||||||
|
"t.at.C2Els[7]._y"->"t.at.C2Els[7].y"-
|
||||||
|
~("t.at.C2Els[7]._y")->"t.at.C2Els[7].y"+
|
||||||
|
"t.at.C3Els[0].a"&"t.at.C3Els[0].b"&"t.at.C3Els[0].c"->"t.at.C3Els[0]._y"-
|
||||||
|
~("t.at.C3Els[0].a"&"t.at.C3Els[0].b"&"t.at.C3Els[0].c")->"t.at.C3Els[0]._y"+
|
||||||
|
"t.at.C3Els[0]._y"->"t.at.C3Els[0].y"-
|
||||||
|
~("t.at.C3Els[0]._y")->"t.at.C3Els[0].y"+
|
||||||
|
"t.at.C3Els[1].a"&"t.at.C3Els[1].b"&"t.at.C3Els[1].c"->"t.at.C3Els[1]._y"-
|
||||||
|
~("t.at.C3Els[1].a"&"t.at.C3Els[1].b"&"t.at.C3Els[1].c")->"t.at.C3Els[1]._y"+
|
||||||
|
"t.at.C3Els[1]._y"->"t.at.C3Els[1].y"-
|
||||||
|
~("t.at.C3Els[1]._y")->"t.at.C3Els[1].y"+
|
||||||
|
"t.at.C3Els[2].a"&"t.at.C3Els[2].b"&"t.at.C3Els[2].c"->"t.at.C3Els[2]._y"-
|
||||||
|
~("t.at.C3Els[2].a"&"t.at.C3Els[2].b"&"t.at.C3Els[2].c")->"t.at.C3Els[2]._y"+
|
||||||
|
"t.at.C3Els[2]._y"->"t.at.C3Els[2].y"-
|
||||||
|
~("t.at.C3Els[2]._y")->"t.at.C3Els[2].y"+
|
||||||
|
= "t.at.tmp[15]" "t.at.C2Els[6].a"
|
||||||
|
= "t.at.tmp[15]" "t.at.C2Els[0].y"
|
||||||
|
= "t.at.tmp[16]" "t.at.C2Els[6].b"
|
||||||
|
= "t.at.tmp[16]" "t.at.C2Els[1].y"
|
||||||
|
= "t.at.tmp[17]" "t.at.C2Els[7].a"
|
||||||
|
= "t.at.tmp[17]" "t.at.C2Els[2].y"
|
||||||
|
= "t.at.tmp[18]" "t.at.C2Els[7].b"
|
||||||
|
= "t.at.tmp[18]" "t.at.C2Els[3].y"
|
||||||
|
= "t.at.tmp[19]" "t.at.C3Els[1].a"
|
||||||
|
= "t.at.tmp[19]" "t.at.C2Els[4].y"
|
||||||
|
= "t.at.tmp[20]" "t.at.C3Els[1].b"
|
||||||
|
= "t.at.tmp[20]" "t.at.C2Els[5].y"
|
||||||
|
= "t.at.tmp[21]" "t.at.C3Els[1].c"
|
||||||
|
= "t.at.tmp[21]" "t.at.C3Els[0].y"
|
||||||
|
= "t.at.tmp[22]" "t.at.C3Els[2].a"
|
||||||
|
= "t.at.tmp[22]" "t.at.C2Els[6].y"
|
||||||
|
= "t.at.tmp[23]" "t.at.C3Els[2].b"
|
||||||
|
= "t.at.tmp[23]" "t.at.C2Els[7].y"
|
||||||
|
= "t.at.tmp[24]" "t.at.C3Els[2].c"
|
||||||
|
= "t.at.tmp[24]" "t.at.C3Els[1].y"
|
||||||
|
= "t.at.supply.vdd" "t.at.C3Els[2].vdd"
|
||||||
|
= "t.at.supply.vdd" "t.at.C3Els[1].vdd"
|
||||||
|
= "t.at.supply.vdd" "t.at.C3Els[0].vdd"
|
||||||
|
= "t.at.supply.vdd" "t.at.C2Els[7].vdd"
|
||||||
|
= "t.at.supply.vdd" "t.at.C2Els[6].vdd"
|
||||||
|
= "t.at.supply.vdd" "t.at.C2Els[5].vdd"
|
||||||
|
= "t.at.supply.vdd" "t.at.C2Els[4].vdd"
|
||||||
|
= "t.at.supply.vdd" "t.at.C2Els[3].vdd"
|
||||||
|
= "t.at.supply.vdd" "t.at.C2Els[2].vdd"
|
||||||
|
= "t.at.supply.vdd" "t.at.C2Els[1].vdd"
|
||||||
|
= "t.at.supply.vdd" "t.at.C2Els[0].vdd"
|
||||||
|
= "t.at.supply.vss" "t.at.C3Els[2].vss"
|
||||||
|
= "t.at.supply.vss" "t.at.C3Els[1].vss"
|
||||||
|
= "t.at.supply.vss" "t.at.C3Els[0].vss"
|
||||||
|
= "t.at.supply.vss" "t.at.C2Els[7].vss"
|
||||||
|
= "t.at.supply.vss" "t.at.C2Els[6].vss"
|
||||||
|
= "t.at.supply.vss" "t.at.C2Els[5].vss"
|
||||||
|
= "t.at.supply.vss" "t.at.C2Els[4].vss"
|
||||||
|
= "t.at.supply.vss" "t.at.C2Els[3].vss"
|
||||||
|
= "t.at.supply.vss" "t.at.C2Els[2].vss"
|
||||||
|
= "t.at.supply.vss" "t.at.C2Els[1].vss"
|
||||||
|
= "t.at.supply.vss" "t.at.C2Els[0].vss"
|
||||||
|
= "t.at.in[0]" "t.at.C2Els[0].a"
|
||||||
|
= "t.at.in[0]" "t.at.tmp[0]"
|
||||||
|
= "t.at.in[1]" "t.at.C2Els[0].b"
|
||||||
|
= "t.at.in[1]" "t.at.tmp[1]"
|
||||||
|
= "t.at.in[2]" "t.at.C2Els[1].a"
|
||||||
|
= "t.at.in[2]" "t.at.tmp[2]"
|
||||||
|
= "t.at.in[3]" "t.at.C2Els[1].b"
|
||||||
|
= "t.at.in[3]" "t.at.tmp[3]"
|
||||||
|
= "t.at.in[4]" "t.at.C2Els[2].a"
|
||||||
|
= "t.at.in[4]" "t.at.tmp[4]"
|
||||||
|
= "t.at.in[5]" "t.at.C2Els[2].b"
|
||||||
|
= "t.at.in[5]" "t.at.tmp[5]"
|
||||||
|
= "t.at.in[6]" "t.at.C2Els[3].a"
|
||||||
|
= "t.at.in[6]" "t.at.tmp[6]"
|
||||||
|
= "t.at.in[7]" "t.at.C2Els[3].b"
|
||||||
|
= "t.at.in[7]" "t.at.tmp[7]"
|
||||||
|
= "t.at.in[8]" "t.at.C2Els[4].a"
|
||||||
|
= "t.at.in[8]" "t.at.tmp[8]"
|
||||||
|
= "t.at.in[9]" "t.at.C2Els[4].b"
|
||||||
|
= "t.at.in[9]" "t.at.tmp[9]"
|
||||||
|
= "t.at.in[10]" "t.at.C2Els[5].a"
|
||||||
|
= "t.at.in[10]" "t.at.tmp[10]"
|
||||||
|
= "t.at.in[11]" "t.at.C2Els[5].b"
|
||||||
|
= "t.at.in[11]" "t.at.tmp[11]"
|
||||||
|
= "t.at.in[12]" "t.at.C3Els[0].a"
|
||||||
|
= "t.at.in[12]" "t.at.tmp[12]"
|
||||||
|
= "t.at.in[13]" "t.at.C3Els[0].b"
|
||||||
|
= "t.at.in[13]" "t.at.tmp[13]"
|
||||||
|
= "t.at.in[14]" "t.at.C3Els[0].c"
|
||||||
|
= "t.at.in[14]" "t.at.tmp[14]"
|
||||||
|
= "t.at.out" "t.at.C3Els[2].y"
|
||||||
|
= "t.at.out" "t.at.tmp[25]"
|
||||||
|
= "Vdd" "t.at.supply.vdd"
|
||||||
|
= "GND" "t.at.supply.vss"
|
||||||
|
= "t.out" "t.at.out"
|
||||||
|
= "t.in[0]" "t.at.in[0]"
|
||||||
|
= "t.in[1]" "t.at.in[1]"
|
||||||
|
= "t.in[2]" "t.at.in[2]"
|
||||||
|
= "t.in[3]" "t.at.in[3]"
|
||||||
|
= "t.in[4]" "t.at.in[4]"
|
||||||
|
= "t.in[5]" "t.at.in[5]"
|
||||||
|
= "t.in[6]" "t.at.in[6]"
|
||||||
|
= "t.in[7]" "t.at.in[7]"
|
||||||
|
= "t.in[8]" "t.at.in[8]"
|
||||||
|
= "t.in[9]" "t.at.in[9]"
|
||||||
|
= "t.in[10]" "t.at.in[10]"
|
||||||
|
= "t.in[11]" "t.at.in[11]"
|
||||||
|
= "t.in[12]" "t.at.in[12]"
|
||||||
|
= "t.in[13]" "t.at.in[13]"
|
||||||
|
= "t.in[14]" "t.at.in[14]"
|
||||||
|
|
@ -0,0 +1,41 @@
|
||||||
|
/*************************************************************************
|
||||||
|
*
|
||||||
|
* This file is part of ACT dataflow neuro library.
|
||||||
|
* It's the testing facility for cell_lib_std.act
|
||||||
|
*
|
||||||
|
* Copyright (c) 2022 University of Groningen - Ole Richter
|
||||||
|
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
|
||||||
|
* Copyright (c) 2022 University of Groningen - Michele Mastella
|
||||||
|
* Copyright (c) 2022 University of Groningen - Madison Cotteret
|
||||||
|
*
|
||||||
|
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
|
||||||
|
*
|
||||||
|
* You may redistribute and modify this documentation and make products
|
||||||
|
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
|
||||||
|
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
|
||||||
|
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
|
||||||
|
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
|
||||||
|
* for applicable conditions.
|
||||||
|
*
|
||||||
|
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
|
||||||
|
*
|
||||||
|
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
|
||||||
|
* these sources, You must maintain the Source Location visible in its
|
||||||
|
* documentation.
|
||||||
|
*
|
||||||
|
**************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
import "../../dataflow_neuro/treegates.act";
|
||||||
|
import globals;
|
||||||
|
|
||||||
|
open tmpl::dataflow_neuro;
|
||||||
|
|
||||||
|
defproc andtree_15 (bool? in[15]; bool! out){
|
||||||
|
andtree<15> at(.in=in, .out=out);
|
||||||
|
at.supply.vss = GND;
|
||||||
|
at.supply.vdd = Vdd;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
andtree_15 t;
|
||||||
|
|
@ -0,0 +1,110 @@
|
||||||
|
watchall
|
||||||
|
|
||||||
|
system "echo '0'"
|
||||||
|
|
||||||
|
set t.in[0] 0
|
||||||
|
set t.in[1] 0
|
||||||
|
set t.in[2] 0
|
||||||
|
set t.in[3] 0
|
||||||
|
set t.in[4] 0
|
||||||
|
set t.in[5] 0
|
||||||
|
set t.in[6] 0
|
||||||
|
set t.in[7] 0
|
||||||
|
set t.in[8] 0
|
||||||
|
set t.in[9] 0
|
||||||
|
set t.in[10] 0
|
||||||
|
set t.in[11] 0
|
||||||
|
set t.in[12] 0
|
||||||
|
set t.in[13] 0
|
||||||
|
set t.in[14] 0
|
||||||
|
|
||||||
|
system "echo '1'"
|
||||||
|
|
||||||
|
cycle
|
||||||
|
mode run
|
||||||
|
|
||||||
|
assert t.out 0
|
||||||
|
|
||||||
|
system "echo '[] setting some bits high'"
|
||||||
|
set t.in[0] 1
|
||||||
|
set t.in[1] 1
|
||||||
|
set t.in[2] 1
|
||||||
|
set t.in[3] 1
|
||||||
|
set t.in[4] 1
|
||||||
|
set t.in[5] 1
|
||||||
|
set t.in[6] 1
|
||||||
|
set t.in[7] 1
|
||||||
|
set t.in[8] 1
|
||||||
|
set t.in[9] 1
|
||||||
|
set t.in[10] 1
|
||||||
|
set t.in[11] 1
|
||||||
|
set t.in[12] 0
|
||||||
|
set t.in[13] 0
|
||||||
|
set t.in[14] 0
|
||||||
|
|
||||||
|
cycle
|
||||||
|
|
||||||
|
assert t.out 0
|
||||||
|
|
||||||
|
system "echo '[] setting all bits high'"
|
||||||
|
set t.in[0] 1
|
||||||
|
set t.in[1] 1
|
||||||
|
set t.in[2] 1
|
||||||
|
set t.in[3] 1
|
||||||
|
set t.in[4] 1
|
||||||
|
set t.in[5] 1
|
||||||
|
set t.in[6] 1
|
||||||
|
set t.in[7] 1
|
||||||
|
set t.in[8] 1
|
||||||
|
set t.in[9] 1
|
||||||
|
set t.in[10] 1
|
||||||
|
set t.in[11] 1
|
||||||
|
set t.in[12] 1
|
||||||
|
set t.in[13] 1
|
||||||
|
set t.in[14] 1
|
||||||
|
|
||||||
|
cycle
|
||||||
|
assert t.out 1
|
||||||
|
|
||||||
|
|
||||||
|
system "echo '[] setting some low'"
|
||||||
|
set t.in[0] 1
|
||||||
|
set t.in[1] 1
|
||||||
|
set t.in[2] 1
|
||||||
|
set t.in[3] 1
|
||||||
|
set t.in[4] 1
|
||||||
|
set t.in[5] 1
|
||||||
|
set t.in[6] 1
|
||||||
|
set t.in[7] 1
|
||||||
|
set t.in[8] 1
|
||||||
|
set t.in[9] 1
|
||||||
|
set t.in[10] 0
|
||||||
|
set t.in[11] 1
|
||||||
|
set t.in[12] 1
|
||||||
|
set t.in[13] 1
|
||||||
|
set t.in[14] 1
|
||||||
|
|
||||||
|
cycle
|
||||||
|
assert t.out 0
|
||||||
|
|
||||||
|
|
||||||
|
system "echo '[] setting all low'"
|
||||||
|
set t.in[0] 0
|
||||||
|
set t.in[1] 0
|
||||||
|
set t.in[2] 0
|
||||||
|
set t.in[3] 0
|
||||||
|
set t.in[4] 0
|
||||||
|
set t.in[5] 0
|
||||||
|
set t.in[6] 0
|
||||||
|
set t.in[7] 0
|
||||||
|
set t.in[8] 0
|
||||||
|
set t.in[9] 0
|
||||||
|
set t.in[10] 0
|
||||||
|
set t.in[11] 0
|
||||||
|
set t.in[12] 0
|
||||||
|
set t.in[13] 0
|
||||||
|
set t.in[14] 0
|
||||||
|
|
||||||
|
cycle
|
||||||
|
assert t.out 0
|
||||||
|
|
||||||
|
|
@ -0,0 +1,40 @@
|
||||||
|
t.in[0] t.in[2] t.at.tmp[5] t.in[3] t.at.C2Els[0]._y t.in[4] t.at.C3Els[0]._y t.at.tmp[6] t.in[1] t.out t.at.C2Els[1]._y
|
||||||
|
0
|
||||||
|
1
|
||||||
|
0 t.in[0] : 0
|
||||||
|
0 t.in[4] : 0
|
||||||
|
0 t.in[2] : 0
|
||||||
|
0 t.in[1] : 0
|
||||||
|
0 t.in[3] : 0
|
||||||
|
1 t.at.C2Els[0]._y : 1 [by t.in[0]:=0]
|
||||||
|
7092 t.at.C3Els[0]._y : 1 [by t.in[4]:=0]
|
||||||
|
7094 t.at.tmp[6] : 0 [by t.at.C3Els[0]._y:=1]
|
||||||
|
10468 t.at.tmp[5] : 0 [by t.at.C2Els[0]._y:=1]
|
||||||
|
11847 t.at.C2Els[1]._y : 1 [by t.at.tmp[6]:=0]
|
||||||
|
12984 t.out : 0 [by t.at.C2Els[1]._y:=1]
|
||||||
|
[] setting some bits high
|
||||||
|
12984 t.in[0] : 1
|
||||||
|
12984 t.in[2] : 1
|
||||||
|
12984 t.in[1] : 1
|
||||||
|
13098 t.at.C2Els[0]._y : 0 [by t.in[1]:=1]
|
||||||
|
78464 t.at.tmp[5] : 1 [by t.at.C2Els[0]._y:=0]
|
||||||
|
[] setting all bits high
|
||||||
|
78464 t.in[3] : 1
|
||||||
|
78464 t.in[4] : 1
|
||||||
|
80190 t.at.C3Els[0]._y : 0 [by t.in[4]:=1]
|
||||||
|
80229 t.at.tmp[6] : 1 [by t.at.C3Els[0]._y:=0]
|
||||||
|
80244 t.at.C2Els[1]._y : 0 [by t.at.tmp[6]:=1]
|
||||||
|
80735 t.out : 1 [by t.at.C2Els[1]._y:=0]
|
||||||
|
[] setting some low
|
||||||
|
80735 t.in[0] : 0
|
||||||
|
80735 t.in[1] : 0
|
||||||
|
80748 t.at.C2Els[0]._y : 1 [by t.in[0]:=0]
|
||||||
|
80788 t.at.tmp[5] : 0 [by t.at.C2Els[0]._y:=1]
|
||||||
|
81203 t.at.C2Els[1]._y : 1 [by t.at.tmp[5]:=0]
|
||||||
|
81223 t.out : 0 [by t.at.C2Els[1]._y:=1]
|
||||||
|
[] setting all low
|
||||||
|
81223 t.in[2] : 0
|
||||||
|
81223 t.in[4] : 0
|
||||||
|
81223 t.in[3] : 0
|
||||||
|
87284 t.at.C3Els[0]._y : 1 [by t.in[2]:=0]
|
||||||
|
87331 t.at.tmp[6] : 0 [by t.at.C3Els[0]._y:=1]
|
||||||
Binary file not shown.
|
|
@ -0,0 +1,45 @@
|
||||||
|
= "GND" "GND"
|
||||||
|
= "Vdd" "Vdd"
|
||||||
|
= "Reset" "Reset"
|
||||||
|
"t.at.C2Els[0].a"&"t.at.C2Els[0].b"->"t.at.C2Els[0]._y"-
|
||||||
|
~("t.at.C2Els[0].a"&"t.at.C2Els[0].b")->"t.at.C2Els[0]._y"+
|
||||||
|
"t.at.C2Els[0]._y"->"t.at.C2Els[0].y"-
|
||||||
|
~("t.at.C2Els[0]._y")->"t.at.C2Els[0].y"+
|
||||||
|
"t.at.C2Els[1].a"&"t.at.C2Els[1].b"->"t.at.C2Els[1]._y"-
|
||||||
|
~("t.at.C2Els[1].a"&"t.at.C2Els[1].b")->"t.at.C2Els[1]._y"+
|
||||||
|
"t.at.C2Els[1]._y"->"t.at.C2Els[1].y"-
|
||||||
|
~("t.at.C2Els[1]._y")->"t.at.C2Els[1].y"+
|
||||||
|
"t.at.C3Els[0].a"&"t.at.C3Els[0].b"&"t.at.C3Els[0].c"->"t.at.C3Els[0]._y"-
|
||||||
|
~("t.at.C3Els[0].a"&"t.at.C3Els[0].b"&"t.at.C3Els[0].c")->"t.at.C3Els[0]._y"+
|
||||||
|
"t.at.C3Els[0]._y"->"t.at.C3Els[0].y"-
|
||||||
|
~("t.at.C3Els[0]._y")->"t.at.C3Els[0].y"+
|
||||||
|
= "t.at.tmp[5]" "t.at.C2Els[1].a"
|
||||||
|
= "t.at.tmp[5]" "t.at.C2Els[0].y"
|
||||||
|
= "t.at.tmp[6]" "t.at.C2Els[1].b"
|
||||||
|
= "t.at.tmp[6]" "t.at.C3Els[0].y"
|
||||||
|
= "t.at.supply.vdd" "t.at.C3Els[0].vdd"
|
||||||
|
= "t.at.supply.vdd" "t.at.C2Els[1].vdd"
|
||||||
|
= "t.at.supply.vdd" "t.at.C2Els[0].vdd"
|
||||||
|
= "t.at.supply.vss" "t.at.C3Els[0].vss"
|
||||||
|
= "t.at.supply.vss" "t.at.C2Els[1].vss"
|
||||||
|
= "t.at.supply.vss" "t.at.C2Els[0].vss"
|
||||||
|
= "t.at.in[0]" "t.at.C2Els[0].a"
|
||||||
|
= "t.at.in[0]" "t.at.tmp[0]"
|
||||||
|
= "t.at.in[1]" "t.at.C2Els[0].b"
|
||||||
|
= "t.at.in[1]" "t.at.tmp[1]"
|
||||||
|
= "t.at.in[2]" "t.at.C3Els[0].a"
|
||||||
|
= "t.at.in[2]" "t.at.tmp[2]"
|
||||||
|
= "t.at.in[3]" "t.at.C3Els[0].b"
|
||||||
|
= "t.at.in[3]" "t.at.tmp[3]"
|
||||||
|
= "t.at.in[4]" "t.at.C3Els[0].c"
|
||||||
|
= "t.at.in[4]" "t.at.tmp[4]"
|
||||||
|
= "t.at.out" "t.at.C2Els[1].y"
|
||||||
|
= "t.at.out" "t.at.tmp[7]"
|
||||||
|
= "Vdd" "t.at.supply.vdd"
|
||||||
|
= "GND" "t.at.supply.vss"
|
||||||
|
= "t.out" "t.at.out"
|
||||||
|
= "t.in[0]" "t.at.in[0]"
|
||||||
|
= "t.in[1]" "t.at.in[1]"
|
||||||
|
= "t.in[2]" "t.at.in[2]"
|
||||||
|
= "t.in[3]" "t.at.in[3]"
|
||||||
|
= "t.in[4]" "t.at.in[4]"
|
||||||
|
|
@ -0,0 +1,41 @@
|
||||||
|
/*************************************************************************
|
||||||
|
*
|
||||||
|
* This file is part of ACT dataflow neuro library.
|
||||||
|
* It's the testing facility for cell_lib_std.act
|
||||||
|
*
|
||||||
|
* Copyright (c) 2022 University of Groningen - Ole Richter
|
||||||
|
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
|
||||||
|
* Copyright (c) 2022 University of Groningen - Michele Mastella
|
||||||
|
* Copyright (c) 2022 University of Groningen - Madison Cotteret
|
||||||
|
*
|
||||||
|
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
|
||||||
|
*
|
||||||
|
* You may redistribute and modify this documentation and make products
|
||||||
|
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
|
||||||
|
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
|
||||||
|
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
|
||||||
|
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
|
||||||
|
* for applicable conditions.
|
||||||
|
*
|
||||||
|
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
|
||||||
|
*
|
||||||
|
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
|
||||||
|
* these sources, You must maintain the Source Location visible in its
|
||||||
|
* documentation.
|
||||||
|
*
|
||||||
|
**************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
import "../../dataflow_neuro/treegates.act";
|
||||||
|
import globals;
|
||||||
|
|
||||||
|
open tmpl::dataflow_neuro;
|
||||||
|
|
||||||
|
defproc andtree_5 (bool? in[5]; bool! out){
|
||||||
|
andtree<5> at(.in=in, .out=out);
|
||||||
|
at.supply.vss = GND;
|
||||||
|
at.supply.vdd = Vdd;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
andtree_5 t;
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
watchall
|
||||||
|
|
||||||
|
system "echo '0'"
|
||||||
|
|
||||||
|
set t.in[0] 0
|
||||||
|
set t.in[1] 0
|
||||||
|
set t.in[2] 0
|
||||||
|
set t.in[3] 0
|
||||||
|
set t.in[4] 0
|
||||||
|
|
||||||
|
system "echo '1'"
|
||||||
|
|
||||||
|
cycle
|
||||||
|
mode run
|
||||||
|
|
||||||
|
assert t.out 0
|
||||||
|
|
||||||
|
system "echo '[] setting some bits high'"
|
||||||
|
set t.in[0] 1
|
||||||
|
set t.in[1] 1
|
||||||
|
set t.in[2] 1
|
||||||
|
|
||||||
|
cycle
|
||||||
|
|
||||||
|
assert t.out 0
|
||||||
|
|
||||||
|
system "echo '[] setting all bits high'"
|
||||||
|
set t.in[3] 1
|
||||||
|
set t.in[4] 1
|
||||||
|
|
||||||
|
cycle
|
||||||
|
assert t.out 1
|
||||||
|
|
||||||
|
|
||||||
|
system "echo '[] setting some low'"
|
||||||
|
set t.in[0] 0
|
||||||
|
set t.in[1] 0
|
||||||
|
|
||||||
|
cycle
|
||||||
|
assert t.out 0
|
||||||
|
|
||||||
|
|
||||||
|
system "echo '[] setting all low'"
|
||||||
|
set t.in[2] 0
|
||||||
|
set t.in[3] 0
|
||||||
|
set t.in[4] 0
|
||||||
|
|
||||||
|
cycle
|
||||||
|
assert t.out 0
|
||||||
|
|
||||||
Loading…
Reference in New Issue