added and tree

This commit is contained in:
alexmadison 2022-03-01 12:22:36 +01:00
parent c947b28b03
commit fc4ccea3c0
11 changed files with 698 additions and 2 deletions

View File

@ -3,6 +3,9 @@
* This file is part of ACT dataflow neuro library * This file is part of ACT dataflow neuro library
* *
* Copyright (c) 2022 University of Groningen - Ole Richter * Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Madison Cotteret
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2021 Rajit Manohar * Copyright (c) 2021 Rajit Manohar
* *
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later * This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
@ -79,12 +82,121 @@ defproc ortree (bool? in[N]; bool! out; power supply)
/* array to hold the actual C-elments, either A2C or A3C */ /* array to hold the actual C-elments, either A2C or A3C */
[lenTree2Count > 0 -> [lenTree2Count > 0 ->
OR2_X1 C2Els[lenTree2Count]; OR2_X1 C2Els[lenTree2Count];
] ]
[lenTree3Count > 0 -> [lenTree3Count > 0 ->
OR3_X1 C3Els[lenTree3Count]; OR3_X1 C3Els[lenTree3Count];
]
(h:lenTree2Count:C2Els[h].vdd = supply.vdd;)
(h:lenTree3Count:C3Els[h].vdd = supply.vdd;)
(h:lenTree2Count:C2Els[h].vss = supply.vss;)
(h:lenTree3Count:C3Els[h].vss = supply.vss;)
/* Reset the variables we just stole lol */
i = 0;
end = N-1;
j = 0;
pint tree2Index = 0;
pint tree3Index = 0;
/* Invariant: i <= end */
*[ i != end ->
/*
* Invariant: tmp[i..end] has the current signals that need to be
* combined together, and "isinv" specifies if they are the inverted
* sense or not
*/
j = 0;
*[ i < end ->
/*-- there are still signals that need to be combined --*/
j = j + 1;
[ i+1 >= end ->
/*-- last piece: use either a 2 input C-element --*/
C2Els[tree2Index].a = tmp[i];
C2Els[tree2Index].b = tmp[i+1];
C2Els[tree2Index].y = tmp[end+j];
tree2Index = tree2Index +1;
i = end;
[] i+2 >= end ->
/*-- last piece: use either a 3 input C-element --*/
C3Els[tree3Index].a = tmp[i];
C3Els[tree3Index].b = tmp[i+1];
C3Els[tree3Index].c = tmp[i+2];
C3Els[tree3Index].y = tmp[end+j];
tree3Index = tree3Index +1;
i = end;
[] else ->
/*-- more to come; so use a two input C-element --*/
C2Els[tree2Index].a = tmp[i];
C2Els[tree2Index].b = tmp[i+1];
C2Els[tree2Index].y = tmp[end+j];
tree2Index = tree2Index +1;
i = i + 2;
]
]
/*-- update range that has to be combined --*/
i = end+1;
end = end+j;
j = 0;
]
out = tmp[end];
}
export template<pint N>
defproc andtree (bool? in[N]; bool! out; power supply)
{
bool tout;
{ N > 0 : "What?" };
pint i, end, j;
i = 0;
end = N-1;
pint lenTree2Count, lenTree3Count;
lenTree2Count = 0;
lenTree3Count = 0;
/* Pre"calculate" the number of C cells required, look below if confused */
*[ i != end ->
j = 0;
*[ i < end ->
j = j + 1;
[ i+1 >= end ->
i = end;
lenTree2Count = lenTree2Count +1;
[] i+2 >= end ->
i = end;
lenTree3Count = lenTree3Count +1;
[] else ->
i = i + 2;
lenTree2Count = lenTree2Count +1;
]
]
/*-- update range that has to be combined --*/
i = end+1;
end = end+j;
j = 0;
]
/* array that holds ALL the nodes in the completion tree */
bool tmp[end+1];
(k:N:tmp[k] = in[k];)
/* array to hold the actual C-elments, either A2C or A3C */
[lenTree2Count > 0 ->
AND2_X1 C2Els[lenTree2Count];
]
[lenTree3Count > 0 ->
AND3_X1 C3Els[lenTree3Count];
] ]
(h:lenTree2Count:C2Els[h].vdd = supply.vdd;) (h:lenTree2Count:C2Els[h].vdd = supply.vdd;)

View File

@ -0,0 +1,118 @@
t.in[0] t.at.tmp[22] t.in[5] t.in[2] t.at.tmp[15] t.in[3] t.at.tmp[23] t.at.C2Els[0]._y t.in[7] t.in[6] t.at.C2Els[3]._y t.in[4] t.at.C3Els[0]._y t.in[12] t.out t.at.tmp[21] t.at.C2Els[6]._y t.in[11] t.at.tmp[17] t.in[14] t.in[1] t.in[10] t.in[9] t.at.C2Els[5]._y t.at.tmp[19] t.at.tmp[20] t.at.tmp[24] t.in[13] t.at.tmp[16] t.at.C2Els[4]._y t.in[8] t.at.tmp[18] t.at.C2Els[2]._y t.at.C3Els[2]._y t.at.C2Els[1]._y t.at.C2Els[7]._y t.at.C3Els[1]._y
0
1
0 t.in[0] : 0
0 t.in[14] : 0
0 t.in[2] : 0
0 t.in[6] : 0
0 t.in[13] : 0
0 t.in[5] : 0
0 t.in[12] : 0
0 t.in[11] : 0
0 t.in[1] : 0
0 t.in[4] : 0
0 t.in[10] : 0
0 t.in[9] : 0
0 t.in[3] : 0
0 t.in[8] : 0
0 t.in[7] : 0
1 t.at.C2Els[0]._y : 1 [by t.in[0]:=0]
2 t.at.C2Els[3]._y : 1 [by t.in[6]:=0]
114 t.at.C2Els[4]._y : 1 [by t.in[9]:=0]
153 t.at.tmp[19] : 0 [by t.at.C2Els[4]._y:=1]
168 t.at.C3Els[1]._y : 1 [by t.at.tmp[19]:=0]
659 t.at.tmp[24] : 0 [by t.at.C3Els[1]._y:=1]
672 t.at.C3Els[2]._y : 1 [by t.at.tmp[24]:=0]
712 t.out : 0 [by t.at.C3Els[2]._y:=1]
1137 t.at.C2Els[5]._y : 1 [by t.in[11]:=0]
1552 t.at.tmp[20] : 0 [by t.at.C2Els[5]._y:=1]
1728 t.at.tmp[18] : 0 [by t.at.C2Els[3]._y:=1]
1748 t.at.C2Els[7]._y : 1 [by t.at.tmp[18]:=0]
4753 t.at.C2Els[2]._y : 1 [by t.in[5]:=0]
4800 t.at.tmp[17] : 0 [by t.at.C2Els[2]._y:=1]
7092 t.at.C3Els[0]._y : 1 [by t.in[14]:=0]
7108 t.at.tmp[21] : 0 [by t.at.C3Els[0]._y:=1]
7809 t.at.tmp[23] : 0 [by t.at.C2Els[7]._y:=1]
10467 t.at.C2Els[1]._y : 1 [by t.in[2]:=0]
54565 t.at.tmp[16] : 0 [by t.at.C2Els[1]._y:=1]
65367 t.at.tmp[15] : 0 [by t.at.C2Els[0]._y:=1]
68289 t.at.C2Els[6]._y : 1 [by t.at.tmp[16]:=0]
68293 t.at.tmp[22] : 0 [by t.at.C2Els[6]._y:=1]
[] setting some bits high
68293 t.in[0] : 1
68293 t.in[11] : 1
68293 t.in[10] : 1
68293 t.in[9] : 1
68293 t.in[2] : 1
68293 t.in[8] : 1
68293 t.in[7] : 1
68293 t.in[6] : 1
68293 t.in[5] : 1
68293 t.in[1] : 1
68293 t.in[4] : 1
68293 t.in[3] : 1
68308 t.at.C2Els[4]._y : 0 [by t.in[8]:=1]
68348 t.at.C2Els[2]._y : 0 [by t.in[4]:=1]
77422 t.at.C2Els[5]._y : 0 [by t.in[10]:=1]
82197 t.at.tmp[17] : 1 [by t.at.C2Els[2]._y:=0]
98088 t.at.tmp[19] : 1 [by t.at.C2Els[4]._y:=0]
102234 t.at.tmp[20] : 1 [by t.at.C2Els[5]._y:=0]
105224 t.at.C2Els[0]._y : 0 [by t.in[1]:=1]
111541 t.at.C2Els[3]._y : 0 [by t.in[6]:=1]
111963 t.at.tmp[18] : 1 [by t.at.C2Els[3]._y:=0]
119567 t.at.tmp[15] : 1 [by t.at.C2Els[0]._y:=0]
119946 t.at.C2Els[1]._y : 0 [by t.in[3]:=1]
119947 t.at.tmp[16] : 1 [by t.at.C2Els[1]._y:=0]
119948 t.at.C2Els[6]._y : 0 [by t.at.tmp[16]:=1]
140153 t.at.tmp[22] : 1 [by t.at.C2Els[6]._y:=0]
160677 t.at.C2Els[7]._y : 0 [by t.at.tmp[18]:=1]
160959 t.at.tmp[23] : 1 [by t.at.C2Els[7]._y:=0]
[] setting all bits high
160959 t.in[12] : 1
160959 t.in[14] : 1
160959 t.in[13] : 1
161727 t.at.C3Els[0]._y : 0 [by t.in[13]:=1]
161730 t.at.tmp[21] : 1 [by t.at.C3Els[0]._y:=0]
184171 t.at.C3Els[1]._y : 0 [by t.at.tmp[21]:=1]
184722 t.at.tmp[24] : 1 [by t.at.C3Els[1]._y:=0]
185793 t.at.C3Els[2]._y : 0 [by t.at.tmp[24]:=1]
186747 t.out : 1 [by t.at.C3Els[2]._y:=0]
[] setting some low
186747 t.in[10] : 0
187828 t.at.C2Els[5]._y : 1 [by t.in[10]:=0]
242298 t.at.tmp[20] : 0 [by t.at.C2Els[5]._y:=1]
243280 t.at.C3Els[1]._y : 1 [by t.at.tmp[20]:=0]
243298 t.at.tmp[24] : 0 [by t.at.C3Els[1]._y:=1]
247311 t.at.C3Els[2]._y : 1 [by t.at.tmp[24]:=0]
251314 t.out : 0 [by t.at.C3Els[2]._y:=1]
[] setting all low
251314 t.in[0] : 0
251314 t.in[14] : 0
251314 t.in[2] : 0
251314 t.in[6] : 0
251314 t.in[5] : 0
251314 t.in[13] : 0
251314 t.in[12] : 0
251314 t.in[1] : 0
251314 t.in[4] : 0
251314 t.in[11] : 0
251314 t.in[9] : 0
251314 t.in[3] : 0
251314 t.in[8] : 0
251314 t.in[7] : 0
251517 t.at.C2Els[2]._y : 1 [by t.in[5]:=0]
251656 t.at.tmp[17] : 0 [by t.at.C2Els[2]._y:=1]
251816 t.at.C2Els[3]._y : 1 [by t.in[6]:=0]
251885 t.at.tmp[18] : 0 [by t.at.C2Els[3]._y:=1]
253168 t.at.C2Els[4]._y : 1 [by t.in[9]:=0]
253179 t.at.tmp[19] : 0 [by t.at.C2Els[4]._y:=1]
256074 t.at.C2Els[1]._y : 1 [by t.in[2]:=0]
272898 t.at.C3Els[0]._y : 1 [by t.in[14]:=0]
273102 t.at.tmp[21] : 0 [by t.at.C3Els[0]._y:=1]
288002 t.at.C2Els[7]._y : 1 [by t.at.tmp[17]:=0]
288017 t.at.tmp[23] : 0 [by t.at.C2Els[7]._y:=1]
296215 t.at.C2Els[0]._y : 1 [by t.in[0]:=0]
296216 t.at.tmp[15] : 0 [by t.at.C2Els[0]._y:=1]
296253 t.at.C2Els[6]._y : 1 [by t.at.tmp[15]:=0]
296992 t.at.tmp[22] : 0 [by t.at.C2Els[6]._y:=1]
307860 t.at.tmp[16] : 0 [by t.at.C2Els[1]._y:=1]

Binary file not shown.

View File

@ -0,0 +1,139 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"t.at.C2Els[0].a"&"t.at.C2Els[0].b"->"t.at.C2Els[0]._y"-
~("t.at.C2Els[0].a"&"t.at.C2Els[0].b")->"t.at.C2Els[0]._y"+
"t.at.C2Els[0]._y"->"t.at.C2Els[0].y"-
~("t.at.C2Els[0]._y")->"t.at.C2Els[0].y"+
"t.at.C2Els[1].a"&"t.at.C2Els[1].b"->"t.at.C2Els[1]._y"-
~("t.at.C2Els[1].a"&"t.at.C2Els[1].b")->"t.at.C2Els[1]._y"+
"t.at.C2Els[1]._y"->"t.at.C2Els[1].y"-
~("t.at.C2Els[1]._y")->"t.at.C2Els[1].y"+
"t.at.C2Els[2].a"&"t.at.C2Els[2].b"->"t.at.C2Els[2]._y"-
~("t.at.C2Els[2].a"&"t.at.C2Els[2].b")->"t.at.C2Els[2]._y"+
"t.at.C2Els[2]._y"->"t.at.C2Els[2].y"-
~("t.at.C2Els[2]._y")->"t.at.C2Els[2].y"+
"t.at.C2Els[3].a"&"t.at.C2Els[3].b"->"t.at.C2Els[3]._y"-
~("t.at.C2Els[3].a"&"t.at.C2Els[3].b")->"t.at.C2Els[3]._y"+
"t.at.C2Els[3]._y"->"t.at.C2Els[3].y"-
~("t.at.C2Els[3]._y")->"t.at.C2Els[3].y"+
"t.at.C2Els[4].a"&"t.at.C2Els[4].b"->"t.at.C2Els[4]._y"-
~("t.at.C2Els[4].a"&"t.at.C2Els[4].b")->"t.at.C2Els[4]._y"+
"t.at.C2Els[4]._y"->"t.at.C2Els[4].y"-
~("t.at.C2Els[4]._y")->"t.at.C2Els[4].y"+
"t.at.C2Els[5].a"&"t.at.C2Els[5].b"->"t.at.C2Els[5]._y"-
~("t.at.C2Els[5].a"&"t.at.C2Els[5].b")->"t.at.C2Els[5]._y"+
"t.at.C2Els[5]._y"->"t.at.C2Els[5].y"-
~("t.at.C2Els[5]._y")->"t.at.C2Els[5].y"+
"t.at.C2Els[6].a"&"t.at.C2Els[6].b"->"t.at.C2Els[6]._y"-
~("t.at.C2Els[6].a"&"t.at.C2Els[6].b")->"t.at.C2Els[6]._y"+
"t.at.C2Els[6]._y"->"t.at.C2Els[6].y"-
~("t.at.C2Els[6]._y")->"t.at.C2Els[6].y"+
"t.at.C2Els[7].a"&"t.at.C2Els[7].b"->"t.at.C2Els[7]._y"-
~("t.at.C2Els[7].a"&"t.at.C2Els[7].b")->"t.at.C2Els[7]._y"+
"t.at.C2Els[7]._y"->"t.at.C2Els[7].y"-
~("t.at.C2Els[7]._y")->"t.at.C2Els[7].y"+
"t.at.C3Els[0].a"&"t.at.C3Els[0].b"&"t.at.C3Els[0].c"->"t.at.C3Els[0]._y"-
~("t.at.C3Els[0].a"&"t.at.C3Els[0].b"&"t.at.C3Els[0].c")->"t.at.C3Els[0]._y"+
"t.at.C3Els[0]._y"->"t.at.C3Els[0].y"-
~("t.at.C3Els[0]._y")->"t.at.C3Els[0].y"+
"t.at.C3Els[1].a"&"t.at.C3Els[1].b"&"t.at.C3Els[1].c"->"t.at.C3Els[1]._y"-
~("t.at.C3Els[1].a"&"t.at.C3Els[1].b"&"t.at.C3Els[1].c")->"t.at.C3Els[1]._y"+
"t.at.C3Els[1]._y"->"t.at.C3Els[1].y"-
~("t.at.C3Els[1]._y")->"t.at.C3Els[1].y"+
"t.at.C3Els[2].a"&"t.at.C3Els[2].b"&"t.at.C3Els[2].c"->"t.at.C3Els[2]._y"-
~("t.at.C3Els[2].a"&"t.at.C3Els[2].b"&"t.at.C3Els[2].c")->"t.at.C3Els[2]._y"+
"t.at.C3Els[2]._y"->"t.at.C3Els[2].y"-
~("t.at.C3Els[2]._y")->"t.at.C3Els[2].y"+
= "t.at.tmp[15]" "t.at.C2Els[6].a"
= "t.at.tmp[15]" "t.at.C2Els[0].y"
= "t.at.tmp[16]" "t.at.C2Els[6].b"
= "t.at.tmp[16]" "t.at.C2Els[1].y"
= "t.at.tmp[17]" "t.at.C2Els[7].a"
= "t.at.tmp[17]" "t.at.C2Els[2].y"
= "t.at.tmp[18]" "t.at.C2Els[7].b"
= "t.at.tmp[18]" "t.at.C2Els[3].y"
= "t.at.tmp[19]" "t.at.C3Els[1].a"
= "t.at.tmp[19]" "t.at.C2Els[4].y"
= "t.at.tmp[20]" "t.at.C3Els[1].b"
= "t.at.tmp[20]" "t.at.C2Els[5].y"
= "t.at.tmp[21]" "t.at.C3Els[1].c"
= "t.at.tmp[21]" "t.at.C3Els[0].y"
= "t.at.tmp[22]" "t.at.C3Els[2].a"
= "t.at.tmp[22]" "t.at.C2Els[6].y"
= "t.at.tmp[23]" "t.at.C3Els[2].b"
= "t.at.tmp[23]" "t.at.C2Els[7].y"
= "t.at.tmp[24]" "t.at.C3Els[2].c"
= "t.at.tmp[24]" "t.at.C3Els[1].y"
= "t.at.supply.vdd" "t.at.C3Els[2].vdd"
= "t.at.supply.vdd" "t.at.C3Els[1].vdd"
= "t.at.supply.vdd" "t.at.C3Els[0].vdd"
= "t.at.supply.vdd" "t.at.C2Els[7].vdd"
= "t.at.supply.vdd" "t.at.C2Els[6].vdd"
= "t.at.supply.vdd" "t.at.C2Els[5].vdd"
= "t.at.supply.vdd" "t.at.C2Els[4].vdd"
= "t.at.supply.vdd" "t.at.C2Els[3].vdd"
= "t.at.supply.vdd" "t.at.C2Els[2].vdd"
= "t.at.supply.vdd" "t.at.C2Els[1].vdd"
= "t.at.supply.vdd" "t.at.C2Els[0].vdd"
= "t.at.supply.vss" "t.at.C3Els[2].vss"
= "t.at.supply.vss" "t.at.C3Els[1].vss"
= "t.at.supply.vss" "t.at.C3Els[0].vss"
= "t.at.supply.vss" "t.at.C2Els[7].vss"
= "t.at.supply.vss" "t.at.C2Els[6].vss"
= "t.at.supply.vss" "t.at.C2Els[5].vss"
= "t.at.supply.vss" "t.at.C2Els[4].vss"
= "t.at.supply.vss" "t.at.C2Els[3].vss"
= "t.at.supply.vss" "t.at.C2Els[2].vss"
= "t.at.supply.vss" "t.at.C2Els[1].vss"
= "t.at.supply.vss" "t.at.C2Els[0].vss"
= "t.at.in[0]" "t.at.C2Els[0].a"
= "t.at.in[0]" "t.at.tmp[0]"
= "t.at.in[1]" "t.at.C2Els[0].b"
= "t.at.in[1]" "t.at.tmp[1]"
= "t.at.in[2]" "t.at.C2Els[1].a"
= "t.at.in[2]" "t.at.tmp[2]"
= "t.at.in[3]" "t.at.C2Els[1].b"
= "t.at.in[3]" "t.at.tmp[3]"
= "t.at.in[4]" "t.at.C2Els[2].a"
= "t.at.in[4]" "t.at.tmp[4]"
= "t.at.in[5]" "t.at.C2Els[2].b"
= "t.at.in[5]" "t.at.tmp[5]"
= "t.at.in[6]" "t.at.C2Els[3].a"
= "t.at.in[6]" "t.at.tmp[6]"
= "t.at.in[7]" "t.at.C2Els[3].b"
= "t.at.in[7]" "t.at.tmp[7]"
= "t.at.in[8]" "t.at.C2Els[4].a"
= "t.at.in[8]" "t.at.tmp[8]"
= "t.at.in[9]" "t.at.C2Els[4].b"
= "t.at.in[9]" "t.at.tmp[9]"
= "t.at.in[10]" "t.at.C2Els[5].a"
= "t.at.in[10]" "t.at.tmp[10]"
= "t.at.in[11]" "t.at.C2Els[5].b"
= "t.at.in[11]" "t.at.tmp[11]"
= "t.at.in[12]" "t.at.C3Els[0].a"
= "t.at.in[12]" "t.at.tmp[12]"
= "t.at.in[13]" "t.at.C3Els[0].b"
= "t.at.in[13]" "t.at.tmp[13]"
= "t.at.in[14]" "t.at.C3Els[0].c"
= "t.at.in[14]" "t.at.tmp[14]"
= "t.at.out" "t.at.C3Els[2].y"
= "t.at.out" "t.at.tmp[25]"
= "Vdd" "t.at.supply.vdd"
= "GND" "t.at.supply.vss"
= "t.out" "t.at.out"
= "t.in[0]" "t.at.in[0]"
= "t.in[1]" "t.at.in[1]"
= "t.in[2]" "t.at.in[2]"
= "t.in[3]" "t.at.in[3]"
= "t.in[4]" "t.at.in[4]"
= "t.in[5]" "t.at.in[5]"
= "t.in[6]" "t.at.in[6]"
= "t.in[7]" "t.at.in[7]"
= "t.in[8]" "t.at.in[8]"
= "t.in[9]" "t.at.in[9]"
= "t.in[10]" "t.at.in[10]"
= "t.in[11]" "t.at.in[11]"
= "t.in[12]" "t.at.in[12]"
= "t.in[13]" "t.at.in[13]"
= "t.in[14]" "t.at.in[14]"

View File

@ -0,0 +1,41 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/treegates.act";
import globals;
open tmpl::dataflow_neuro;
defproc andtree_15 (bool? in[15]; bool! out){
andtree<15> at(.in=in, .out=out);
at.supply.vss = GND;
at.supply.vdd = Vdd;
}
andtree_15 t;

View File

@ -0,0 +1,110 @@
watchall
system "echo '0'"
set t.in[0] 0
set t.in[1] 0
set t.in[2] 0
set t.in[3] 0
set t.in[4] 0
set t.in[5] 0
set t.in[6] 0
set t.in[7] 0
set t.in[8] 0
set t.in[9] 0
set t.in[10] 0
set t.in[11] 0
set t.in[12] 0
set t.in[13] 0
set t.in[14] 0
system "echo '1'"
cycle
mode run
assert t.out 0
system "echo '[] setting some bits high'"
set t.in[0] 1
set t.in[1] 1
set t.in[2] 1
set t.in[3] 1
set t.in[4] 1
set t.in[5] 1
set t.in[6] 1
set t.in[7] 1
set t.in[8] 1
set t.in[9] 1
set t.in[10] 1
set t.in[11] 1
set t.in[12] 0
set t.in[13] 0
set t.in[14] 0
cycle
assert t.out 0
system "echo '[] setting all bits high'"
set t.in[0] 1
set t.in[1] 1
set t.in[2] 1
set t.in[3] 1
set t.in[4] 1
set t.in[5] 1
set t.in[6] 1
set t.in[7] 1
set t.in[8] 1
set t.in[9] 1
set t.in[10] 1
set t.in[11] 1
set t.in[12] 1
set t.in[13] 1
set t.in[14] 1
cycle
assert t.out 1
system "echo '[] setting some low'"
set t.in[0] 1
set t.in[1] 1
set t.in[2] 1
set t.in[3] 1
set t.in[4] 1
set t.in[5] 1
set t.in[6] 1
set t.in[7] 1
set t.in[8] 1
set t.in[9] 1
set t.in[10] 0
set t.in[11] 1
set t.in[12] 1
set t.in[13] 1
set t.in[14] 1
cycle
assert t.out 0
system "echo '[] setting all low'"
set t.in[0] 0
set t.in[1] 0
set t.in[2] 0
set t.in[3] 0
set t.in[4] 0
set t.in[5] 0
set t.in[6] 0
set t.in[7] 0
set t.in[8] 0
set t.in[9] 0
set t.in[10] 0
set t.in[11] 0
set t.in[12] 0
set t.in[13] 0
set t.in[14] 0
cycle
assert t.out 0

View File

@ -0,0 +1,40 @@
t.in[0] t.in[2] t.at.tmp[5] t.in[3] t.at.C2Els[0]._y t.in[4] t.at.C3Els[0]._y t.at.tmp[6] t.in[1] t.out t.at.C2Els[1]._y
0
1
0 t.in[0] : 0
0 t.in[4] : 0
0 t.in[2] : 0
0 t.in[1] : 0
0 t.in[3] : 0
1 t.at.C2Els[0]._y : 1 [by t.in[0]:=0]
7092 t.at.C3Els[0]._y : 1 [by t.in[4]:=0]
7094 t.at.tmp[6] : 0 [by t.at.C3Els[0]._y:=1]
10468 t.at.tmp[5] : 0 [by t.at.C2Els[0]._y:=1]
11847 t.at.C2Els[1]._y : 1 [by t.at.tmp[6]:=0]
12984 t.out : 0 [by t.at.C2Els[1]._y:=1]
[] setting some bits high
12984 t.in[0] : 1
12984 t.in[2] : 1
12984 t.in[1] : 1
13098 t.at.C2Els[0]._y : 0 [by t.in[1]:=1]
78464 t.at.tmp[5] : 1 [by t.at.C2Els[0]._y:=0]
[] setting all bits high
78464 t.in[3] : 1
78464 t.in[4] : 1
80190 t.at.C3Els[0]._y : 0 [by t.in[4]:=1]
80229 t.at.tmp[6] : 1 [by t.at.C3Els[0]._y:=0]
80244 t.at.C2Els[1]._y : 0 [by t.at.tmp[6]:=1]
80735 t.out : 1 [by t.at.C2Els[1]._y:=0]
[] setting some low
80735 t.in[0] : 0
80735 t.in[1] : 0
80748 t.at.C2Els[0]._y : 1 [by t.in[0]:=0]
80788 t.at.tmp[5] : 0 [by t.at.C2Els[0]._y:=1]
81203 t.at.C2Els[1]._y : 1 [by t.at.tmp[5]:=0]
81223 t.out : 0 [by t.at.C2Els[1]._y:=1]
[] setting all low
81223 t.in[2] : 0
81223 t.in[4] : 0
81223 t.in[3] : 0
87284 t.at.C3Els[0]._y : 1 [by t.in[2]:=0]
87331 t.at.tmp[6] : 0 [by t.at.C3Els[0]._y:=1]

Binary file not shown.

View File

@ -0,0 +1,45 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"t.at.C2Els[0].a"&"t.at.C2Els[0].b"->"t.at.C2Els[0]._y"-
~("t.at.C2Els[0].a"&"t.at.C2Els[0].b")->"t.at.C2Els[0]._y"+
"t.at.C2Els[0]._y"->"t.at.C2Els[0].y"-
~("t.at.C2Els[0]._y")->"t.at.C2Els[0].y"+
"t.at.C2Els[1].a"&"t.at.C2Els[1].b"->"t.at.C2Els[1]._y"-
~("t.at.C2Els[1].a"&"t.at.C2Els[1].b")->"t.at.C2Els[1]._y"+
"t.at.C2Els[1]._y"->"t.at.C2Els[1].y"-
~("t.at.C2Els[1]._y")->"t.at.C2Els[1].y"+
"t.at.C3Els[0].a"&"t.at.C3Els[0].b"&"t.at.C3Els[0].c"->"t.at.C3Els[0]._y"-
~("t.at.C3Els[0].a"&"t.at.C3Els[0].b"&"t.at.C3Els[0].c")->"t.at.C3Els[0]._y"+
"t.at.C3Els[0]._y"->"t.at.C3Els[0].y"-
~("t.at.C3Els[0]._y")->"t.at.C3Els[0].y"+
= "t.at.tmp[5]" "t.at.C2Els[1].a"
= "t.at.tmp[5]" "t.at.C2Els[0].y"
= "t.at.tmp[6]" "t.at.C2Els[1].b"
= "t.at.tmp[6]" "t.at.C3Els[0].y"
= "t.at.supply.vdd" "t.at.C3Els[0].vdd"
= "t.at.supply.vdd" "t.at.C2Els[1].vdd"
= "t.at.supply.vdd" "t.at.C2Els[0].vdd"
= "t.at.supply.vss" "t.at.C3Els[0].vss"
= "t.at.supply.vss" "t.at.C2Els[1].vss"
= "t.at.supply.vss" "t.at.C2Els[0].vss"
= "t.at.in[0]" "t.at.C2Els[0].a"
= "t.at.in[0]" "t.at.tmp[0]"
= "t.at.in[1]" "t.at.C2Els[0].b"
= "t.at.in[1]" "t.at.tmp[1]"
= "t.at.in[2]" "t.at.C3Els[0].a"
= "t.at.in[2]" "t.at.tmp[2]"
= "t.at.in[3]" "t.at.C3Els[0].b"
= "t.at.in[3]" "t.at.tmp[3]"
= "t.at.in[4]" "t.at.C3Els[0].c"
= "t.at.in[4]" "t.at.tmp[4]"
= "t.at.out" "t.at.C2Els[1].y"
= "t.at.out" "t.at.tmp[7]"
= "Vdd" "t.at.supply.vdd"
= "GND" "t.at.supply.vss"
= "t.out" "t.at.out"
= "t.in[0]" "t.at.in[0]"
= "t.in[1]" "t.at.in[1]"
= "t.in[2]" "t.at.in[2]"
= "t.in[3]" "t.at.in[3]"
= "t.in[4]" "t.at.in[4]"

View File

@ -0,0 +1,41 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/treegates.act";
import globals;
open tmpl::dataflow_neuro;
defproc andtree_5 (bool? in[5]; bool! out){
andtree<5> at(.in=in, .out=out);
at.supply.vss = GND;
at.supply.vdd = Vdd;
}
andtree_5 t;

View File

@ -0,0 +1,50 @@
watchall
system "echo '0'"
set t.in[0] 0
set t.in[1] 0
set t.in[2] 0
set t.in[3] 0
set t.in[4] 0
system "echo '1'"
cycle
mode run
assert t.out 0
system "echo '[] setting some bits high'"
set t.in[0] 1
set t.in[1] 1
set t.in[2] 1
cycle
assert t.out 0
system "echo '[] setting all bits high'"
set t.in[3] 1
set t.in[4] 1
cycle
assert t.out 1
system "echo '[] setting some low'"
set t.in[0] 0
set t.in[1] 0
cycle
assert t.out 0
system "echo '[] setting all low'"
set t.in[2] 0
set t.in[3] 0
set t.in[4] 0
cycle
assert t.out 0