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Author SHA1 Message Date
Ole Richter 48b691d7d4 added license, moved cell libs into repo 
added buffer (not tested),
 2022-02-21 00:33:58 +01:00
3 changed files with 256 additions and 251 deletions
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2
Makefile
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@ -21,7 +21,7 @@
TARGETACT=LICENSE TARGETACT=LICENSE
# template because its a template based appoach no syntesis so it would be wrong in syn # template because its a template based appoach no syntesis so it would be wrong in syn
TARGETACTSUBDIR=template/dataflow TARGETACTSUBDIR=template/dataflow_neuro
SUBDIRS=dataflow_neuro SUBDIRS=dataflow_neuro

14
README.md
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@ -1,10 +1,14 @@
# The classical dataflow template library for mixed signal neuromoric processors # A dataflow template library for mixed signal neuromoric processors
the library will be installed in `$ACT_HOME/act/template/dataflow_neuro`.
This path is part of the default search path for any ACT tool.
the library will be installed in `$ACT_HOME/act/template/dataflow`. This path is part of the default search path for any ACT tool. this library depends on stdlib (https://github.com/asyncvlsi/stdlib)
this library depends on stdlib
## Installation ## Installation
Set `$ACT_HOME` to the root of your ACT installation, and then run `make install` Set `$ACT_HOME` to the root of your ACT installation, and then run `make install`.
## Unit tests
After installation, you can run `make runtest` to execute the unit tests

183
dataflow_neuro/cell_lib_std.act
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@ -24,47 +24,46 @@
************************************************************************** **************************************************************************
*/ */
namespace dataflow { namespace template {
namespace dataflow_neuro {
export defproc TIELO_X1(bool! y; bool? vdd, vss) export defproc TIELO_X1(bool! y; bool? vdd, vss)
{ {
y = vss; y = vss;
} }
export defproc TIEHI_X1(bool! y; bool? vdd, vss) export defproc TIEHI_X1(bool! y; bool? vdd, vss)
{ {
y = vdd; y = vdd;
} }
/*-- inverters --*/ /*-- inverters --*/
defproc inv (bool! y; bool? a, vdd, vss) defproc inv (bool! y; bool? a, vdd, vss)
{ {
prs { prs {
a => y- a => y-
} }
} }
template<pint nf>
defproc szinv <: inv()
template<pint nf> {
defproc szinv <: inv()
{
[nf = 0 -> sizing { y {-1} } [nf = 0 -> sizing { y {-1} }
[] else -> sizing { y {-2*nf,svt,nf} } [] else -> sizing { y {-2*nf,svt,nf} }
] ]
} }
export defcell INV_X1<: szinv<0>() { } export defcell INV_X1<: szinv<0>() { }
export defcell INV_X2<: szinv<1>() { } export defcell INV_X2<: szinv<1>() { }
export defcell INV_X4<: szinv<2>() { } export defcell INV_X4<: szinv<2>() { }
export defcell INV_X8<: szinv<4>() { } export defcell INV_X8<: szinv<4>() { }
/*-- clock delay buffers --*/ /*-- clock delay buffers --*/
template<pint N> template<pint N>
defproc dbuf (bool! y; bool? a, vdd, vss) defproc dbuf (bool! y; bool? a, vdd, vss)
{ {
{N > 0 : "Delay buffer needs at least one stage!"}; {N > 0 : "Delay buffer needs at least one stage!"};
bool sig[2*N+1]; bool sig[2*N+1];
sig[0] = a; sig[0] = a;
@ -74,111 +73,111 @@ defproc dbuf (bool! y; bool? a, vdd, vss)
sig[i] <40;2> -> sig[i+1]- sig[i] <40;2> -> sig[i+1]-
) )
} }
} }
export defproc CLKBUF1 <: dbuf<2>() { } export defproc CLKBUF1 <: dbuf<2>() { }
export defproc CLKBUF2 <: dbuf<3>() { } export defproc CLKBUF2 <: dbuf<3>() { }
export defproc CLKBUF3 <: dbuf<4>() { } export defproc CLKBUF3 <: dbuf<4>() { }
/*-- signal buffers --*/ /*-- signal buffers --*/
defproc buf (bool! y; bool? a, vdd, vss) defproc buf (bool! y; bool? a, vdd, vss)
{ {
bool _y; bool _y;
prs { prs {
a => _y- a => _y-
_y => y- _y => y-
} }
} }
export defcell BUF_X2<: buf() export defcell BUF_X2<: buf()
{ {
sizing { _y {-1}; y {-2} } sizing { _y {-1}; y {-2} }
} }
export defcell BUF_X4<: buf() export defcell BUF_X4<: buf()
{ {
sizing { _y {-1.5}; y {-4,2} } sizing { _y {-1.5}; y {-4,2} }
} }
/*-- simple gates --*/ /*-- simple gates --*/
export defcell NOR2_X1(bool! y; bool? a, b, vdd, vss) export defcell NOR2_X1(bool! y; bool? a, b, vdd, vss)
{ {
prs { prs {
a | b => y- a | b => y-
} }
sizing { y {-1} } sizing { y {-1} }
} }
export defcell NOR3_X1(bool! y; bool? a, b, c, vdd, vss) export defcell NOR3_X1(bool! y; bool? a, b, c, vdd, vss)
{ {
prs { prs {
a | b | c => y- a | b | c => y-
} }
sizing { y {-1} } sizing { y {-1} }
} }
export defcell OR2_X1(bool! y; bool? a, b, vdd, vss) export defcell OR2_X1(bool! y; bool? a, b, vdd, vss)
{ {
bool _y; bool _y;
prs { prs {
a | b => _y- a | b => _y-
_y => y- _y => y-
} }
sizing { _y{-1}; y{-1} } sizing { _y{-1}; y{-1} }
} }
export defcell OR2_X2(bool! y; bool? a, b, vdd, vss) export defcell OR2_X2(bool! y; bool? a, b, vdd, vss)
{ {
bool _y; bool _y;
prs { prs {
a | b => _y- a | b => _y-
_y => y- _y => y-
} }
sizing { _y{-1}; y{-2} } sizing { _y{-1}; y{-2} }
} }
export defcell NAND2_X1(bool! y; bool? a, b, vdd, vss) export defcell NAND2_X1(bool! y; bool? a, b, vdd, vss)
{ {
prs { prs {
a & b => y- a & b => y-
} }
sizing { y{-1} } sizing { y{-1} }
} }
export defcell NAND3_X1(bool! y; bool? a, b, c, vdd, vss) export defcell NAND3_X1(bool! y; bool? a, b, c, vdd, vss)
{ {
prs { prs {
a & b & c => y- a & b & c => y-
} }
sizing { y{-1} } sizing { y{-1} }
} }
export defcell AND2_X1(bool! y; bool? a, b, vdd, vss) export defcell AND2_X1(bool! y; bool? a, b, vdd, vss)
{ {
bool _y; bool _y;
prs { prs {
a & b => _y- a & b => _y-
_y => y- _y => y-
} }
sizing { _y{-1}; y{-1} } sizing { _y{-1}; y{-1} }
} }
export defcell AND2_X2(bool! y; bool? a, b, vdd, vss) export defcell AND2_X2(bool! y; bool? a, b, vdd, vss)
{ {
bool _y; bool _y;
prs { prs {
a & b => _y- a & b => _y-
_y => y- _y => y-
} }
sizing { _y{-1}; y{-2} } sizing { _y{-1}; y{-2} }
} }
export defcell XOR2_X1(bool! y; bool? a, b, vdd, vss) export defcell XOR2_X1(bool! y; bool? a, b, vdd, vss)
{ {
bool _a, _b; bool _a, _b;
prs { prs {
a => _a- a => _a-
@ -188,10 +187,10 @@ export defcell XOR2_X1(bool! y; bool? a, b, vdd, vss)
_b & _a | b & a -> y- _b & _a | b & a -> y-
} }
sizing { _a{-1}; _b{-1}; y{-1} } sizing { _a{-1}; _b{-1}; y{-1} }
} }
export defcell XNOR2_X1(bool! y; bool? a, b, vdd, vss) export defcell XNOR2_X1(bool! y; bool? a, b, vdd, vss)
{ {
bool _a, _b; bool _a, _b;
prs { prs {
a => _a- a => _a-
@ -201,10 +200,10 @@ export defcell XNOR2_X1(bool! y; bool? a, b, vdd, vss)
b & _a | _b & a -> y- b & _a | _b & a -> y-
} }
sizing { _a{-1}; _b{-1}; y{-1} } sizing { _a{-1}; _b{-1}; y{-1} }
} }
export defcell MUX2_X1(bool! y; bool? a, b, S, vdd, vss) export defcell MUX2_X1(bool! y; bool? a, b, S, vdd, vss)
{ {
// y = !( S ? a : b ) // y = !( S ? a : b )
bool _S; bool _S;
prs { prs {
@ -214,46 +213,46 @@ export defcell MUX2_X1(bool! y; bool? a, b, S, vdd, vss)
a & S | b & _S -> y- a & S | b & _S -> y-
} }
sizing { _S{-1}; y{-1} } sizing { _S{-1}; y{-1} }
} }
export defcell OAI21_X1(bool! y; bool? a, b, c, vdd, vss) export defcell OAI21_X1(bool! y; bool? a, b, c, vdd, vss)
{ {
prs { prs {
(a | b) & c => y- (a | b) & c => y-
} }
sizing { y{-1} } sizing { y{-1} }
} }
export defcell AOI21_X1(bool! y; bool? a, b, c, vdd, vss) export defcell AOI21_X1(bool! y; bool? a, b, c, vdd, vss)
{ {
prs { prs {
a & b | c => y- a & b | c => y-
} }
sizing { y{-1} } sizing { y{-1} }
} }
export defcell OAI22_X1(bool! y; bool? a, b, c, d, vdd, vss) export defcell OAI22_X1(bool! y; bool? a, b, c, d, vdd, vss)
{ {
// y = !((a|b) & (c|d)) // y = !((a|b) & (c|d))
prs { prs {
(a | b) & (c | d) => y- (a | b) & (c | d) => y-
} }
sizing { y{-1} } sizing { y{-1} }
} }
export defcell AOI22_X1(bool! y; bool? a, b, c, d, vdd, vss) export defcell AOI22_X1(bool! y; bool? a, b, c, d, vdd, vss)
{ {
prs { prs {
a & b | c & d => y- a & b | c & d => y-
} }
sizing { y{-1} } sizing { y{-1} }
} }
/*--- buffered transmission gates ---*/ /*--- buffered transmission gates ---*/
export defcell TBUF1_X1 (bool! y; bool? a, en, vdd, vss) export defcell TBUF1_X1 (bool! y; bool? a, en, vdd, vss)
{ {
bool _en; bool _en;
prs { prs {
en => _en- en => _en-
@ -262,10 +261,10 @@ export defcell TBUF1_X1 (bool! y; bool? a, en, vdd, vss)
a & en -> y- a & en -> y-
} }
sizing { _en{-1}; y{-1} } sizing { _en{-1}; y{-1} }
} }
export defcell TBUF_X2 (bool! y; bool? a, en, vdd, vss) export defcell TBUF_X2 (bool! y; bool? a, en, vdd, vss)
{ {
bool _en; bool _en;
prs { prs {
en => _en- en => _en-
@ -274,6 +273,8 @@ export defcell TBUF_X2 (bool! y; bool? a, en, vdd, vss)
a & en -> y- a & en -> y-
} }
sizing { _en{-2}; y{-2,2} } sizing { _en{-2}; y{-2,2} }
}
}
} }