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2 Commits
21c78e4461
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8c4f081090
| Author | SHA1 | Date |
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 M. Mastella
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8c4f081090 | |
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M. Mastella
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f468913472 |
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@ -1,49 +1,55 @@
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t.ff.__clk_B t.ff._clk_B t.d t.clk
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t.ff.__clk_B t.ff._clk_B t.d t.clk t._clk_B
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[0] start test
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61021 Reset : 0
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61021 t.clk : 1
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61021 t.d : 0
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61022 t.ff._clk_B : 0 [by t.clk:=1]
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61023 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
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65875 t._reset_B : 1 [by Reset:=0]
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15221 Reset : 0
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15221 t.clk : 0
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15221 t.d : 0
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16947 t._clk_B : 1 [by t.clk:=0]
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16986 t.ff._clk_B : 0 [by t._clk_B:=1]
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17001 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
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80587 t._reset_B : 1 [by Reset:=0]
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[1] reset completed
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[2] tested d = 0, clk rise
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65875 t.clk : 0
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65875 t.d : 1
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84773 t.ff._mqib : 0 [by t.d:=1]
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85476 t.ff._mqi : 1 [by t.ff._mqib:=0]
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96922 t.ff._clk_B : 1 [by t.clk:=0]
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97123 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
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107244 t.ff._sqib : 0 [by t.ff._clk_B:=1]
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107250 t.ff._sqi : 1 [by t.ff._sqib:=0]
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110736 t.q : 1 [by t.ff._sqib:=0]
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110738 t.ff.q_B : 0 [by t.q:=1]
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110738 t.clk : 1
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113054 t.ff._clk_B : 0 [by t.clk:=1]
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113104 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
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113104 t.d : 0
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114289 t.ff._mqib : 1 [by t.d:=0]
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137967 t.ff._mqi : 0 [by t.ff._mqib:=1]
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137967 t.clk : 0
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137992 t.ff._clk_B : 1 [by t.clk:=0]
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138009 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
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138073 t.ff._sqib : 1 [by t.ff.__clk_B:=0]
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138074 t.q : 0 [by t.ff._sqib:=1]
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138478 t.ff._sqi : 0 [by t.ff._sqib:=1]
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203221 t.ff.q_B : 1 [by t.q:=0]
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203221 t.d : 1
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203221 t.clk : 1
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203222 t.ff._clk_B : 0 [by t.clk:=1]
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214646 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
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227406 t.ff._mqib : 0 [by t.ff.__clk_B:=1]
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227582 t.ff._mqi : 1 [by t.ff._mqib:=0]
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80587 t.clk : 1
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80587 t.d : 1
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80600 t.ff._mqib : 0 [by t.d:=1]
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80640 t.ff._mqi : 1 [by t.ff._mqib:=0]
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81078 t._clk_B : 0 [by t.clk:=1]
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81493 t.ff._clk_B : 1 [by t._clk_B:=0]
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81513 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
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87554 t.ff._sqib : 0 [by t.ff._clk_B:=1]
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87570 t.q : 1 [by t.ff._sqib:=0]
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87601 t.ff._sqi : 1 [by t.ff._sqib:=0]
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131668 t.ff.q_B : 0 [by t.q:=1]
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131668 t.clk : 0
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145392 t._clk_B : 1 [by t.clk:=0]
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145396 t.ff._clk_B : 0 [by t._clk_B:=1]
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154525 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
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154525 t.d : 0
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154540 t.ff._mqib : 1 [by t.d:=0]
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197788 t.ff._mqi : 0 [by t.ff._mqib:=1]
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197788 t.clk : 1
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234719 t._clk_B : 0 [by t.clk:=1]
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234774 t.ff._clk_B : 1 [by t._clk_B:=0]
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286427 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
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316207 t.ff._sqib : 1 [by t.ff.__clk_B:=0]
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330056 t.ff._sqi : 0 [by t.ff._sqib:=1]
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341019 t.q : 0 [by t.ff._sqib:=1]
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355362 t.ff.q_B : 1 [by t.q:=0]
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355362 t.clk : 0
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355784 t._clk_B : 1 [by t.clk:=0]
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404498 t.ff._clk_B : 0 [by t._clk_B:=1]
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404499 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
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404499 t.d : 1
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404500 t.ff._mqib : 0 [by t.d:=1]
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424705 t.ff._mqi : 1 [by t.ff._mqib:=0]
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[3] tested d = 1, clk rise and fall
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227582 t.clk : 0
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227583 t.ff._clk_B : 1 [by t.clk:=0]
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227590 t.ff._sqib : 0 [by t.ff._clk_B:=1]
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227593 t.q : 1 [by t.ff._sqib:=0]
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234776 t.ff.q_B : 0 [by t.q:=1]
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241004 t.ff._sqi : 1 [by t.ff._sqib:=0]
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278221 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
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278221 t.d : 0
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424705 t.clk : 1
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424987 t._clk_B : 0 [by t.clk:=1]
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425755 t.ff._clk_B : 1 [by t._clk_B:=0]
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425758 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
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448196 t.ff._sqib : 0 [by t.ff._clk_B:=1]
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448747 t.ff._sqi : 1 [by t.ff._sqib:=0]
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449267 t.q : 1 [by t.ff._sqib:=0]
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450221 t.ff.q_B : 0 [by t.q:=1]
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450221 t.d : 0
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@ -3,6 +3,8 @@
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= "Reset" "Reset"
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"Reset"->"t._reset_B"-
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~("Reset")->"t._reset_B"+
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"t.clk"->"t._clk_B"-
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~("t.clk")->"t._clk_B"+
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= "t._reset_B" "t.ff.reset_B"
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"t.ff.clk_B"->"t.ff._clk_B"-
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~("t.ff.clk_B")->"t.ff._clk_B"+
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@ -23,5 +25,5 @@
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= "Vdd" "t.ff.vdd"
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= "GND" "t.ff.vss"
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= "t.q" "t.ff.q"
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= "t.clk" "t.ff.clk_B"
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= "t._clk_B" "t.ff.clk_B"
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= "t.d" "t.ff.d"
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@ -32,13 +32,15 @@ import globals;
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open tmpl::dataflow_neuro;
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defproc flipflop_test (bool! q; bool? d,clk){
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DFFQ_R_X1 ff(.d=d,.clk_B = clk, .q = q);
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bool _clk_B;
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DFFQ_R_X1 ff(.d=d,.clk_B = _clk_B, .q = q);
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//Low active Reset
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bool _reset_B;
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prs {
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Reset => _reset_B-
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clk => _clk_B-
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}
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ff.vss = GND;
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ff.vdd = Vdd;
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ff.reset_B = _reset_B;
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@ -3,7 +3,7 @@ system "echo '[0] start test'"
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set Reset 0
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set t.d 0
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set t.clk 1
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set t.clk 0
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cycle
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status X
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mode run
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@ -12,18 +12,18 @@ assert t.q 0
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system "echo '[1] reset completed'"
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system "echo '[2] tested d = 0, clk rise'"
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set t.clk 0
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set t.clk 1
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set t.d 1
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cycle
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set t.clk 1
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set t.clk 0
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cycle
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set t.d 0
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cycle
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assert t.q 1
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set t.clk 0
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set t.clk 1
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cycle
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assert t.q 0
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@ -35,7 +35,7 @@ assert t.q 0
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set t.d 1
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cycle
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set t.clk 1
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set t.clk 0
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cycle
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assert t.q 0
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@ -43,7 +43,7 @@ system "echo '[3] tested d = 1, clk rise and fall'"
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set t.d 1
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cycle
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set t.clk 0
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set t.clk 1
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cycle
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set t.d 0
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cycle
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