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2 Commits
25e0b4b1a2 ... 1d542e8a15

Author SHA1 Message Date
alexmadison
1d542e8a15 added todo about line end pullups 2023-11-17 13:18:58 +01:00
alexmadison
1c4160092d fixed decoder_2d_hybrid unit test 2023-11-17 13:18:17 +01:00
3 changed files with 100 additions and 80 deletions
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2
dataflow_neuro/coders.act
View File

@ -433,6 +433,8 @@ defproc decoder_2d_synapse_hs (bool? in_req_x[Nx], in_req_y[Ny]; a1of1 synapses[
* ack_disable blocks the ack being returned to the buffer.
* Is needed in case there are instabilities while we fiddle with delays.
*/
// @TODO : think hard about the fact that the line end pullups are not placed manually,
// and write argumentation about whether this is fine
export template<pint NxC, NyC, Nx, Ny, N_dly_cfg>
defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; bool! out_req_x[Nx], out_req_y[Ny]; bool? dly_cfg[N_dly_cfg], hs_en, ack_disable;
bool in_ackB_decoder[Nx]; // AckB lines back to the decoder for handshaking

65
test/unit_tests/decoder_2d_hybrid/test.act
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@ -39,7 +39,7 @@ open std::data;
open tmpl::dataflow_neuro;
defproc decoder_2d_hybrid_2x4 (avMx1of2<3> in; a1of1 out[8]; bool? dly_cfg[4], hs_en){
defproc decoder_2d_hybrid_2x4 (avMx1of2<3> in; a1of1 out[8]; bool? dly_cfg[4], hs_en, ack_disable){
bool _reset_B;
prs {
Reset => _reset_B-
@ -48,38 +48,55 @@ defproc decoder_2d_hybrid_2x4 (avMx1of2<3> in; a1of1 out[8]; bool? dly_cfg[4], h
supply.vdd = Vdd;
supply.vss = GND;
decoder_2d_hybrid<1,2,2,4,4> decoder(.in = in, .dly_cfg = dly_cfg, .hs_en = hs_en,
decoder_2d_hybrid<1,2,2,4,4> decoder(.in = in, .dly_cfg = dly_cfg, .hs_en = hs_en, .ack_disable = ack_disable,
.reset_B = _reset_B, .supply = supply);
// model the synapse as having automatic pulldown of ack.
INV_X1 synapses[8];
AND2_X1 req_and2s[8];
// Dummy synapses to perform the handshaking.
// They consist of a grid of ANDs and pulldowns, and have the "synapses" exposed,\
// which would be the pulse extenders (which we thus short here)
pint index;
PULLDOWN_X4 synapses2[8];
(i:4:
(j:2:
index = i + 4*j;
decoder_2d_synapse_hs<2,4> syn_hs(.in_req_x = decoder.out_req_x, .in_req_y = decoder.out_req_y,
.out_ackB_decoder = decoder.in_ackB_decoder,
.to_pu = decoder.to_pu,
.synapses = out,
.supply = supply);
req_and2s[index].a = decoder.out_req_x[index];
req_and2s[index].b = decoder.out_req_y[index];
// synapses[index].a = decoder.out[index].r;
synapses[index].a = req_and2s[index].y;
synapses2[index].a = synapses[index].y;
synapses2[index].y = decoder.out[index].a;
synapses[index].vss = supply.vss;
synapses[index].vdd = supply.vdd;
synapses2[index].vss = supply.vss;
synapses2[index].vdd = supply.vdd;
req_and2s[index].vss = supply.vss;
req_and2s[index].vdd = supply.vdd;
// (i:8: syn_hs.synapses[i].a = syn_hs.synapses[i].r;)
)
// // model the synapse as having automatic pulldown of ack.
// INV_X1 synapses[8];
// AND2_X1 req_and2s[8];
// pint index;
// PULLDOWN_X4 synapses2[8];
// (i:4:
// (j:2:
// index = i + 4*j;
// req_and2s[index].a = decoder.out_req_x[index];
// req_and2s[index].b = decoder.out_req_y[index];
// // synapses[index].a = decoder.out[index].r;
// synapses[index].a = req_and2s[index].y;
// synapses2[index].a = synapses[index].y;
// synapses2[index].y = decoder.out[index].a;
// synapses[index].vss = supply.vss;
// synapses[index].vdd = supply.vdd;
// synapses2[index].vss = supply.vss;
// synapses2[index].vdd = supply.vdd;
// req_and2s[index].vss = supply.vss;
// req_and2s[index].vdd = supply.vdd;
// )
)
// )
}

113
test/unit_tests/decoder_2d_hybrid/test.prsim
View File

@ -8,7 +8,7 @@ set e.out[4].a 0
set e.out[5].a 0
set e.out[6].a 0
set e.out[7].a 0
cycle
set e.dly_cfg[0] 0
set e.dly_cfg[1] 0
set e.dly_cfg[2] 0
@ -16,6 +16,8 @@ set e.dly_cfg[3] 0
set e.hs_en 1
set e.ack_disable 0
set-qdi-channel-neutral "e.in" 3
set Reset 1
@ -58,16 +60,15 @@ assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 0
assert e.in.v 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
set e.out[0].a 0
set e.out[1].a 0
set e.out[2].a 0
set e.out[3].a 0
set e.out[4].a 0
set e.out[5].a 0
set e.out[6].a 0
set e.out[7].a 0
cycle
@ -102,15 +103,15 @@ assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 0
assert e.in.v 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
set e.out[0].a 0
set e.out[1].a 0
set e.out[2].a 0
set e.out[3].a 0
set e.out[4].a 0
set e.out[5].a 0
set e.out[6].a 0
set e.out[7].a 0
cycle
system "echo '[] Sending in a 1 packet'"
@ -140,15 +141,15 @@ assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
set e.out[0].a 0
set e.out[1].a 0
set e.out[2].a 0
set e.out[3].a 0
set e.out[4].a 0
set e.out[5].a 0
set e.out[6].a 0
set e.out[7].a 0
cycle
assert e.in.a 1
assert e.in.v 1
@ -197,15 +198,15 @@ assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 0
assert e.in.v 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
set e.out[0].a 0
set e.out[1].a 0
set e.out[2].a 0
set e.out[3].a 0
set e.out[4].a 0
set e.out[5].a 0
set e.out[6].a 0
set e.out[7].a 0
cycle
@ -241,15 +242,15 @@ assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 0
assert e.in.v 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
set e.out[0].a 0
set e.out[1].a 0
set e.out[2].a 0
set e.out[3].a 0
set e.out[4].a 0
set e.out[5].a 0
set e.out[6].a 0
set e.out[7].a 0
cycle
system "echo '[] Sending in a 1 packet'"
@ -279,15 +280,15 @@ assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
set e.out[0].a 0
set e.out[1].a 0
set e.out[2].a 0
set e.out[3].a 0
set e.out[4].a 0
set e.out[5].a 0
set e.out[6].a 0
set e.out[7].a 0
cycle
assert e.in.a 1
assert e.in.v 1