hybrid decoder in fifo train working

dataflow_neuro/coders.act

@@ -270,6 +270,9 @@ export template<pint NxC, NyC, Nx, Ny, N_dly_cfg>
 defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg[N_dly_cfg], hs_en,
 	reset_B; power supply) {
 
+	bool hs_enB;
+	INV_X4 hs_inv(.a = hs_en, .y = hs_enB, .vdd = supply.vdd, .vss = supply.vss);
+
 	// Buffer to recieve concat(x,y) address packet
 	buffer<NxC+NyC> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
 
@@ -323,10 +326,11 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 	// bc smaller
 	// and bc the delay that an AND induces means that the pullup could
 	// end up fighting a synapse pulldown, as both have the correct req sigs.
-	A_1P_U_X4 pu[Nx]; // TODO probably replace this with variable strength PU
+	A_2P_U_X4 pu[Nx]; // TODO probably replace this with variable strength PU
 	A_1P_U_X4 pu_reset[Nx];
 	(i:Nx:
 		pu[i].a = d_dr_xX[i].out[Ny];
+		pu[i].b = hs_enB;
 		pu[i].y = _out_acksB[i];
 		pu[i].vdd = supply.vdd;
 		pu[i].vss = supply.vss;
@@ -354,17 +358,15 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 	// _only_ once _both_ ackB has been reset, _and_ its output data
 	// has been fully invalidated.
 	// Otherwise run into the issue that ack is removed before data is invalid.
-	A_2C_B_X1 buf_ack_Cel(.c1 = _ortree.out, .c2 = valid_Cel.y, .y = addr_buf.out.a,
+	A_2C_B_X1 buf_ack_Cel(.c1 = _ortree.out, .c2 = valid_Cel.y,
 		.vdd = supply.vdd, .vss = supply.vss);
 
-	
+	// Mux to switch between acks from handshake or delay
-
+	MUX2_X1 ack_mux(.s = hs_en, .a = valid_Cel.y, .b = buf_ack_Cel.y,
+		.vdd = supply.vdd, .vss = supply.vss);
 
 	// Programmable delay
-	delayprog<N_dly_cfg> dly(.s = dly_cfg, .supply = supply);
+	delayprog<N_dly_cfg> dly(.in = ack_mux.y, .out = addr_buf.out.a, .s = dly_cfg, .supply = supply);
-	dly.out = addr_buf.out.a;
-
-
 
 }
 

test/unit_tests/decoder_2d_hybrid/test.act

@@ -0,0 +1,74 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/primitives.act";
+import "../../dataflow_neuro/cell_lib_async.act";
+import "../../dataflow_neuro/cell_lib_std.act";
+
+
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc decoder_2d_hybrid_2x4 (avMx1of2<3> in; a1of1 out[8]; bool? dly_cfg[4], hs_en){
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    decoder_2d_hybrid<1,2,2,4,4> decoder(.in = in, .out = out, .dly_cfg = dly_cfg, .hs_en = hs_en,
+        .reset_B = _reset_B, .supply = supply);
+
+    // model the synapse as having automatic pulldown of ack.
+    INV_X1 synapses[8];
+    
+    PULLDOWN_X4 synapses2[8];
+    (i:8:
+        synapses[i].a = decoder.out[i].r;
+        synapses2[i].a = synapses[i].y; 
+        synapses2[i].y = decoder.out[i].a;
+
+        synapses[i].vss = supply.vss;
+        synapses[i].vdd = supply.vdd;
+        synapses2[i].vss = supply.vss;
+        synapses2[i].vdd = supply.vdd;
+
+    )
+
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+decoder_2d_hybrid_2x4 e; 

test/unit_tests/decoder_2d_hybrid/test.prsim

@@ -0,0 +1,341 @@
+watchall
+
+set e.out[0].a 0
+set e.out[1].a 0
+set e.out[2].a 0
+set e.out[3].a 0
+set e.out[4].a 0
+set e.out[5].a 0
+set e.out[6].a 0
+set e.out[7].a 0
+
+set e.dly_cfg[0] 0
+set e.dly_cfg[1] 0
+set e.dly_cfg[2] 0
+set e.dly_cfg[3] 0
+
+set e.hs_en 1
+
+set-qdi-channel-neutral "e.in" 3
+set Reset 1
+
+cycle
+
+mode run
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+
+system "echo '[] Sending in a 7 packet'"
+set-qdi-channel-valid "e.in" 3 7
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 1
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+
+
+system "echo '[] Synapse [7] gives ack'"
+set e.out[7].a 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 0
+assert e.in.v 0
+assert e.out[0].a 0
+assert e.out[1].a 0
+assert e.out[2].a 0
+assert e.out[3].a 0
+assert e.out[4].a 0
+assert e.out[5].a 0
+assert e.out[6].a 0
+assert e.out[7].a 0
+
+
+
+
+
+system "echo '[] Sending in a 5 packet'"
+set-qdi-channel-valid "e.in" 3 5
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 1
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+
+
+system "echo '[] Synapse [5] gives ack'"
+set e.out[5].a 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 0
+assert e.in.v 0
+assert e.out[0].a 0
+assert e.out[1].a 0
+assert e.out[2].a 0
+assert e.out[3].a 0
+assert e.out[4].a 0
+assert e.out[5].a 0
+assert e.out[6].a 0
+assert e.out[7].a 0
+
+
+
+system "echo '[] Sending in a 1 packet'"
+set-qdi-channel-valid "e.in" 3 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 1
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 1
+assert e.in.v 1
+
+
+system "echo '[] Synapse [1] gives ack'"
+set e.out[1].a 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+
+assert e.out[0].a 0
+assert e.out[1].a 0
+assert e.out[2].a 0
+assert e.out[3].a 0
+assert e.out[4].a 0
+assert e.out[5].a 0
+assert e.out[6].a 0
+assert e.out[7].a 0
+
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input, enabling delays'"
+set-qdi-channel-neutral "e.in" 3
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+
+system "echo '[] Enabling delays'"
+cycle
+set e.dly_cfg[0] 1
+set e.dly_cfg[1] 1
+set e.dly_cfg[2] 1
+set e.dly_cfg[3] 1
+
+system "echo '[] Sending in a 7 packet, with delays'"
+set-qdi-channel-valid "e.in" 3 7
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 1
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+
+
+system "echo '[] Synapse [7] gives ack'"
+set e.out[7].a 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 0
+assert e.in.v 0
+assert e.out[0].a 0
+assert e.out[1].a 0
+assert e.out[2].a 0
+assert e.out[3].a 0
+assert e.out[4].a 0
+assert e.out[5].a 0
+assert e.out[6].a 0
+assert e.out[7].a 0
+
+
+
+
+
+system "echo '[] Sending in a 5 packet'"
+set-qdi-channel-valid "e.in" 3 5
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 1
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+
+
+system "echo '[] Synapse [5] gives ack'"
+set e.out[5].a 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 0
+assert e.in.v 0
+assert e.out[0].a 0
+assert e.out[1].a 0
+assert e.out[2].a 0
+assert e.out[3].a 0
+assert e.out[4].a 0
+assert e.out[5].a 0
+assert e.out[6].a 0
+assert e.out[7].a 0
+
+
+
+system "echo '[] Sending in a 1 packet'"
+set-qdi-channel-valid "e.in" 3 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 1
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+assert e.in.a 1
+assert e.in.v 1
+
+
+system "echo '[] Synapse [1] gives ack'"
+set e.out[1].a 1
+cycle
+assert e.out[0].r 0
+assert e.out[1].r 0
+assert e.out[2].r 0
+assert e.out[3].r 0
+assert e.out[4].r 0
+assert e.out[5].r 0
+assert e.out[6].r 0
+assert e.out[7].r 0
+
+assert e.out[0].a 0
+assert e.out[1].a 0
+assert e.out[2].a 0
+assert e.out[3].a 0
+assert e.out[4].a 0
+assert e.out[5].a 0
+assert e.out[6].a 0
+assert e.out[7].a 0
+
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input, disabling handshaking'"
+set-qdi-channel-neutral "e.in" 3
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+set e.hs_en 0
+cycle
+
+system "echo '[] Sending in a 0, handshaking disabled'"
+set-qdi-channel-valid "e.in" 3 0
+cycle
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+system "echo '[] Sending in a 7, handshaking disabled'"
+set-qdi-channel-valid "e.in" 3 7
+cycle
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+
+system "echo '[] Sending in a 5, handshaking disabled'"
+set-qdi-channel-valid "e.in" 3 5
+cycle
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 3
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+
+

test/unit_tests/fifo-decoder_hybrid-neurons-encoder-fifo/test.act

@@ -0,0 +1,73 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/primitives.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc fifo_decoder_neurons_encoder_fifo (avMx1of2<7> in; avMx1of2<7> out; bool? dly_cfg[4], hs_en){
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    pint NxC,NyC,Nx,Ny;
+    NxC = 4;
+    NyC = 3;
+    Nx = 1<<NxC;
+    Ny = 1<<NyC;
+
+    fifo<NxC + NyC,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);
+    decoder_2d_hybrid<NxC,NyC,Nx,Ny,4> decoder(.in = fifo_pre.out, .dly_cfg =dly_cfg, .hs_en = hs_en,
+        .reset_B = _reset_B, .supply = supply);
+    // Pretend that each "synapse" immediately makes its one neuron "spike".
+    // that is, connect the output of each encoder target to the decoder input.
+    nrn_hs_2D_array<Nx,Ny,10> neuron_grid(.reset_B = _reset_B, .supply = supply);
+    (i:Nx*Ny:
+        neuron_grid.in[i].r = decoder.out[i].r;
+        neuron_grid.in[i].a = decoder.out[i].a;
+    )
+
+    encoder2D<NxC,NyC,Nx,Ny,4> encoder(.inx = neuron_grid.outx, .iny = neuron_grid.outy,
+        .reset_B = _reset_B, .supply = supply);
+    fifo<NxC + NyC,5> fifo_post(.in = encoder.out, .out = out, .reset_B = _reset_B, .supply = supply);
+
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+fifo_decoder_neurons_encoder_fifo e; 

test/unit_tests/fifo-decoder_hybrid-neurons-encoder-fifo/test.prsim

@@ -0,0 +1,149 @@
+watchall
+
+
+# Use handshaking at first
+set e.dly_cfg[0] 0
+set e.dly_cfg[1] 0
+set e.dly_cfg[2] 0
+set e.dly_cfg[3] 0
+set e.hs_en 1
+
+
+
+set e.out.a 0
+set e.out.v 0
+set-qdi-channel-neutral "e.in" 7
+set Reset 1
+
+cycle
+
+
+mode run
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+
+
+
+system "echo '[] Sending in a packet'"
+set-qdi-channel-valid "e.in" 7 75
+cycle
+assert-qdi-channel-valid "e.out" 7 75
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 7
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+system "echo '[] Sending in another packet'"
+set-qdi-channel-valid "e.in" 7 22
+cycle
+# Output is still the first packet
+assert-qdi-channel-valid "e.out" 7 75
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 7
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+system "echo '[] Giving out ack'"
+set e.out.a 1
+set e.out.v 1
+cycle
+assert-qdi-channel-neutral "e.out" 7
+
+system "echo '[] Removing ack'"
+set e.out.a 0
+set e.out.v 0
+cycle
+assert-qdi-channel-valid "e.out" 7 22
+
+system "echo '[] Giving out ack'"
+set e.out.a 1
+set e.out.v 1
+cycle
+assert-qdi-channel-neutral "e.out" 7
+
+system "echo '[] Removing ack'"
+set e.out.a 0
+set e.out.v 0
+cycle
+assert-qdi-channel-neutral "e.out" 7
+
+
+# Enable delays
+set e.dly_cfg[0] 1
+set e.dly_cfg[1] 1
+set e.dly_cfg[2] 1
+set e.dly_cfg[3] 1
+set e.hs_en 0
+cycle
+
+
+
+mode run
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+
+
+
+system "echo '[] Sending in a packet WITH DELAYS'"
+set-qdi-channel-valid "e.in" 7 75
+cycle
+assert-qdi-channel-valid "e.out" 7 75
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 7
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+system "echo '[] Sending in another packet'"
+set-qdi-channel-valid "e.in" 7 22
+cycle
+# Output is still the first packet
+assert-qdi-channel-valid "e.out" 7 75
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 7
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+system "echo '[] Giving out ack'"
+set e.out.a 1
+set e.out.v 1
+cycle
+assert-qdi-channel-neutral "e.out" 7
+
+system "echo '[] Removing ack'"
+set e.out.a 0
+set e.out.v 0
+cycle
+assert-qdi-channel-valid "e.out" 7 22
+
+system "echo '[] Giving out ack'"
+set e.out.a 1
+set e.out.v 1
+cycle
+assert-qdi-channel-neutral "e.out" 7
+
+system "echo '[] Removing ack'"
+set e.out.a 0
+set e.out.v 0
+cycle
+assert-qdi-channel-neutral "e.out" 7
+