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base: bics:5aab3d2d3b111f9d8bca69fa9017a58f96072dc1
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bics:dev
bics:main
bics:encoder_wip
bics:TexelTapeout
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compare: bics:c81e77a2fa334378bb612b878d40b3e27835262c
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bics:main
bics:dev
bics:encoder_wip
bics:TexelTapeout

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2 changed files with 13 additions and 66 deletions
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32
dataflow_neuro/chips.act
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@ -133,58 +133,34 @@ defproc chip_texel (bd<N_IN> in, out;
pint NC_SYN_MON_X = std::ceil_log2(N_SYN_MON_X);
pint NC_SYN_MON_Y = std::ceil_log2(N_SYN_MON_Y);
decoder_dualrail_en<NC_NRN_MON_X, N_NRN_MON_X> nrn_mon_dec_x(.out = nrn_mon_x,
decoder_dualrail_en<NC_NRN_MON_X, N_NRN_MON_X, N_NRN_Y> nrn_mon_dec_x(.out = nrn_mon_x,
.supply = supply);
nrn_mon_dec_x.en = register.data[1].d[0].t;
(i:NC_NRN_MON_X:
nrn_mon_dec_x.in.d[i] = register.data[2].d[i];
)
decoder_dualrail_en<NC_NRN_MON_Y, N_NRN_MON_Y> nrn_mon_dec_y(.out = nrn_mon_y,
decoder_dualrail_en<NC_NRN_MON_Y, N_NRN_MON_Y, N_NRN_X> nrn_mon_dec_y(.out = nrn_mon_y,
.supply = supply);
nrn_mon_dec_y.en = register.data[1].d[0].t;
(i:NC_NRN_MON_Y:
nrn_mon_dec_y.in.d[i] = register.data[2].d[i+NC_NRN_MON_X];
)
decoder_dualrail_en<NC_SYN_MON_X, N_SYN_MON_X> syn_mon_dec_x(
decoder_dualrail_en<NC_SYN_MON_X, N_SYN_MON_X, N_SYN_Y> syn_mon_dec_x(.out = syn_mon_x,
.supply = supply);
syn_mon_dec_x.en = register.data[1].d[1].t;
(i:NC_SYN_MON_X:
syn_mon_dec_x.in.d[i] = register.data[3].d[i];
)
decoder_dualrail_en<NC_SYN_MON_Y, N_SYN_MON_Y> syn_mon_dec_y(.out = syn_mon_y,
decoder_dualrail_en<NC_SYN_MON_Y, N_SYN_MON_Y, N_SYN_X> syn_mon_dec_y(.out = syn_mon_y,
.supply = supply);
syn_mon_dec_y.en = register.data[1].d[1].t;
(i:NC_SYN_MON_Y:
syn_mon_dec_y.in.d[i] = register.data[3].d[i+NC_SYN_MON_X];
)
// Device debug hard-wired safety (reg0, b05 = DEV_DEBUG)
// Stops the possibility of dev_mon being high while some other sig is high.
// Otherwise boom.
bool DEV_DEBUG;
pint NSMX4 = N_SYN_MON_X/4; // Self explanatory
sigbuf<NSMX4> sb_DEV_DEBUG(.in = register.data[0].d[5].t,
.supply = supply);
DEV_DEBUG = sb_DEV_DEBUG.out[0];
AND2_X1 ands_devmon[NSMX4];
(i:NSMX4:
ands_devmon[i].a = syn_mon_dec_x.out[1+i*4];
ands_devmon[i].b = DEV_DEBUG;
ands_devmon[i].y = syn_mon_x[1+i*4];
ands_devmon[i].vdd = supply.vdd;
ands_devmon[i].vss = supply.vss;
)
// Wire up the non-ANDed lines.
(i:N_SYN_MON_X:
[~(i%4 = 1) ->
syn_mon_x[i] = syn_mon_dec_x.out[i];
]
)
}
}
}

47
dataflow_neuro/coders.act
View File

@ -105,13 +105,14 @@ defproc decoder_dualrail_x(Mx1of2<Nc> in; bool? out[N*OUT_STRENGTH]; power suppl
/**
* Dualrail decoder with on/off switch.
* Outputs are NOT buffered.
* Outputs are buffered.
*/
export template<pint Nc, N>
defproc decoder_dualrail_en(Mx1of2<Nc> in; bool? en, out[N]; power supply) {
export template<pint Nc, N, OUT_STRENGTH>
defproc decoder_dualrail_en(Mx1of2<Nc> in; bool? en, out[N*OUT_STRENGTH]; power supply) {
decoder_dualrail<Nc, N> decoder(.in = in, .supply = supply);
sigbuf<N> sb_en(.in = en, .supply = supply);
sigbuf<OUT_STRENGTH> sb[N];
AND2_X1 en_ands[N];
(i:N:
en_ands[i].a = decoder.out[i];
@ -120,46 +121,16 @@ defproc decoder_dualrail_en(Mx1of2<Nc> in; bool? en, out[N]; power supply) {
en_ands[i].vdd = supply.vdd;
en_ands[i].vss = supply.vss;
en_ands[i].y = out[i];
sb[i].in = en_ands[i].y;
sb[i].supply = supply;
(j:OUT_STRENGTH:
sb[i].out[j] = out[j + i*OUT_STRENGTH];
)
)
}
/**
* Dualrail decoder with on/off switch.
* Outputs are buffered.
*/
// export template<pint Nc, N, OUT_STRENGTH>
// defproc decoder_dualrail_en_x(Mx1of2<Nc> in; bool? en, out[N]; power supply) {
// decoder_dualrail<Nc, N> decoder(.in = in, .supply = supply);
// sigbuf<N> sb_en(.in = en, .supply = supply);
// sigbuf<OUT_STRENGTH> sb[N];
// AND2_X1 en_ands[N];
// (i:N:
// en_ands[i].a = decoder.out[i];
// en_ands[i].b = sb_en.out[i];
// en_ands[i].vdd = supply.vdd;
// en_ands[i].vss = supply.vss;
// sb[i].in = en_ands[i].y;
// sb[i].supply = supply;
// // (j:OUT_STRENGTH:
// // sb[i].out[j] = out[j + i*OUT_STRENGTH];
// // )
// sb[i].out[0] = out[i];
// )
// }
/**