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Author SHA1 Message Date
Michele f7cd7006d0 removed arbiter_tree from primitives because is already in coders 2022-03-03 12:15:17 +01:00
Michele 24a6260862 Merged encoder_wip into dev 2022-03-03 12:14:48 +01:00
Michele f5859040d8 Arbiter tree test 2022-03-03 12:11:20 +01:00
Michele 3e1b63c201 continued handshaking tree, not finished 2022-03-03 12:11:20 +01:00
Michele b49b9d98c3 started arbiter tree 2022-03-03 12:11:20 +01:00
4 changed files with 131 additions and 0 deletions

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@ -507,6 +507,8 @@ namespace tmpl {
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
}
export template<pint N>
defproc merge (avMx1of2<N> in1; avMx1of2<N> in2; avMx1of2<N> out ; bool? reset_B; power supply) {

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@ -0,0 +1,3 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"

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@ -0,0 +1,62 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc arbiter_treee (a1of1 in[5]; a1of1 out)
{
a1of1 _in[5];
power _supply
_supply.vdd = Vdd;
_supply.vss = GND;
fifo_t<2> fifo_to_tree[5];
(i:5:
fifo_to_tree[i].in = in[i];
fifo_to_tree[i].out = _in[i];
fifo_to_tree.supply = _supply;
fifo_to_tree.reset_B = _reset_B;
)
arbiter_tree<5> at_cell(.in=_in, .out = out);
//Low active Reset
bool _reset_B;
prs {
Reset => _reset_B-
}
at_cell.supply = _supply;
}
arbiter_treee my_tree;

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@ -0,0 +1,64 @@
watchall
set Reset 1
set my_tree.in[0].r 0
set my_tree.in[1].r 0
set my_tree.in[2].r 0
set my_tree.in[3].r 0
set my_tree.in[4].r 0
set my_tree.out.a 0
cycle
assert my_tree.in[0].a 0
assert my_tree.in[1].a 0
assert my_tree.in[2].a 0
assert my_tree.in[3].a 0
assert my_tree.in[4].a 0
assert my_tree.out.r 0
system "echo '-------------------------------------------------'"
system "echo '[0] System initialized'"
set Reset 0
cycle
system "echo '-------------------------------------------------'"
system "echo '[1] System reset completed'"
set in[0].r 1
set in[2].r 1
set in[4].r 1
cycle
assert out.r 1
set out.a 1
cycle
assert out.r 0
set out.a 0
cycle
assert out.r 1
set out.a 1
cycle
assert out.r 0
set out.a 0
cycle
assert out.r 1
set out.a 1
cycle
assert out.r 0
set out.a 0
cycle
system "echo '-------------------------------------------------'"
system "echo '[3] Sent three inputs, received 3 outputs'"