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@ -507,6 +507,8 @@ namespace tmpl {
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BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
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BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
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}
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}
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export template<pint N>
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export template<pint N>
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defproc merge (avMx1of2<N> in1; avMx1of2<N> in2; avMx1of2<N> out ; bool? reset_B; power supply) {
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defproc merge (avMx1of2<N> in1; avMx1of2<N> in2; avMx1of2<N> out ; bool? reset_B; power supply) {
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3
test/unit_tests/arbiter_tree_test/run/test.prs
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3
test/unit_tests/arbiter_tree_test/run/test.prs
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= "GND" "GND"
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= "Vdd" "Vdd"
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= "Reset" "Reset"
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62
test/unit_tests/arbiter_tree_test/test.act
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62
test/unit_tests/arbiter_tree_test/test.act
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/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library.
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* It's the testing facility for cell_lib_std.act
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/primitives.act";
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import globals;
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open tmpl::dataflow_neuro;
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defproc arbiter_treee (a1of1 in[5]; a1of1 out)
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{
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a1of1 _in[5];
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power _supply
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_supply.vdd = Vdd;
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_supply.vss = GND;
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fifo_t<2> fifo_to_tree[5];
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(i:5:
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fifo_to_tree[i].in = in[i];
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fifo_to_tree[i].out = _in[i];
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fifo_to_tree.supply = _supply;
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fifo_to_tree.reset_B = _reset_B;
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)
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arbiter_tree<5> at_cell(.in=_in, .out = out);
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//Low active Reset
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bool _reset_B;
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prs {
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Reset => _reset_B-
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}
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at_cell.supply = _supply;
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}
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arbiter_treee my_tree;
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64
test/unit_tests/arbiter_tree_test/test.prsim
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64
test/unit_tests/arbiter_tree_test/test.prsim
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watchall
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set Reset 1
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set my_tree.in[0].r 0
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set my_tree.in[1].r 0
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set my_tree.in[2].r 0
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set my_tree.in[3].r 0
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set my_tree.in[4].r 0
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set my_tree.out.a 0
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cycle
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assert my_tree.in[0].a 0
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assert my_tree.in[1].a 0
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assert my_tree.in[2].a 0
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assert my_tree.in[3].a 0
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assert my_tree.in[4].a 0
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assert my_tree.out.r 0
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system "echo '-------------------------------------------------'"
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system "echo '[0] System initialized'"
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set Reset 0
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cycle
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system "echo '-------------------------------------------------'"
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system "echo '[1] System reset completed'"
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set in[0].r 1
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set in[2].r 1
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set in[4].r 1
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cycle
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assert out.r 1
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set out.a 1
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cycle
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assert out.r 0
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set out.a 0
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cycle
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assert out.r 1
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set out.a 1
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cycle
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assert out.r 0
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set out.a 0
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cycle
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assert out.r 1
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set out.a 1
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cycle
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assert out.r 0
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set out.a 0
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cycle
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system "echo '-------------------------------------------------'"
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system "echo '[3] Sent three inputs, received 3 outputs'"
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