dataflow_neuro/primitives.act

@@ -165,7 +165,7 @@ namespace tmpl {
             fifo_element[i].supply = supply;
             fifo_element[i].reset_B = _reset_BXX[i];
           )
-          fifo_element[M-1].out = out;
+          fifo_element[N-1].out = out;
 
           // reset buffers
           bool _reset_BX;
@@ -697,7 +697,6 @@ namespace tmpl {
           PULLUP_X4 pull_up(.a=nor_out, .y=out);
         }
 
-        export
         defproc line_end_pull_down (a1of1 in; bool? reset_B; power supply; bool! out)
         {
           bool _out, __out, nor_out;
@@ -708,61 +707,4 @@ namespace tmpl {
 
           PULLUP_X4 pull_down(.a=nor_out, .y=out);
         }
-        
-
-        
-
-        /**
-         * Appends a hard-coded word "VAL" to an input.
-         * Works by piping through all sigs, but adding
-         * some extra sigs when the input is valid.
-         * N is size of channel to pipe through.
-         * NVAL is size of word to be put on output.
-         * VAL is word to be put on output.
-         *
-         */
-        export template<pint N, NVAL, VAL>
-        defproc append (avMx1of2<N> in; avMx1of2<N+NVAL> out; power supply)
-        {
-            { N >= 0 : "What?" };
-            { NVAL >= 0 : "What?" };
-            { NVAL < 1<<VAL : "VAL too big!" };
-
-            // valid tree
-            vtree<N> in_val(.supply = supply);
-            (i:N:
-                in_val.in.d[i].t = in.d.d[i].t;
-                in_val.in.d[i].f = in.d.d[i].f;
-            )
-
-            // wire through most signals
-            (i:N:
-                in.d.d[i].t = out.d.d[i].t;
-                in.d.d[i].f = out.d.d[i].f;
-            )
-            in.a = out.a;
-            in.v = out.v;
-
-            // appender
-            pint bitval;
-            sigbuf<NVAL> sb(.in = in_val.out, .supply = supply);
-            TIELO_X1 tielows[NVAL];
-            (i:NVAL:tielows[i].vss = supply.vss; tielows[i].vdd = supply.vdd;)
-            (i:0..NVAL-1:
-                bitval = (VAL & ( 1 << i )) >> i;
-                [  bitval = 1 ->
-                    out.d.d[i+N].t = sb.out[i];
-                    out.d.d[i+N].f = tielows[i].y;
-                [] bitval = 0 ->
-                    out.d.d[i+N].f = sb.out[i];
-                    out.d.d[i+N].t = tielows[i].y;
-                [] bitval >= 2 -> {false : "fuck"};        
-                ]
-            )
-
-        }
-
-
-
-
 }}

test/unit_tests/append_5_3_2/test.act

@@ -1,53 +0,0 @@
-/*************************************************************************
- *
- *  This file is part of ACT dataflow neuro library.
- *  It's the testing facility for cell_lib_std.act
- *
- *  Copyright (c) 2022 University of Groningen - Ole Richter  
- *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
- *  Copyright (c) 2022 University of Groningen - Michele Mastella
- *  Copyright (c) 2022 University of Groningen - Madison Cotteret
- *
- *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
- *
- *  You may redistribute and modify this documentation and make products
- *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
- *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
- *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
- *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
- *  for applicable conditions.
- *
- *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
- *
- *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
- *  these sources, You must maintain the Source Location visible in its
- *  documentation.
- *
- **************************************************************************
- */
-
-import "../../dataflow_neuro/primitives.act";
-import globals;
-
-open tmpl::dataflow_neuro;
-
-defproc append_5_3_2(avMx1of2<5> in; avMx1of2<8> out)
-{
-  bool _reset_B; 
-  prs {
-    Reset => _reset_B-
-  }
-
-  fifo<5,4> fifo_pre(.in = in, .reset_B = _reset_B);
-  append<5,3,3> app(.in = fifo_pre.out);
-  fifo<5+3,4> fifo_post(.in = app.out, .out = out, .reset_B = _reset_B);
-
-  app.supply.vdd = Vdd;
-  app.supply.vss = GND;
-  fifo_pre.supply.vdd = Vdd;
-  fifo_pre.supply.vss = GND;
-  fifo_post.supply.vdd = Vdd;
-  fifo_post.supply.vss = GND;
-}
-
-append_5_3_2 b;

test/unit_tests/append_5_3_2/test.prsim

@@ -1,78 +0,0 @@
-watchall
-
-set b.out.a 0
-set b.out.v 0
-set Reset 0
-set-qdi-channel-neutral "b.in" 5
-cycle
-
-system "echo '[] set Reset 1'"
-set Reset 1
-cycle
-
-system "echo '[] set Reset 0'"
-set Reset 0
-mode run
-cycle
-status X
-assert-qdi-channel-neutral "b.out" 8
-assert b.in.a 0
-assert b.in.v 0
-
-system "echo '[] sending in a 31'"
-set-qdi-channel-valid "b.in" 5 31
-cycle
-assert-qdi-channel-valid "b.out" 8 127
-assert b.in.a 1
-assert b.in.v 1
-
-system "echo '[] removing input'"
-set-qdi-channel-neutral "b.in" 5
-cycle
-assert b.in.a 0
-assert b.in.v 0
-
-system "echo '[] sending in a 0'"
-set-qdi-channel-valid "b.in" 5 0
-cycle
-# assert-qdi-channel-valid "b.out" 8 96
-assert b.in.a 1
-assert b.in.v 1
-
-system "echo '[] removing input'"
-set-qdi-channel-neutral "b.in" 5
-cycle
-assert b.in.a 0
-assert b.in.v 0
-
-
-system "echo '[] receiving out ack/val'"
-set b.out.a 1
-set b.out.v 1
-cycle
-assert-qdi-channel-neutral "b.out" 8
-
-
-system "echo '[] removing out ack/val'"
-set b.out.a 0
-set b.out.v 0
-cycle
-assert-qdi-channel-valid "b.out" 8 96
-
-
-system "echo '[] receiving out ack/val'"
-set b.out.a 1
-set b.out.v 1
-cycle
-assert-qdi-channel-neutral "b.out" 8
-
-
-system "echo '[] removing out ack/val'"
-set b.out.a 0
-set b.out.v 0
-cycle
-assert-qdi-channel-neutral "b.out" 8
-
-
-
-