unit test for hs

dataflow_neuro/coders.act

@@ -486,9 +486,17 @@ namespace tmpl {
 
 			bool _en, _req;
 			
-			A_1C2N_RB_X1 A_ack(.c1 = _en, .n1 = _req, .n2 = in.r, .y = in.a,
+			// A_1C2N_RB_X1 A_ack(.c1 = _en, .n1 = _req, .n2 = in.r, .y = in.a,
+			// 	.pr_B = _reset_BX, .sr_B = _reset_BX, .vss = supply.vss, .vdd = supply.vdd);
+
+			// Switched it back
+			// Because had the problem that if the req was not removed in time,
+			// it would be recounted as a double spike,
+			// since in.req is still high after the out has been dealt with.
+			A_2C1N_RB_X1 A_ack(.c1 = _en, .c2 = in.r, .n1 = _req, .y = in.a,
 				.pr_B = _reset_BX, .sr_B = _reset_BX, .vss = supply.vss, .vdd = supply.vdd);
 
+
 			A_1C1P_X1 A_en(.p1 = _req, .c1 = in.a, .y = _en,
 				.vss = supply.vss, .vdd = supply.vdd);
 

test/unit_tests/nrn_hs_2D_array_3x5/test.act

@@ -0,0 +1,46 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import globals;
+
+open tmpl::dataflow_neuro;
+
+defproc nrn_hs_2D_array_3x5(a1of1 in[15]; a1of1 outx[3], outy[5])
+{
+  bool _reset_B; 
+  prs {
+    Reset => _reset_B-
+  }
+  nrn_hs_2D_array<3,5,5> b(.in = in, .outx = outx, .outy = outy);
+  b.supply.vdd = Vdd;
+  b.supply.vss = GND; 
+  b.reset_B = _reset_B;
+}
+
+nrn_hs_2D_array_3x5 b;

test/unit_tests/nrn_hs_2D_array_3x5/test.prsim

@@ -0,0 +1,202 @@
+watchall
+
+set b.in[0].r 0
+set b.in[1].r 0
+set b.in[2].r 0
+set b.in[3].r 0
+set b.in[4].r 0
+set b.in[5].r 0
+set b.in[6].r 0
+set b.in[7].r 0
+set b.in[8].r 0
+set b.in[9].r 0
+set b.in[10].r 0
+set b.in[11].r 0
+set b.in[12].r 0
+set b.in[13].r 0
+set b.in[14].r 0
+
+set b.outx[0].a 0
+set b.outx[1].a 0
+set b.outx[2].a 0
+
+set b.outy[0].a 0
+set b.outy[1].a 0
+set b.outy[2].a 0
+set b.outy[3].a 0
+set b.outy[4].a 0
+
+set b.outx[0].r 1
+set b.outx[1].r 1
+set b.outx[2].r 1
+
+set b.outy[0].r 1
+set b.outy[1].r 1
+set b.outy[2].r 1
+set b.outy[3].r 1
+set b.outy[4].r 0
+
+set b.b.neurons[0]._en 0
+set b.b.neurons[0]._req 1
+
+# set Reset 0
+cycle
+
+system "echo '[] set Reset 1'"
+set Reset 1
+cycle
+status X
+
+
+system "echo '[] set Reset 0'"
+set Reset 0
+mode run
+cycle
+
+assert b.outx[0].r 0
+assert b.outx[1].r 0
+assert b.outx[2].r 0
+
+assert b.outy[0].r 0
+assert b.outy[1].r 0
+assert b.outy[2].r 0
+assert b.outy[3].r 0
+assert b.outy[4].r 0
+
+
+system "echo '[] Neurons 0,1,3 spike'"
+set b.in[0].r 1
+set b.in[1].r 1
+set b.in[3].r 1
+cycle
+assert b.outx[0].r 0
+assert b.outx[1].r 0
+assert b.outx[2].r 0
+
+assert b.outy[0].r 1
+assert b.outy[1].r 1
+assert b.outy[2].r 0
+assert b.outy[3].r 0
+assert b.outy[4].r 0
+
+assert b.in[0].a 1
+assert b.in[1].a 1
+assert b.in[3].a 1
+
+system "echo '[] removing in reqs'"
+set b.in[0].r 0
+set b.in[1].r 0
+set b.in[3].r 0
+cycle
+assert b.in[0].a 0
+assert b.in[1].a 0
+assert b.in[3].a 0
+
+
+system "echo '[] y0 chosen, give ack'"
+set b.outy[0].a 1
+cycle
+assert b.outx[0].r 1
+assert b.outx[1].r 1
+assert b.outx[2].r 0
+
+assert b.outy[0].r 0
+assert b.outy[1].r 1
+assert b.outy[2].r 0
+assert b.outy[3].r 0
+assert b.outy[4].r 0
+
+system "echo '[] x0 chosen, give ack'"
+set b.outx[0].a 1
+cycle
+assert b.outx[0].r 0
+assert b.outx[1].r 1
+assert b.outx[2].r 0
+
+assert b.outy[0].r 0
+assert b.outy[1].r 1
+assert b.outy[2].r 0
+assert b.outy[3].r 0
+assert b.outy[4].r 0
+
+system "echo '[] remove x ack'"
+set b.outx[0].a 0
+cycle
+assert b.outx[0].r 0
+assert b.outx[1].r 1
+assert b.outx[2].r 0
+
+assert b.outy[0].r 0
+assert b.outy[1].r 1
+assert b.outy[2].r 0
+assert b.outy[3].r 0
+assert b.outy[4].r 0
+
+system "echo '[] x1 remaining, give ack'"
+set b.outx[1].a 1
+cycle
+assert b.outx[0].r 0
+assert b.outx[1].r 0
+assert b.outx[2].r 0
+
+assert b.outy[0].r 0
+assert b.outy[1].r 1
+assert b.outy[2].r 0
+assert b.outy[3].r 0
+assert b.outy[4].r 0
+
+system "echo '[] remove acks'"
+set b.outx[1].a 0
+set b.outy[0].a 0
+cycle
+assert b.outx[0].r 0
+assert b.outx[1].r 0
+assert b.outx[2].r 0
+
+assert b.outy[0].r 0
+assert b.outy[1].r 1
+assert b.outy[2].r 0
+assert b.outy[3].r 0
+assert b.outy[4].r 0
+
+system "echo '[] y1 remaining, give ack'"
+set b.outy[1].a 1
+cycle
+assert b.outx[0].r 1
+assert b.outx[1].r 0
+assert b.outx[2].r 0
+
+assert b.outy[0].r 0
+assert b.outy[1].r 0
+assert b.outy[2].r 0
+assert b.outy[3].r 0
+assert b.outy[4].r 0
+
+system "echo '[] x0 req, give ack'"
+set b.outx[0].a 1
+cycle
+assert b.outx[0].r 0
+assert b.outx[1].r 0
+assert b.outx[2].r 0
+
+assert b.outy[0].r 0
+assert b.outy[1].r 0
+assert b.outy[2].r 0
+assert b.outy[3].r 0
+assert b.outy[4].r 0
+
+
+system "echo '[] remove acks'"
+set b.outx[0].a 0
+set b.outy[1].a 0
+cycle
+assert b.outx[0].r 0
+assert b.outx[1].r 0
+assert b.outx[2].r 0
+
+assert b.outy[0].r 0
+assert b.outy[1].r 0
+assert b.outy[2].r 0
+assert b.outy[3].r 0
+assert b.outy[4].r 0
+