bics/actlib_dataflow_neuro
20
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Compare commits

base: bics:8528ee12cd3fd7d8ba9303e0f1cc46f798f3b689
Branches Tags
bics:dev
bics:main
bics:encoder_wip
bics:TexelTapeout
..
compare: bics:fb127d55f59f0b7db240bf4e7d80011fefec21f7
Branches Tags
bics:main
bics:dev
bics:encoder_wip
bics:TexelTapeout

No commits in common. "8528ee12cd3fd7d8ba9303e0f1cc46f798f3b689" and "fb127d55f59f0b7db240bf4e7d80011fefec21f7" have entirely different histories.
8528ee12cd ... fb127d55f5

3 changed files with 23 additions and 126 deletions
Show Stats Expand all files Collapse all files

43
dataflow_neuro/cell_lib_async.act
View File

@ -26,33 +26,6 @@
namespace tmpl {
namespace dataflow_neuro{
export defcell KEEP_X1 (bool y; bool vdd, vss) {
bool _y;
prs{
y => _y-
[weak=1] _y => y-
}
sizing {
leak_adjust <- 1;
p_n_mode <- 1;
y {-1}; _y{-1}
}
}
export defcell A_1C2N_RB_X1 (bool! y; bool? c1,n1,n2,pr_B, sr_B; bool vdd, vss) {
bool _y;
prs{
(~c1)|~pr_B -> _y+
c1 & n1 & n2 & sr_B -> _y-
_y => y-
}
sizing {
leak_adjust <- 1;
p_n_mode <- 1;
y {-1}; _y{-1}
}
}
export defcell A_1C1P2N_RB_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B; bool vdd, vss) {
bool _y;
prs{
@ -68,22 +41,6 @@ namespace tmpl {
}
}
export defcell A_2C1P1N_RB_X1 (bool! y; bool? c1,c2,p1,n1,pr_B,sr_B; bool vdd, vss) {
bool _y;
prs{
(~p1 & ~c1 & ~c2)|~pr_B -> _y+
c1 & c2 & n1 & sr_B -> _y-
_y => y-
}
sizing {
leak_adjust <- 1;
p_n_mode <- 1;
y {-1}; _y{-1}
}
}
export defcell A_1C1P2N_R_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B; bool vdd, vss) {
prs{
(~p1 & ~c1)|~pr_B -> y-

81
dataflow_neuro/coders.act
View File

@ -477,35 +477,35 @@ namespace tmpl {
/**
* Neuron handshaking.
* Looks for a rising edge on the neuron req.
* Then performs a 2d handshake out outy then outx.
* Then performs a 2d handshake out out_y then out_x.
*/
export
defproc neuron_hs_2D(a1of1 in; a1of1 outx; a1of1 outy; power supply; bool reset_B) {
defproc neuron_hs_2D(a1of1 in; a1of1 out_x; a1of1 out_y; power supply; bool reset_B) {
bool _reset_BX;
BUF_X2 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
bool _en, _req;
A_1C2N_RB_X1 A_ack(.c1 = _en, .n1 = _req, .n2 = in.r, .y = in.a,
.pr_B = _reset_BX, .sr_B = _reset_BX, .vss = supply.vss, .vdd = supply.vdd);
.sr_B = _reset_BX, .sr_B = _reset_BX, .vss = supply.vss, .vdd = supply.vdd);
A_1C1P_X1 A_en(.p1 = _req, .c1 = in.a, .y = _en,
.vss = supply.vss, .vdd = supply.vdd);
bool _y_a_B, _x_a_B;
INV_X2 inv_x(.a = outx.a, .y = _x_a_B, .vss = supply.vss, .vdd = supply.vdd);
INV_X2 inv_y(.a = outy.a, .y = _y_a_B, .vss = supply.vss, .vdd = supply.vdd);
INV_X2 inv_x(.a = out_x.a, .y = _x_a_B, .vss = supply.vss, .vdd = supply.vdd);
INV_X2 inv_y(.a = out_y.a, .y = _y_a_B, .vss = supply.vss, .vdd = supply.vdd);
A_2C1P1N_RB_X1 A_req(.p1 = _x_a_B, .c1 = _en, .c2 = _y_a_B, .n1 = in.r, .y = _req,
.pr_B = _reset_BX, .sr_B = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
A_2C1P1N_RB_X1 A_req(.p1 = _x_a_B, .c1 = _en, .c2 = _y_a_B, .n1 = in.r,
.sr_B = _reset_BX, .sr_B = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
// y_req pull up
NAND2_X1 nand_y(.a = _y_a_B, .b = _req, .vdd = supply.vdd, .vss = supply.vss);
PULLUP_X4 pu_y(.a = nand_y.y, .y = outy.r, .vdd = supply.vdd, .vss = supply.vss);
PULLUP_X4 pu_y(.a = nand_y.y, .y = out_y.r, .vdd = supply.vdd, .vss = supply.vss);
// x_req pull up
NAND3_X1 nand_x(.a = _x_a_B, .b = _req, .c = outy.a, .vdd = supply.vdd, .vss = supply.vss);
PULLUP_X4 pu_x(.a = nand_x.y, .y = outx.r, .vdd = supply.vdd, .vss = supply.vss);
NAND3_X1 nand_x(.a = _x_a_B, .b = _req, .c = out_y.a, .vdd = supply.vdd, .vss = supply.vss);
PULLUP_X4 pu_x(.a = nand_x.y, .y = out_x.r, .vdd = supply.vdd, .vss = supply.vss);
}
@ -513,14 +513,14 @@ namespace tmpl {
export
defproc line_end_pull_down (bool? in; bool? reset_B; power supply; bool! out)
{
bool _out, __out, nand_out;
bool _out, __out, nor_out;
BUF_X1 buf1(.a=in, .y=_out, .vdd=supply.vdd,.vss=supply.vss);
BUF_X1 buf2(.a=_out, .y=__out, .vdd=supply.vdd,.vss=supply.vss);
INV_X1 inv(.a = __out, .vdd=supply.vdd,.vss =supply.vss);
NAND2_X1 aenor(.a=inv.y, .b=reset_B, .y = nand_out, .vdd=supply.vdd,.vss=supply.vss);
NAND2_X1 aenor(.a=inv.y, .b=reset_B, .y = nor_out, .vdd=supply.vdd,.vss=supply.vss);
PULLDOWN_X4 pull_down(.a=nand_out, .y=out);
PULLDOWN_X4 pull_down(.a=nor_out, .y=out);
}
@ -529,12 +529,9 @@ namespace tmpl {
* A 2d grid of neuron handshakers.
* Should then slot into the encoder.
* Each neuron has an a1of1 channel (in), which is tripped when a neuron spikes.
* N_dly is number of delay elements to add to line pull down,
* for the purpose of running ACT sims.
* It should probably be set to 0 though.
*/
export template<pint Nx, Ny, N_dly>
defproc nrn_hs_2D_array(a1of1 in[Nx*Ny]; a1of1 outx[Nx], outy[Ny];
export template<pint Nx, Ny>
defproc neuron_hs_2D_array(a1of1 in[Nx*Ny]; a1of1 out_x[Nx], out_y[Ny];
power supply; bool reset_B) {
// Make hella signal buffers
@ -545,7 +542,6 @@ namespace tmpl {
rsb[j].supply = supply;
)
// Create handshake grid
pint index;
neuron_hs_2D neurons[Nx*Ny];
@ -555,63 +551,32 @@ namespace tmpl {
neurons[index].supply = supply;
neurons[index].reset_B = rsb[j].out[i];
neurons[index].in = in[index];
neurons[index].outx = outx[i];
neurons[index].outy = outy[j];
neurons[index].out_x = out_x[i];
neurons[index].out_y = out_y[j];
)
)
// Hacks to maybe construct some fifos, ignore.
[N_dly >= 1 ->
delay_fifo<N_dly> dly_x[Nx];
delay_fifo<N_dly> dly_y[Ny];
]
// Create x line req pull downs
// Create line req pull downs
line_end_pull_down pd_x[Nx];
sigbuf<Nx> rsb_pd_x(.in = reset_B, .supply = supply);
(i:0..Nx-1:
[ N_dly = 0 ->
pd_x[i].in = outx[i].a;
[] N_dly >= 1 ->
dly_x[i].supply = supply;
dly_x[i].in = outx[i].a;
pd_x[i].in = dly_x[i].out;
]
pd_x[i].out = outx[i].r;
pd_x[i].in = out_x[i].a;
pd_x[i].out = out_x[i].r;
pd_x[i].reset_B = rsb_pd_x.out[i];
pd_x[i].supply = supply;
)
// Create y line req pull downs
// Create line req pull downs
line_end_pull_down pd_y[Ny];
sigbuf<Ny> rsb_pd_y(.in = reset_B, .supply = supply);
(j:0..Ny-1:
[ N_dly = 0 ->
pd_y[j].in = outy[j].a;
[] N_dly >= 1 ->
dly_y[j].supply = supply;
dly_y[j].in = outy[j].a;
pd_y[j].in = dly_y[j].out;
]
pd_y[j].out = outy[j].r;
pd_y[j].in = out_y[j].a;
pd_y[j].out = out_y[j].r;
pd_y[j].reset_B = rsb_pd_y.out[j];
pd_y[j].supply = supply;
)
// Add keeps
KEEP_X1 keep_x[Nx];
(i:Nx:
keep_x[i].vdd = supply.vdd;
keep_x[i].vss = supply.vss;
keep_x[i].y = outx[i].r;
)
KEEP_X1 keep_y[Ny];
(j:Ny:
keep_y[j].vdd = supply.vdd;
keep_y[j].vss = supply.vss;
keep_y[j].y = outy[j].r;
)
}

25
dataflow_neuro/primitives.act
View File

@ -685,31 +685,6 @@ namespace tmpl {
(i:((1<<N)-1):dly[i].vss = supply.vss;)
}
// Non programmable delays
// N is number of delays to have in series (not log!!).
// Is useful for testing purposes.
// But should probably remove before running innovus etc.
export template<pint N>
defproc delay_fifo (bool! out; bool? in; power supply) {
{ N >= 0 : "What?" };
DLY4_X1 dly[N];
dly[0].vdd = supply.vdd;
dly[0].vss = supply.vss;
dly[0].a = in;
(i:1..N-1:
dly[i].vdd = supply.vdd;
dly[i].vss = supply.vss;
dly[i].a = dly[i-1].y;
)
dly[N-1].vdd = supply.vdd;
dly[N-1].vss = supply.vss;
dly[N-1].y = out;
}
/**
* Appends a hard-coded word "VAL" to an input.
* Works by piping through all sigs, but adding