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No commits in common. "8528ee12cd3fd7d8ba9303e0f1cc46f798f3b689" and "fb127d55f59f0b7db240bf4e7d80011fefec21f7" have entirely different histories.
8528ee12cd
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fb127d55f5
@ -26,33 +26,6 @@
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namespace tmpl {
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namespace tmpl {
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namespace dataflow_neuro{
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namespace dataflow_neuro{
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export defcell KEEP_X1 (bool y; bool vdd, vss) {
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bool _y;
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prs{
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y => _y-
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[weak=1] _y => y-
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}
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sizing {
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leak_adjust <- 1;
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p_n_mode <- 1;
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y {-1}; _y{-1}
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}
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}
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export defcell A_1C2N_RB_X1 (bool! y; bool? c1,n1,n2,pr_B, sr_B; bool vdd, vss) {
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bool _y;
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prs{
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(~c1)|~pr_B -> _y+
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c1 & n1 & n2 & sr_B -> _y-
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_y => y-
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}
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sizing {
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leak_adjust <- 1;
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p_n_mode <- 1;
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y {-1}; _y{-1}
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}
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}
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export defcell A_1C1P2N_RB_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B; bool vdd, vss) {
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export defcell A_1C1P2N_RB_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B; bool vdd, vss) {
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bool _y;
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bool _y;
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prs{
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prs{
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@ -68,22 +41,6 @@ namespace tmpl {
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}
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}
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}
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}
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export defcell A_2C1P1N_RB_X1 (bool! y; bool? c1,c2,p1,n1,pr_B,sr_B; bool vdd, vss) {
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bool _y;
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prs{
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(~p1 & ~c1 & ~c2)|~pr_B -> _y+
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c1 & c2 & n1 & sr_B -> _y-
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_y => y-
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}
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sizing {
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leak_adjust <- 1;
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p_n_mode <- 1;
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y {-1}; _y{-1}
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}
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}
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export defcell A_1C1P2N_R_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B; bool vdd, vss) {
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export defcell A_1C1P2N_R_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B; bool vdd, vss) {
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prs{
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prs{
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(~p1 & ~c1)|~pr_B -> y-
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(~p1 & ~c1)|~pr_B -> y-
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@ -477,35 +477,35 @@ namespace tmpl {
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/**
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/**
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* Neuron handshaking.
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* Neuron handshaking.
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* Looks for a rising edge on the neuron req.
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* Looks for a rising edge on the neuron req.
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* Then performs a 2d handshake out outy then outx.
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* Then performs a 2d handshake out out_y then out_x.
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*/
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*/
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export
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export
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defproc neuron_hs_2D(a1of1 in; a1of1 outx; a1of1 outy; power supply; bool reset_B) {
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defproc neuron_hs_2D(a1of1 in; a1of1 out_x; a1of1 out_y; power supply; bool reset_B) {
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bool _reset_BX;
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bool _reset_BX;
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BUF_X2 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
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BUF_X2 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
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bool _en, _req;
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bool _en, _req;
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A_1C2N_RB_X1 A_ack(.c1 = _en, .n1 = _req, .n2 = in.r, .y = in.a,
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A_1C2N_RB_X1 A_ack(.c1 = _en, .n1 = _req, .n2 = in.r, .y = in.a,
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.pr_B = _reset_BX, .sr_B = _reset_BX, .vss = supply.vss, .vdd = supply.vdd);
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.sr_B = _reset_BX, .sr_B = _reset_BX, .vss = supply.vss, .vdd = supply.vdd);
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A_1C1P_X1 A_en(.p1 = _req, .c1 = in.a, .y = _en,
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A_1C1P_X1 A_en(.p1 = _req, .c1 = in.a, .y = _en,
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.vss = supply.vss, .vdd = supply.vdd);
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.vss = supply.vss, .vdd = supply.vdd);
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bool _y_a_B, _x_a_B;
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bool _y_a_B, _x_a_B;
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INV_X2 inv_x(.a = outx.a, .y = _x_a_B, .vss = supply.vss, .vdd = supply.vdd);
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INV_X2 inv_x(.a = out_x.a, .y = _x_a_B, .vss = supply.vss, .vdd = supply.vdd);
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INV_X2 inv_y(.a = outy.a, .y = _y_a_B, .vss = supply.vss, .vdd = supply.vdd);
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INV_X2 inv_y(.a = out_y.a, .y = _y_a_B, .vss = supply.vss, .vdd = supply.vdd);
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A_2C1P1N_RB_X1 A_req(.p1 = _x_a_B, .c1 = _en, .c2 = _y_a_B, .n1 = in.r, .y = _req,
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A_2C1P1N_RB_X1 A_req(.p1 = _x_a_B, .c1 = _en, .c2 = _y_a_B, .n1 = in.r,
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.pr_B = _reset_BX, .sr_B = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
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.sr_B = _reset_BX, .sr_B = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
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// y_req pull up
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// y_req pull up
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NAND2_X1 nand_y(.a = _y_a_B, .b = _req, .vdd = supply.vdd, .vss = supply.vss);
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NAND2_X1 nand_y(.a = _y_a_B, .b = _req, .vdd = supply.vdd, .vss = supply.vss);
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PULLUP_X4 pu_y(.a = nand_y.y, .y = outy.r, .vdd = supply.vdd, .vss = supply.vss);
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PULLUP_X4 pu_y(.a = nand_y.y, .y = out_y.r, .vdd = supply.vdd, .vss = supply.vss);
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// x_req pull up
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// x_req pull up
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NAND3_X1 nand_x(.a = _x_a_B, .b = _req, .c = outy.a, .vdd = supply.vdd, .vss = supply.vss);
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NAND3_X1 nand_x(.a = _x_a_B, .b = _req, .c = out_y.a, .vdd = supply.vdd, .vss = supply.vss);
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PULLUP_X4 pu_x(.a = nand_x.y, .y = outx.r, .vdd = supply.vdd, .vss = supply.vss);
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PULLUP_X4 pu_x(.a = nand_x.y, .y = out_x.r, .vdd = supply.vdd, .vss = supply.vss);
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}
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}
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@ -513,14 +513,14 @@ namespace tmpl {
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export
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export
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defproc line_end_pull_down (bool? in; bool? reset_B; power supply; bool! out)
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defproc line_end_pull_down (bool? in; bool? reset_B; power supply; bool! out)
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{
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{
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bool _out, __out, nand_out;
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bool _out, __out, nor_out;
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BUF_X1 buf1(.a=in, .y=_out, .vdd=supply.vdd,.vss=supply.vss);
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BUF_X1 buf1(.a=in, .y=_out, .vdd=supply.vdd,.vss=supply.vss);
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BUF_X1 buf2(.a=_out, .y=__out, .vdd=supply.vdd,.vss=supply.vss);
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BUF_X1 buf2(.a=_out, .y=__out, .vdd=supply.vdd,.vss=supply.vss);
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INV_X1 inv(.a = __out, .vdd=supply.vdd,.vss =supply.vss);
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INV_X1 inv(.a = __out, .vdd=supply.vdd,.vss =supply.vss);
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NAND2_X1 aenor(.a=inv.y, .b=reset_B, .y = nand_out, .vdd=supply.vdd,.vss=supply.vss);
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NAND2_X1 aenor(.a=inv.y, .b=reset_B, .y = nor_out, .vdd=supply.vdd,.vss=supply.vss);
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PULLDOWN_X4 pull_down(.a=nand_out, .y=out);
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PULLDOWN_X4 pull_down(.a=nor_out, .y=out);
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}
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}
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@ -529,12 +529,9 @@ namespace tmpl {
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* A 2d grid of neuron handshakers.
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* A 2d grid of neuron handshakers.
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* Should then slot into the encoder.
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* Should then slot into the encoder.
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* Each neuron has an a1of1 channel (in), which is tripped when a neuron spikes.
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* Each neuron has an a1of1 channel (in), which is tripped when a neuron spikes.
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* N_dly is number of delay elements to add to line pull down,
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* for the purpose of running ACT sims.
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* It should probably be set to 0 though.
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*/
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*/
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export template<pint Nx, Ny, N_dly>
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export template<pint Nx, Ny>
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defproc nrn_hs_2D_array(a1of1 in[Nx*Ny]; a1of1 outx[Nx], outy[Ny];
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defproc neuron_hs_2D_array(a1of1 in[Nx*Ny]; a1of1 out_x[Nx], out_y[Ny];
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power supply; bool reset_B) {
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power supply; bool reset_B) {
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// Make hella signal buffers
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// Make hella signal buffers
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@ -545,7 +542,6 @@ namespace tmpl {
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rsb[j].supply = supply;
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rsb[j].supply = supply;
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)
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)
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// Create handshake grid
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// Create handshake grid
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pint index;
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pint index;
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neuron_hs_2D neurons[Nx*Ny];
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neuron_hs_2D neurons[Nx*Ny];
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@ -555,63 +551,32 @@ namespace tmpl {
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neurons[index].supply = supply;
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neurons[index].supply = supply;
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neurons[index].reset_B = rsb[j].out[i];
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neurons[index].reset_B = rsb[j].out[i];
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neurons[index].in = in[index];
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neurons[index].in = in[index];
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neurons[index].outx = outx[i];
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neurons[index].out_x = out_x[i];
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neurons[index].outy = outy[j];
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neurons[index].out_y = out_y[j];
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)
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)
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)
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)
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// Hacks to maybe construct some fifos, ignore.
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// Create line req pull downs
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[N_dly >= 1 ->
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delay_fifo<N_dly> dly_x[Nx];
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delay_fifo<N_dly> dly_y[Ny];
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]
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// Create x line req pull downs
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line_end_pull_down pd_x[Nx];
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line_end_pull_down pd_x[Nx];
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sigbuf<Nx> rsb_pd_x(.in = reset_B, .supply = supply);
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sigbuf<Nx> rsb_pd_x(.in = reset_B, .supply = supply);
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(i:0..Nx-1:
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(i:0..Nx-1:
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[ N_dly = 0 ->
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pd_x[i].in = out_x[i].a;
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pd_x[i].in = outx[i].a;
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pd_x[i].out = out_x[i].r;
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[] N_dly >= 1 ->
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dly_x[i].supply = supply;
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dly_x[i].in = outx[i].a;
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pd_x[i].in = dly_x[i].out;
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]
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pd_x[i].out = outx[i].r;
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pd_x[i].reset_B = rsb_pd_x.out[i];
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pd_x[i].reset_B = rsb_pd_x.out[i];
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pd_x[i].supply = supply;
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pd_x[i].supply = supply;
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)
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)
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// Create y line req pull downs
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// Create line req pull downs
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line_end_pull_down pd_y[Ny];
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line_end_pull_down pd_y[Ny];
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sigbuf<Ny> rsb_pd_y(.in = reset_B, .supply = supply);
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sigbuf<Ny> rsb_pd_y(.in = reset_B, .supply = supply);
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(j:0..Ny-1:
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(j:0..Ny-1:
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[ N_dly = 0 ->
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pd_y[j].in = out_y[j].a;
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pd_y[j].in = outy[j].a;
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pd_y[j].out = out_y[j].r;
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[] N_dly >= 1 ->
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dly_y[j].supply = supply;
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dly_y[j].in = outy[j].a;
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pd_y[j].in = dly_y[j].out;
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]
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pd_y[j].out = outy[j].r;
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pd_y[j].reset_B = rsb_pd_y.out[j];
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pd_y[j].reset_B = rsb_pd_y.out[j];
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pd_y[j].supply = supply;
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pd_y[j].supply = supply;
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)
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)
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// Add keeps
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KEEP_X1 keep_x[Nx];
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(i:Nx:
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keep_x[i].vdd = supply.vdd;
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keep_x[i].vss = supply.vss;
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keep_x[i].y = outx[i].r;
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)
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KEEP_X1 keep_y[Ny];
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(j:Ny:
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keep_y[j].vdd = supply.vdd;
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keep_y[j].vss = supply.vss;
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keep_y[j].y = outy[j].r;
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)
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}
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}
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@ -685,31 +685,6 @@ namespace tmpl {
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(i:((1<<N)-1):dly[i].vss = supply.vss;)
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(i:((1<<N)-1):dly[i].vss = supply.vss;)
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}
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}
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// Non programmable delays
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// N is number of delays to have in series (not log!!).
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// Is useful for testing purposes.
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// But should probably remove before running innovus etc.
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export template<pint N>
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defproc delay_fifo (bool! out; bool? in; power supply) {
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{ N >= 0 : "What?" };
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DLY4_X1 dly[N];
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dly[0].vdd = supply.vdd;
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dly[0].vss = supply.vss;
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dly[0].a = in;
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(i:1..N-1:
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dly[i].vdd = supply.vdd;
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dly[i].vss = supply.vss;
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dly[i].a = dly[i-1].y;
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)
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dly[N-1].vdd = supply.vdd;
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dly[N-1].vss = supply.vss;
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dly[N-1].y = out;
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}
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/**
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/**
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* Appends a hard-coded word "VAL" to an input.
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* Appends a hard-coded word "VAL" to an input.
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* Works by piping through all sigs, but adding
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* Works by piping through all sigs, but adding
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Reference in New Issue
Block a user