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5e4e905960
@ -604,20 +604,23 @@ namespace tmpl {
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)
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)
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// Create delay fifos to emulate the fact that the line pull downs
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// are at the end of the line, and thus slow.
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// Note that if N_dly = 0, delay fifo is just a pipe.
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// Hacks to maybe construct some fifos, ignore.
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[N_dly >= 1 ->
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delay_fifo<N_dly> dly_x[Nx];
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delay_fifo<N_dly> dly_y[Ny];
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]
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// Create x line req pull downs
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line_end_pull_down pd_x[Nx];
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sigbuf<Nx> rsb_pd_x(.in = reset_B, .supply = supply);
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(i:0..Nx-1:
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[ N_dly = 0 ->
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pd_x[i].in = _outx[i].a;
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[] N_dly >= 1 ->
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dly_x[i].supply = supply;
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dly_x[i].in = _outx[i].a;
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pd_x[i].in = dly_x[i].out;
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]
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pd_x[i].out = _outx[i].r;
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pd_x[i].reset_B = rsb_pd_x.out[i];
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pd_x[i].supply = supply;
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@ -627,10 +630,13 @@ namespace tmpl {
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line_end_pull_down pd_y[Ny];
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sigbuf<Ny> rsb_pd_y(.in = reset_B, .supply = supply);
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(j:0..Ny-1:
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[ N_dly = 0 ->
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pd_y[j].in = _outy[j].a;
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[] N_dly >= 1 ->
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dly_y[j].supply = supply;
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dly_y[j].in = _outy[j].a;
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pd_y[j].in = dly_y[j].out;
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]
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pd_y[j].out = _outy[j].r;
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pd_y[j].reset_B = rsb_pd_y.out[j];
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pd_y[j].supply = supply;
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@ -690,9 +690,8 @@ namespace tmpl {
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// Is useful for testing purposes.
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// But should probably remove before running innovus etc.
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export template<pint N>
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defproc delay_fifo (bool out; bool in; power supply) {
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defproc delay_fifo (bool! out; bool? in; power supply) {
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{ N >= 0 : "What?" };
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[N >= 1 ->
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DLY4_X1 dly[N];
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dly[0].vdd = supply.vdd;
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@ -708,10 +707,6 @@ namespace tmpl {
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dly[N-1].vdd = supply.vdd;
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dly[N-1].vss = supply.vss;
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dly[N-1].y = out;
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[] N = 1 ->
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in = out;
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]
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}
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@ -1,99 +0,0 @@
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/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library.
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* It's the testing facility for cell_lib_std.act
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/coders.act";
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import "../../dataflow_neuro/primitives.act";
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import globals;
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import std::data;
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open std::data;
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open tmpl::dataflow_neuro;
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defproc fifo_decoder_neurons_encoder_fifo (avMx1of2<7> in; avMx1of2<7> out; bool? dly_cfg[6]){
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bool _reset_B;
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prs {
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Reset => _reset_B-
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}
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power supply;
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supply.vdd = Vdd;
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supply.vss = GND;
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pint NxC,NyC,Nx,Ny;
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NxC = 4;
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NyC = 3;
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Nx = 1<<NxC;
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Ny = 1<<NyC;
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fifo<NxC + NyC,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);
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decoder_2d_dly<NxC,NyC,Nx,Ny,6> decoder(.in = fifo_pre.out, .dly_cfg = dly_cfg,
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.reset_B = _reset_B, .supply = supply);
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and_grid<Nx, Ny> _and_grid(.inx = decoder.outx, .iny = decoder.outy, .supply = supply);
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// Pretend that each "synapse" immediately makes its one neuron "spike".
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// that is, connect the output of each encoder target to the decoder input.
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nrn_hs_2D_array<Nx,Ny,16> neuron_grid(.reset_B = _reset_B, .supply = supply);
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(i:Nx*Ny:
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// Connect the output bool to the input req of each neuron handshaker
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// Leave ack dangling.
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neuron_grid.in[i].r = _and_grid.out[i];
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)
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encoder2D<NxC,NyC,Nx,Ny,4> encoder(.x = neuron_grid.outx, .y = neuron_grid.outy,
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.reset_B = _reset_B, .supply = supply);
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fifo<NxC + NyC,5> fifo_post(.in = encoder.out, .out = out, .reset_B = _reset_B, .supply = supply);
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}
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// defproc fifo_decoder_and (avMx1of2<7> in; bool! out[8*16]; bool? dly_cfg[6]){
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// bool _reset_B;
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// prs {
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// Reset => _reset_B-
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// }
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// power supply;
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// supply.vdd = Vdd;
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// supply.vss = GND;
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// pint NxC,NyC,Nx,Ny;
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// NxC = 4;
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// NyC = 3;
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// Nx = 1<<NxC;
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// Ny = 1<<NyC;
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// fifo<NxC + NyC,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);
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// decoder_2d_dly<NxC,NyC,Nx,Ny,6> decoder(.in = fifo_pre.out, .dly_cfg = dly_cfg,
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// .reset_B = _reset_B, .supply = supply);
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// and_grid<Nx, Ny> _and_grid(.inx = decoder.outx, .iny = decoder.outy, .out = out, .supply = supply);
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// nrn_hs_2D_array<Nx,Ny,16> nrn_array(.reset_B = _reset_B, .supply = supply);
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// }
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// fifo_decoder_neurons_encoder_fifo e;
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fifo_decoder_neurons_encoder_fifo e;
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@ -1,81 +0,0 @@
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watchall
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set e.out.a 0
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set e.out.v 0
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set-qdi-channel-neutral "e.in" 7
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set Reset 1
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set e.dly_cfg[0] 1
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set e.dly_cfg[1] 1
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set e.dly_cfg[2] 1
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set e.dly_cfg[3] 1
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set e.dly_cfg[4] 1
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set e.dly_cfg[5] 1
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cycle
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mode run
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system "echo '[] Set reset 0'"
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status X
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set Reset 0
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cycle
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system "echo '[] Sending in a packet'"
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set-qdi-channel-valid "e.in" 7 75
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cycle
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assert-qdi-channel-valid "e.out" 7 75
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assert e.in.a 1
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assert e.in.v 1
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "e.in" 7
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cycle
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assert e.in.a 0
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assert e.in.v 0
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system "echo '[] Sending in another packet'"
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set-qdi-channel-valid "e.in" 7 22
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cycle
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# Output is still the first packet
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assert-qdi-channel-valid "e.out" 7 75
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assert e.in.a 1
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assert e.in.v 1
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "e.in" 7
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cycle
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assert e.in.a 0
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assert e.in.v 0
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system "echo '[] Giving out ack'"
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set e.out.a 1
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set e.out.v 1
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cycle
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assert-qdi-channel-neutral "e.out" 7
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system "echo '[] Removing ack'"
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set e.out.a 0
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set e.out.v 0
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cycle
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assert-qdi-channel-valid "e.out" 7 22
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system "echo '[] Giving out ack'"
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set e.out.a 1
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set e.out.v 1
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cycle
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assert-qdi-channel-neutral "e.out" 7
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system "echo '[] Removing ack'"
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set e.out.a 0
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set e.out.v 0
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cycle
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assert-qdi-channel-neutral "e.out" 7
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