replaced Pullup/downs with A cell naming scheme

dataflow_neuro/cell_lib_async.act

@@ -565,7 +565,7 @@ namespace tmpl {
           }
         }
         export
-        defproc PULLDOWN_X4(bool? a; bool! y; bool? vdd, vss)
+        defproc A_1N_U_X4(bool? a; bool! y; bool? vdd, vss)
         {
         prs{
         [keeper=0] a -> y-
@@ -573,7 +573,7 @@ namespace tmpl {
         }
 
         export
-        defproc PULLDOWN2_X4(bool? a, b; bool! y; bool? vdd, vss)
+        defproc A_2N_U_X4(bool? a, b; bool! y; bool? vdd, vss)
         {
         prs{
         [keeper=0] a & b -> y-
@@ -581,7 +581,7 @@ namespace tmpl {
         }
         
         export
-        defproc PULLUP_X4(bool? a; bool! y; bool? vdd, vss)
+        defproc A_1P_U_X4(bool? a; bool! y; bool? vdd, vss)
         {
         prs{
         [keeper=0] ~a -> y+

dataflow_neuro/coders.act

@@ -202,7 +202,7 @@ defproc decoder_2d_hs (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? reset_B; po
 
 	// Pull DOWNs on the ackB lines by synapses (easier to invert).
 	bool _out_acksB[Nx]; // The vertical output ack lines from each syn.
-	PULLDOWN2_X4 ack_pulldowns[Nx*Ny];
+	A_2N_U_X4 ack_pulldowns[Nx*Ny];
 	pint index;
 	(i:Nx:
 		(j:Ny:
@@ -216,15 +216,13 @@ defproc decoder_2d_hs (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? reset_B; po
 	)
 
 	// Line end pull UPs (triggered once reqs removed)
-	PULLUP_X4 pu[Nx]; // TODO probably replace this with variable strength PU
-	PULLUP_X4 pu_reset[Nx]; // TODO probably replace this with variable strength PU
-	// AND2_X1 pu_ANDs[Nx];
+	// Use two pullups rather than and-pullup 
+	// bc smaller
+	// and bc the delay that an AND induces means that the pullup could
+	// end up fighting a synapse pulldown, as both have the correct req sigs.
+	A_1P_U_X4 pu[Nx]; // TODO probably replace this with variable strength PU
+	A_1P_U_X4 pu_reset[Nx];
 	(i:Nx:
-		// pu_ANDs[i].a = d_dr_xX[i].out[Ny];
-		// pu_ANDs[i].b = reset_B; // TODO buffer
-		// pu_ANDs[i].vdd = supply.vdd;
-		// pu_ANDs[i].vss = supply.vss;
-
 		pu[i].a = d_dr_xX[i].out[Ny];
 		pu[i].y = _out_acksB[i];
 		pu[i].vdd = supply.vdd;
@@ -258,6 +256,118 @@ defproc decoder_2d_hs (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? reset_B; po
 
 }
 
+/**
+ * 2D decoder which uses either synapse handshaking, or just a delay.
+ * Controlled by the "hs_en" (handshake_enable) config bit.
+ * hs_en = 0 -> use delayed version.
+ * hs_en = 1 -> use synapse handshaking.
+ * Regardless of which version is used, the final ack going to the buffer
+ * goes through the prog_delay block.
+ * Thus, for the handshaking version to be used "correctly", 
+ * dly_cfg should be set to all zeros.
+ */
+export template<pint NxC, NyC, Nx, Ny, N_dly_cfg>
+defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg[N_dly_cfg], hs_en,
+	reset_B; power supply) {
+
+	// Buffer to recieve concat(x,y) address packet
+	buffer<NxC+NyC> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
+
+	// Decoder X/Y And trees
+	decoder_dualrail<NxC,Nx> d_dr_x(.supply = supply);
+	(i:0..NxC-1:d_dr_x.in.d[i] = addr_buf.out.d.d[i];)
+	decoder_dualrail<NyC,Ny> d_dr_y(.supply = supply);
+	(i:0..NyC-1:d_dr_y.in.d[i] = addr_buf.out.d.d[i+NxC];)
+
+	// sig buf for reqx lines, since they go to synapse pull down gates.
+	sigbuf<Ny+1> d_dr_xX[Nx];
+	(i:Nx:
+		d_dr_xX[i].in = d_dr_x.out[i];
+		d_dr_xX[i].supply = supply;
+	)
+
+	// Validity 
+	vtree<NxC> vtree_x (.supply = supply);
+	vtree<NyC> vtree_y (.supply = supply);
+	(i:0..NxC-1:vtree_x.in.d[i].t = addr_buf.out.d.d[i].t;)
+	(i:0..NxC-1:vtree_x.in.d[i].f = addr_buf.out.d.d[i].f;)
+	(i:0..NyC-1:vtree_y.in.d[i].t = addr_buf.out.d.d[i+NxC].t;)
+	(i:0..NyC-1:vtree_y.in.d[i].f = addr_buf.out.d.d[i+NxC].f;)
+	A_2C_B_X1 valid_Cel(.c1 = vtree_x.out, .c2 = vtree_y.out, .y = addr_buf.out.v,
+		.vdd = supply.vdd, .vss = supply.vss);
+
+
+	// and grid for reqs into synapses
+	and_grid<Nx, Ny> _and_grid(.inx = d_dr_x.out, .iny = d_dr_y.out, .supply = supply);
+	(i:Nx*Ny: out[i].r = _and_grid.out[i];)
+
+	// Acknowledge pull down time
+
+	// Pull DOWNs on the ackB lines by synapses (easier to invert).
+	bool _out_acksB[Nx]; // The vertical output ack lines from each syn.
+	A_2N_U_X4 ack_pulldowns[Nx*Ny];
+	pint index;
+	(i:Nx:
+		(j:Ny:
+			index = i + Nx*j;
+			ack_pulldowns[index].a = out[index].a;
+			ack_pulldowns[index].b = d_dr_xX[i].out[j];
+			ack_pulldowns[index].y = _out_acksB[i];
+			ack_pulldowns[index].vss = supply.vss;
+			ack_pulldowns[index].vdd = supply.vdd;
+		)
+	)
+
+	// Line end pull UPs (triggered once reqs removed)
+	// Use two pullups rather than and-pullup 
+	// bc smaller
+	// and bc the delay that an AND induces means that the pullup could
+	// end up fighting a synapse pulldown, as both have the correct req sigs.
+	A_1P_U_X4 pu[Nx]; // TODO probably replace this with variable strength PU
+	A_1P_U_X4 pu_reset[Nx];
+	(i:Nx:
+		pu[i].a = d_dr_xX[i].out[Ny];
+		pu[i].y = _out_acksB[i];
+		pu[i].vdd = supply.vdd;
+		pu[i].vss = supply.vss;
+
+		pu_reset[i].a = reset_B;
+		pu_reset[i].y = _out_acksB[i];
+		pu_reset[i].vdd = supply.vdd;
+		pu_reset[i].vss = supply.vss;
+	)
+
+	// ORtree from all output acks, back to the buffer ack.
+	// This is instead of the ack that came from the delayed validity trees,
+	// in decoder_2d_dly.
+	ortree<Nx>  _ortree(.supply = supply);
+	INV_X1 out_ack_invs[Nx];
+	(i:Nx:
+		out_ack_invs[i].a = _out_acksB[i];
+		out_ack_invs[i].vdd = supply.vdd;
+		out_ack_invs[i].vss = supply.vss;
+
+		_ortree.in[i] = out_ack_invs[i].y;
+	)
+
+	// C element to ensure that the buffer receives an invalid
+	// _only_ once _both_ ackB has been reset, _and_ its output data
+	// has been fully invalidated.
+	// Otherwise run into the issue that ack is removed before data is invalid.
+	A_2C_B_X1 buf_ack_Cel(.c1 = _ortree.out, .c2 = valid_Cel.y, .y = addr_buf.out.a,
+		.vdd = supply.vdd, .vss = supply.vss);
+
+	
+
+
+	// Programmable delay
+	delayprog<N_dly_cfg> dly(.s = dly_cfg, .supply = supply);
+	dly.out = addr_buf.out.a;
+
+
+
+}
+
 
 
 /*
@@ -628,11 +738,11 @@ defproc decoder_2d_hs (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? reset_B; po
 
 			// y_req pull up
 			NAND2_X1 nand_y(.a = _y_a_B, .b = _req, .vdd = supply.vdd, .vss = supply.vss);
-			PULLUP_X4 pu_y(.a = nand_y.y, .y = outy.r, .vdd = supply.vdd, .vss = supply.vss);
+			A_1P_U_X4 pu_y(.a = nand_y.y, .y = outy.r, .vdd = supply.vdd, .vss = supply.vss);
 
 			// x_req pull up
 			NAND3_X1 nand_x(.a = _x_a_B, .b = _req, .c = outy.a, .vdd = supply.vdd, .vss = supply.vss);
-			PULLUP_X4 pu_x(.a = nand_x.y, .y = outx.r, .vdd = supply.vdd, .vss = supply.vss);
+			A_1P_U_X4 pu_x(.a = nand_x.y, .y = outx.r, .vdd = supply.vdd, .vss = supply.vss);
 		}
 
 
@@ -647,7 +757,7 @@ defproc decoder_2d_hs (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? reset_B; po
 
       NAND2_X1 aenor(.a=inv.y, .b=reset_B, .y = nand_out, .vdd=supply.vdd,.vss=supply.vss);
 
-      PULLDOWN_X4 pull_down(.a=nand_out, .y=out);
+      A_1N_U_X4 pull_down(.a=nand_out, .y=out);
     }
 
 

test/unit_tests/fifo-decoder_hs-neurons-encoder-fifo/test.act

@@ -0,0 +1,72 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/primitives.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+open tmpl::dataflow_neuro;
+
+defproc fifo_decoder_neurons_encoder_fifo (avMx1of2<7> in; avMx1of2<7> out){
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    pint NxC,NyC,Nx,Ny;
+    NxC = 4;
+    NyC = 3;
+    Nx = 1<<NxC;
+    Ny = 1<<NyC;
+
+    fifo<NxC + NyC,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);
+    decoder_2d_hs<NxC,NyC,Nx,Ny> decoder(.in = fifo_pre.out, .reset_B = _reset_B, .supply = supply);
+    // Pretend that each "synapse" immediately makes its one neuron "spike".
+    // that is, connect the output of each encoder target to the decoder input.
+    nrn_hs_2D_array<Nx,Ny,10> neuron_grid(.reset_B = _reset_B, .supply = supply);
+    (i:Nx*Ny:
+        neuron_grid.in[i].r = decoder.out[i].r;
+        neuron_grid.in[i].a = decoder.out[i].a;
+    )
+
+    encoder2D<NxC,NyC,Nx,Ny,4> encoder(.inx = neuron_grid.outx, .iny = neuron_grid.outy,
+        .reset_B = _reset_B, .supply = supply);
+    fifo<NxC + NyC,5> fifo_post(.in = encoder.out, .out = out, .reset_B = _reset_B, .supply = supply);
+
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+fifo_decoder_neurons_encoder_fifo e; 

test/unit_tests/fifo-decoder_hs-neurons-encoder-fifo/test.prsim

@@ -0,0 +1,74 @@
+watchall
+
+set e.out.a 0
+set e.out.v 0
+set-qdi-channel-neutral "e.in" 7
+set Reset 1
+
+cycle
+
+
+mode run
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+
+
+
+system "echo '[] Sending in a packet'"
+set-qdi-channel-valid "e.in" 7 75
+cycle
+assert-qdi-channel-valid "e.out" 7 75
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 7
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+system "echo '[] Sending in another packet'"
+set-qdi-channel-valid "e.in" 7 22
+cycle
+# Output is still the first packet
+assert-qdi-channel-valid "e.out" 7 75
+assert e.in.a 1
+assert e.in.v 1
+
+system "echo '[] Removing input'"
+set-qdi-channel-neutral "e.in" 7
+cycle
+assert e.in.a 0
+assert e.in.v 0
+
+system "echo '[] Giving out ack'"
+set e.out.a 1
+set e.out.v 1
+cycle
+assert-qdi-channel-neutral "e.out" 7
+
+system "echo '[] Removing ack'"
+set e.out.a 0
+set e.out.v 0
+cycle
+assert-qdi-channel-valid "e.out" 7 22
+
+system "echo '[] Giving out ack'"
+set e.out.a 1
+set e.out.v 1
+cycle
+assert-qdi-channel-neutral "e.out" 7
+
+system "echo '[] Removing ack'"
+set e.out.a 0
+set e.out.v 0
+cycle
+assert-qdi-channel-neutral "e.out" 7
+
+
+
+
+
+