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aa299fb45f
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1aeb37f976
@ -57,17 +57,15 @@ defproc fifo_decoder_neurons_encoder_fifo (avMx1of2<7> in; avMx1of2<7> out; bool
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and_grid<Nx, Ny> _and_grid(.inx = decoder.outx, .iny = decoder.outy, .supply = supply);
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and_grid<Nx, Ny> _and_grid(.inx = decoder.outx, .iny = decoder.outy, .supply = supply);
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// Pretend that each "synapse" immediately makes its one neuron "spike".
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// Pretend that each "synapse" immediately makes its one neuron "spike".
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// that is, connect the output of each encoder target to the decoder input.
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// that is, connect the output of each encoder target to the decoder input.
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nrn_hs_2d_array<Nx,Ny> neuron_grid(.reset_B = _reset_B, .supply = supply);
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nrn_hs_2D_array<Nx,Ny,10> neuron_grid(.reset_B = _reset_B, .supply = supply);
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(i:Nx*Ny:
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(i:Nx*Ny:
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// Connect the output bool to the input req of each neuron handshaker
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// Connect the output bool to the input req of each neuron handshaker
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// Leave ack dangling.
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// Leave ack dangling.
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neuron_grid.in[i].r = _and_grid.out[i];
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neuron_grid.in[i].r = _and_grid.out[i];
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)
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)
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encoder2d_simple<NxC,NyC,Nx,Ny,4> encoder(.inx = neuron_grid.outx, .iny = neuron_grid.outy,
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encoder2D<NxC,NyC,Nx,Ny,4> encoder(.inx = neuron_grid.outx, .iny = neuron_grid.outy,
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.to_pd_x = neuron_grid.to_pd_x, .to_pd_y = neuron_grid.to_pd_y,
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.reset_B = _reset_B, .supply = supply);
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.reset_B = _reset_B, .supply = supply);
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fifo<NxC + NyC,5> fifo_post(.in = encoder.out, .out = out, .reset_B = _reset_B, .supply = supply);
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fifo<NxC + NyC,5> fifo_post(.in = encoder.out, .out = out, .reset_B = _reset_B, .supply = supply);
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}
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}
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@ -14,29 +14,9 @@ set e.dly_cfg[5] 1
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cycle
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cycle
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# assert e.decoder.outx[0] 0
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# assert e.neuron_grid.outx[0].r 0
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# assert e.encoder.pd_x[0].inv.y 1
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# assert e.encoder.pd_x[0].pull_downR.n1 1
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# assert e.encoder.pd_x[0].pull_downR.n2 1
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# assert e.encoder.pd_x[0].pull_downR.y 0
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# assert e.neuron_grid.neurons[0].pu_x.p1 1
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# assert e.neuron_grid.neurons[0].pu_x.p2 1
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# assert e.neuron_grid.neurons[0].pu_x.p3 1
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# assert e.encoder.Xarb.in[0].a 0
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mode run
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mode run
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system "echo '[] Set reset 0'"
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system "echo '[] Set reset 0'"
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system "echo '[] Asserting decoder req 0 0'"
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status X
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status X
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set Reset 0
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set Reset 0
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cycle
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cycle
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@ -55,14 +55,13 @@ defproc fifo_decoder_neurons_encoder_fifo (avMx1of2<7> in; avMx1of2<7> out){
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decoder_2d_hs<NxC,NyC,Nx,Ny> decoder(.in = fifo_pre.out, .reset_B = _reset_B, .supply = supply);
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decoder_2d_hs<NxC,NyC,Nx,Ny> decoder(.in = fifo_pre.out, .reset_B = _reset_B, .supply = supply);
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// Pretend that each "synapse" immediately makes its one neuron "spike".
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// Pretend that each "synapse" immediately makes its one neuron "spike".
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// that is, connect the output of each encoder target to the decoder input.
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// that is, connect the output of each encoder target to the decoder input.
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nrn_hs_2d_array<Nx,Ny> neuron_grid(.reset_B = _reset_B, .supply = supply);
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nrn_hs_2D_array<Nx,Ny,10> neuron_grid(.reset_B = _reset_B, .supply = supply);
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(i:Nx*Ny:
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(i:Nx*Ny:
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neuron_grid.in[i].r = decoder.out[i].r;
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neuron_grid.in[i].r = decoder.out[i].r;
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neuron_grid.in[i].a = decoder.out[i].a;
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neuron_grid.in[i].a = decoder.out[i].a;
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)
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)
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encoder2d_simple<NxC,NyC,Nx,Ny,4> encoder(.inx = neuron_grid.outx, .iny = neuron_grid.outy,
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encoder2D<NxC,NyC,Nx,Ny,4> encoder(.inx = neuron_grid.outx, .iny = neuron_grid.outy,
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.to_pd_x = neuron_grid.to_pd_x, .to_pd_y = neuron_grid.to_pd_y,
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.reset_B = _reset_B, .supply = supply);
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.reset_B = _reset_B, .supply = supply);
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fifo<NxC + NyC,5> fifo_post(.in = encoder.out, .out = out, .reset_B = _reset_B, .supply = supply);
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fifo<NxC + NyC,5> fifo_post(.in = encoder.out, .out = out, .reset_B = _reset_B, .supply = supply);
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@ -36,7 +36,7 @@ open std::data;
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open tmpl::dataflow_neuro;
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open tmpl::dataflow_neuro;
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defproc fifo_decoder_neurons_encoder_fifo (avMx1of2<7> in; avMx1of2<7> out; bool? dly_cfg[4], hs_en, ack_disable){
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defproc fifo_decoder_neurons_encoder_fifo (avMx1of2<7> in; avMx1of2<7> out; bool? dly_cfg[4], hs_en){
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bool _reset_B;
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bool _reset_B;
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prs {
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prs {
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Reset => _reset_B-
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Reset => _reset_B-
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@ -52,35 +52,18 @@ defproc fifo_decoder_neurons_encoder_fifo (avMx1of2<7> in; avMx1of2<7> out; bool
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Ny = 1<<NyC;
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Ny = 1<<NyC;
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fifo<NxC + NyC,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);
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fifo<NxC + NyC,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);
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decoder_2d_hybrid<NxC,NyC,Nx,Ny,4> decoder(.in = fifo_pre.out, .dly_cfg =dly_cfg, .hs_en = hs_en,
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decoder_2d_hybrid<NxC,NyC,Nx,Ny,4> decoder(.in = fifo_pre.out, .dly_cfg =dly_cfg,
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.hs_en = hs_en, .ack_disable = ack_disable,
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.reset_B = _reset_B, .supply = supply);
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.reset_B = _reset_B, .supply = supply);
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// Pretend that each "synapse" immediately makes its one neuron "spike".
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// // Pretend that each "synapse" immediately makes its one neuron "spike".
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// that is, connect the output of each encoder target to the decoder input.
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// // that is, connect the output of each encoder target to the decoder input.
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nrn_hs_2D_array<Nx,Ny,10> neuron_grid(.reset_B = _reset_B, .supply = supply);
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// and_grid<Nx, Ny> _and_grid(.inx = decoder.out_req_x, .iny = decoder.out_req_y, .supply = supply);
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(i:Nx*Ny:
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neuron_grid.in[i].r = decoder.out[i].r;
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neuron_grid.in[i].a = decoder.out[i].a;
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)
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// // Attach line end pull ups of decoder
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encoder2D<NxC,NyC,Nx,Ny,4> encoder(.inx = neuron_grid.outx, .iny = neuron_grid.outy,
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// decoder.to_pu = decoder.
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// Dummy synapse handshake circuits, to be removed for innovus
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decoder_2d_synapse_hs<Nx, Ny> _synapses(
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.in_req_x = decoder.out_req_x, .in_req_y = decoder.out_req_y,
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.to_pu = decoder.to_pu,
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.out_ackB_decoder = decoder.in_ackB_decoder,
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.supply = supply);
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nrn_hs_2d_array<Nx,Ny> neuron_grid(.in =_synapses.synapses,
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.reset_B = _reset_B, .supply = supply);
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.reset_B = _reset_B, .supply = supply);
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encoder2d_simple<NxC,NyC,Nx,Ny,4> encoder(.inx = neuron_grid.outx, .iny = neuron_grid.outy,
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.to_pd_x = neuron_grid.to_pd_x, .to_pd_y = neuron_grid.to_pd_y,
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.reset_B = _reset_B, .supply = supply);
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fifo<NxC + NyC,5> fifo_post(.in = encoder.out, .out = out, .reset_B = _reset_B, .supply = supply);
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fifo<NxC + NyC,5> fifo_post(.in = encoder.out, .out = out, .reset_B = _reset_B, .supply = supply);
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}
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}
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@ -7,7 +7,7 @@ set e.dly_cfg[1] 0
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set e.dly_cfg[2] 0
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set e.dly_cfg[2] 0
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set e.dly_cfg[3] 0
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set e.dly_cfg[3] 0
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set e.hs_en 1
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set e.hs_en 1
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set e.ack_disable 0
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set e.out.a 0
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set e.out.a 0
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