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21
dataflow_neuro/cell_lib_async.act
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@ -130,17 +130,6 @@ namespace tmpl {
y {-1}}
}
export defcell A_1C1N_X1 (bool! y; bool? c1, n1; bool vdd, vss)
{
prs{
~c1 -> y+
c1&n1-> y-
}
sizing {leak_adjust <- 1;
p_n_mode <- 1;
y {-1}}
}
// export defcell A_1C1N_RB_X4 (bool! y; bool? c1, n1, pr_B, sr_B; bool vdd, vss)
// {
// bool _y;
@ -167,16 +156,6 @@ namespace tmpl {
// y {-4}; _y{-1}}
// }
export defcell A_1C2N_R_X1 (bool! y; bool? c1, n1, n2, pr_B, sr_B; bool vdd, vss)
{
prs{
~c1 | ~pr_B-> y+
c1&n1&n2&sr_B -> y-
}
sizing {leak_adjust <- 1;
p_n_mode <- 1;
y {-4}}
}
export defcell A_1C2N_RB_X4 (bool! y; bool? c1, n1, n2, pr_B, sr_B; bool vdd, vss)
{

2
dataflow_neuro/cell_lib_std.act
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@ -283,8 +283,6 @@ namespace tmpl {
export defcell MUX2_X1(bool! y; bool? a, b, s, vdd, vss)
{
// y = !( S ? b : a )
// Actually looks more like
// if s = 0 -> use A
// Adjusted to fit the XFAB Muxes
bool _s;
bool _y;