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b4d2d79f5f
| Author | SHA1 | Date |
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Michele
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b4d2d79f5f | |
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Michele
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8dabc59a03 |
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@ -51,10 +51,12 @@ namespace tmpl {
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// - the last wl the word to write
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// data -> the data saved in the flip flop, sized wl x nw
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export template<pint log_nw,wl,N_dly_cfg>
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defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power suppy; bool reset_B,reset_mem_B){
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defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power supply; bool reset_B,reset_mem_B){
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bool _in_v_temp,_in_a_temp,_clock_temp,_clock;
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//Validation of the input
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vtree val_input(.in = in,.out = _in_v_temp, .supply = supply);
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Mx1of2<1+log_nw+wl> in_temp;
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(i:1+log_nw+wl:in_temp.d[i] = in.d.d[i];)
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vtree<1+log_nw+wl> val_input(.in = in_temp,.out = _in_v_temp, .supply = supply);
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sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
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in.v = _in_v_temp;
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// Generation of the clock pulse
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@ -1,9 +1,35 @@
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t.clk t.d t.q t.ff._qb t.ff._q_B t.ff.__clk t.ff._dl t.ff._clk
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t.ff._mqib t.clk t.d t.q t.ff._sqib t.ff._sqi t.ff.__clk t.ff._mqi t.ff._clk
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[0] start test
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1 t.d : 0
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1 t.clk : 0
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7093 t.ff._mqib : 1 [by t.d:=0]
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7095 t.ff._mqi : 0 [by t.ff._mqib:=1]
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10468 t.ff._clk : 1 [by t.clk:=0]
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11605 t.ff.__clk : 0 [by t.ff._clk:=1]
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11848 t.ff._sqib : 1 [by t.ff._mqi:=0]
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11962 t.ff._sqi : 0 [by t.ff._sqib:=1]
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77214 t.q : 0 [by t.ff._sqib:=1]
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77214 Reset : 0
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78940 t._reset_B : 1 [by Reset:=0]
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[1] reset completed
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WRONG ASSERT: "t.q" has value 1 and not 0.
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[2] setting d to 1
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WRONG ASSERT: "t.q" has value 1 and not 0.
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[3] setting clk to 1
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[4] Finished
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78940 t.clk : 1
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78979 t.ff._clk : 0 [by t.clk:=1]
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78994 t.ff.__clk : 1 [by t.ff._clk:=0]
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[2] tested d = 0, clk rise
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78994 t.clk : 0
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79485 t.ff._clk : 1 [by t.clk:=0]
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79498 t.ff.__clk : 0 [by t.ff._clk:=1]
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79498 t.d : 1
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79498 t.clk : 1
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79538 t.ff._clk : 0 [by t.clk:=1]
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79953 t.ff.__clk : 1 [by t.ff._clk:=0]
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79973 t.ff._mqib : 0 [by t.ff.__clk:=1]
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86034 t.ff._mqi : 1 [by t.ff._mqib:=0]
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86034 t.clk : 0
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86081 t.ff._clk : 1 [by t.clk:=0]
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86097 t.ff.__clk : 0 [by t.ff._clk:=1]
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130179 t.ff._sqib : 0 [by t.ff._clk:=1]
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130183 t.q : 1 [by t.ff._sqib:=0]
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143903 t.ff._sqi : 1 [by t.ff._sqib:=0]
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[3] tested d = 1, clk rise and fall
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@ -3,25 +3,21 @@
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= "Reset" "Reset"
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"Reset"->"t._reset_B"-
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~("Reset")->"t._reset_B"+
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"t.ff._q_B"->"t.ff.q"-
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~"t.ff._q_B"->"t.ff.q"+
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= "t._reset_B" "t.ff.reset_B"
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"t.ff.clk"->"t.ff._clk"-
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~"t.ff.clk"->"t.ff._clk"+
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~("t.ff.clk")->"t.ff._clk"+
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"t.ff._clk"->"t.ff.__clk"-
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~"t.ff._clk"->"t.ff.__clk"+
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"t.ff.reset"->"t.ff._Ro"-
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~"t.ff.reset"->"t.ff._Ro"+
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"t.ff.d"&"t.ff._clk"->"t.ff._dl"-
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~"t.ff.d"&~"t.ff.__clk"->"t.ff._dl"+
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"t.ff.reset"&"t.ff._qb"->"t.ff._q_B"-
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~"t.ff.reset"|~"t.ff._qb"->"t.ff._q_B"+
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after 0 "t.ff.__clk" & ~"t.ff._Ro" -> "t.ff._dl"-
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~"t.ff._clk" & "t.ff._Ro" -> "t.ff._dl"+
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after 0 "t.ff.__clk" & ~"t.ff.reset" -> "t.ff._qb"-
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~"t.ff._clk" & "t.ff.reset" -> "t.ff._qb"+
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after 0 "t.ff._clk" & ~"t.ff.reset" -> "t.ff._qb"-
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~"t.ff.__clk" & "t.ff.reset" -> "t.ff._qb"+
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= "Reset" "t.ff.reset"
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~("t.ff._clk")->"t.ff.__clk"+
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~"t.ff.d"&~"t.ff._clk"|~"t.ff.reset_B"|~"t.ff.__clk"&~"t.ff._mqi"->"t.ff._mqib"+
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"t.ff.d"&"t.ff.__clk"|"t.ff.reset_B"&"t.ff._mqi"&"t.ff._clk"->"t.ff._mqib"-
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"t.ff._mqib"->"t.ff._mqi"-
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~("t.ff._mqib")->"t.ff._mqi"+
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~"t.ff._mqi"&~"t.ff.__clk"|~"t.ff.reset_B"|~"t.ff._sqi"&~"t.ff._clk"->"t.ff._sqib"+
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"t.ff._mqi"&"t.ff._clk"|"t.ff._sqi"&"t.ff.__clk"&"t.ff.reset_B"->"t.ff._sqib"-
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"t.ff._sqib"->"t.ff._sqi"-
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~("t.ff._sqib")->"t.ff._sqi"+
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"t.ff._sqib"->"t.ff.q"-
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~("t.ff._sqib")->"t.ff.q"+
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= "Vdd" "t.ff.vdd"
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= "GND" "t.ff.vss"
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= "t.q" "t.ff.q"
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@ -41,7 +41,7 @@ defproc flipflop_test (bool! q; bool? d,clk){
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}
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ff.vss = GND;
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ff.vdd = Vdd;
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ff.reset = Reset;
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ff.reset_B = _reset_B;
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}
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@ -1,21 +1,28 @@
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set t.d 0
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set t.clk 0
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set Reset 0
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cycle
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assert t.q 0
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watchall
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system "echo '[0] start test'"
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set Reset 1
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set t.d 0
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set t.clk 0
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cycle
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status X
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mode run
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assert t.q 0
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set Reset 0
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cycle
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assert t.q 0
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system "echo '[1] reset completed'"
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system "echo '[2] setting d to 1'"
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set t.clk 1
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cycle
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assert t.q 0
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system "echo '[3] setting clk to 1'"
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system "echo '[2] tested d = 0, clk rise'"
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set t.clk 0
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cycle
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set t.d 1
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cycle
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set t.clk 1
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cycle
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assert t.q 0
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set t.clk 0
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cycle
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assert t.q 1
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system "echo '[4] Finished'"
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system "echo '[3] tested d = 1, clk rise and fall'"
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@ -0,0 +1,3 @@
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= "GND" "GND"
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= "Vdd" "Vdd"
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= "Reset" "Reset"
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@ -0,0 +1,51 @@
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/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library.
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* It's the testing facility for cell_lib_std.act
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/registers.act";
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import globals;
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open tmpl::dataflow_neuro;
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defproc register_test (avMx1of2<1+2+2> in; d1of<2> data[2<<2]){
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register_rw<2,2,2> registers(.in=in,.data = data);
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//Low active Reset
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bool _reset_B;
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power supply;
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prs {
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Reset => _reset_B-
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}
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registers.supply = _supply;
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_supply.vss = GND;
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_supply.vdd = Vdd;
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registers.reset_B = _reset_B;
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registers.reset_B_mem = _reset_B;
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}
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register_test t;
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@ -0,0 +1,8 @@
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watchall
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system "echo '[0] start test'"
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set Reset 1
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set-qdi-channel-neutral "t.in" 2
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cycle
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status X
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mode run
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system "echo '[1] reset completed'"
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