started testing the register_w

dataflow_neuro/registers.act

@@ -51,10 +51,12 @@ namespace tmpl {
 //        - the last wl the word to write
 // data -> the data saved in the flip flop, sized wl x nw
 export template<pint log_nw,wl,N_dly_cfg>
-defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power suppy; bool reset_B,reset_mem_B){
+defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power supply; bool reset_B,reset_mem_B){
     bool _in_v_temp,_in_a_temp,_clock_temp,_clock;
     //Validation of the input 
-    vtree val_input(.in = in,.out = _in_v_temp, .supply = supply);
+    Mx1of2<1+log_nw+wl> in_temp;
+    (i:1+log_nw+wl:in_temp.d[i] = in.d.d[i];)
+    vtree<1+log_nw+wl> val_input(.in = in_temp,.out = _in_v_temp, .supply = supply);
     sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
     in.v = _in_v_temp;
     // Generation of the clock pulse

test/unit_tests/flipflop/run/prsim.out

@@ -1,9 +1,35 @@
-t.clk t.d t.q t.ff._qb t.ff._q_B t.ff.__clk t.ff._dl t.ff._clk 
+t.ff._mqib t.clk t.d t.q t.ff._sqib t.ff._sqi t.ff.__clk t.ff._mqi t.ff._clk 
 [0] start test
+	         1 t.d : 0
+	         1 t.clk : 0
+	      7093 t.ff._mqib : 1  [by t.d:=0]
+	      7095 t.ff._mqi : 0  [by t.ff._mqib:=1]
+	     10468 t.ff._clk : 1  [by t.clk:=0]
+	     11605 t.ff.__clk : 0  [by t.ff._clk:=1]
+	     11848 t.ff._sqib : 1  [by t.ff._mqi:=0]
+	     11962 t.ff._sqi : 0  [by t.ff._sqib:=1]
+	     77214 t.q : 0  [by t.ff._sqib:=1]
 
+	     77214 Reset : 0
+	     78940 t._reset_B : 1  [by Reset:=0]
 [1] reset completed
-WRONG ASSERT:	"t.q" has value 1 and not 0.
+	     78940 t.clk : 1
-[2] setting d to 1
+	     78979 t.ff._clk : 0  [by t.clk:=1]
-WRONG ASSERT:	"t.q" has value 1 and not 0.
+	     78994 t.ff.__clk : 1  [by t.ff._clk:=0]
-[3] setting clk to 1
+[2] tested d = 0, clk rise
-[4] Finished
+	     78994 t.clk : 0
+	     79485 t.ff._clk : 1  [by t.clk:=0]
+	     79498 t.ff.__clk : 0  [by t.ff._clk:=1]
+	     79498 t.d : 1
+	     79498 t.clk : 1
+	     79538 t.ff._clk : 0  [by t.clk:=1]
+	     79953 t.ff.__clk : 1  [by t.ff._clk:=0]
+	     79973 t.ff._mqib : 0  [by t.ff.__clk:=1]
+	     86034 t.ff._mqi : 1  [by t.ff._mqib:=0]
+	     86034 t.clk : 0
+	     86081 t.ff._clk : 1  [by t.clk:=0]
+	     86097 t.ff.__clk : 0  [by t.ff._clk:=1]
+	    130179 t.ff._sqib : 0  [by t.ff._clk:=1]
+	    130183 t.q : 1  [by t.ff._sqib:=0]
+	    143903 t.ff._sqi : 1  [by t.ff._sqib:=0]
+[3] tested d = 1, clk rise and fall

test/unit_tests/flipflop/run/test.prs

@@ -3,25 +3,21 @@
 = "Reset" "Reset"
 "Reset"->"t._reset_B"-
 ~("Reset")->"t._reset_B"+
-"t.ff._q_B"->"t.ff.q"-
+= "t._reset_B" "t.ff.reset_B"
-~"t.ff._q_B"->"t.ff.q"+
 "t.ff.clk"->"t.ff._clk"-
-~"t.ff.clk"->"t.ff._clk"+
+~("t.ff.clk")->"t.ff._clk"+
 "t.ff._clk"->"t.ff.__clk"-
-~"t.ff._clk"->"t.ff.__clk"+
+~("t.ff._clk")->"t.ff.__clk"+
-"t.ff.reset"->"t.ff._Ro"-
+~"t.ff.d"&~"t.ff._clk"|~"t.ff.reset_B"|~"t.ff.__clk"&~"t.ff._mqi"->"t.ff._mqib"+
-~"t.ff.reset"->"t.ff._Ro"+
+"t.ff.d"&"t.ff.__clk"|"t.ff.reset_B"&"t.ff._mqi"&"t.ff._clk"->"t.ff._mqib"-
-"t.ff.d"&"t.ff._clk"->"t.ff._dl"-
+"t.ff._mqib"->"t.ff._mqi"-
-~"t.ff.d"&~"t.ff.__clk"->"t.ff._dl"+
+~("t.ff._mqib")->"t.ff._mqi"+
-"t.ff.reset"&"t.ff._qb"->"t.ff._q_B"-
+~"t.ff._mqi"&~"t.ff.__clk"|~"t.ff.reset_B"|~"t.ff._sqi"&~"t.ff._clk"->"t.ff._sqib"+
-~"t.ff.reset"|~"t.ff._qb"->"t.ff._q_B"+
+"t.ff._mqi"&"t.ff._clk"|"t.ff._sqi"&"t.ff.__clk"&"t.ff.reset_B"->"t.ff._sqib"-
-after 0 "t.ff.__clk" & ~"t.ff._Ro" -> "t.ff._dl"-
+"t.ff._sqib"->"t.ff._sqi"-
-~"t.ff._clk" & "t.ff._Ro" -> "t.ff._dl"+
+~("t.ff._sqib")->"t.ff._sqi"+
-after 0 "t.ff.__clk" & ~"t.ff.reset" -> "t.ff._qb"-
+"t.ff._sqib"->"t.ff.q"-
-~"t.ff._clk" & "t.ff.reset" -> "t.ff._qb"+
+~("t.ff._sqib")->"t.ff.q"+
-after 0 "t.ff._clk" & ~"t.ff.reset" -> "t.ff._qb"-
-~"t.ff.__clk" & "t.ff.reset" -> "t.ff._qb"+
-= "Reset" "t.ff.reset"
 = "Vdd" "t.ff.vdd"
 = "GND" "t.ff.vss"
 = "t.q" "t.ff.q"

test/unit_tests/flipflop/test.act

@@ -41,7 +41,7 @@ defproc flipflop_test (bool! q; bool? d,clk){
     }
     ff.vss = GND;
     ff.vdd = Vdd;
-    ff.reset = Reset;
+    ff.reset_B = _reset_B;
     
 }
 

test/unit_tests/flipflop/test.prsim

@@ -1,21 +1,28 @@
-
+watchall
-set t.d 0
-set t.clk 0
-set Reset 0
-cycle
-assert t.q 0
 system "echo '[0] start test'"
 set Reset 1
+set t.d 0
+set t.clk 0
 cycle
 status X
 mode run
+assert t.q 0
+set Reset 0
+cycle
+assert t.q 0
 system "echo '[1] reset completed'"
-system "echo '[2] setting d to 1'"
 set t.clk 1
 cycle
 assert t.q 0
-system "echo '[3] setting clk to 1'"
+system "echo '[2] tested d = 0, clk rise'"
+set t.clk 0
+cycle
+set t.d 1
+cycle
 set t.clk 1
 cycle
+assert t.q 0
+set t.clk 0
+cycle
 assert t.q 1
-system "echo '[4] Finished'"
+system "echo '[3] tested d = 1, clk rise and fall'"

test/unit_tests/register_write/run/test.prs

@@ -0,0 +1,3 @@
+= "GND" "GND"
+= "Vdd" "Vdd"
+= "Reset" "Reset"

test/unit_tests/register_write/test.act

@@ -0,0 +1,51 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/registers.act";
+import globals;
+
+open tmpl::dataflow_neuro;
+
+defproc register_test (avMx1of2<1+2+2> in; d1of<2> data[2<<2]){
+
+    register_rw<2,2,2> registers(.in=in,.data = data);
+    //Low active Reset 
+    bool _reset_B; 
+    power supply;
+    prs {
+    	Reset => _reset_B-
+    }
+    registers.supply = _supply;
+    _supply.vss = GND;
+    _supply.vdd = Vdd;
+    registers.reset_B = _reset_B;
+    registers.reset_B_mem = _reset_B;
+    
+}
+
+register_test t;

test/unit_tests/register_write/test.prsim

@@ -0,0 +1,8 @@
+watchall
+system "echo '[0] start test'"
+set Reset 1
+set-qdi-channel-neutral "t.in" 2
+cycle
+status X
+mode run
+system "echo '[1] reset completed'"