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c81e77a2fa
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e27d55bff4
@ -56,8 +56,6 @@ defproc chip_texel (bd<N_IN> in, out;
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Mx1of2<REG_NCW> reg_data[REG_M];
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Mx1of2<REG_NCW> reg_data[REG_M];
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a1of1 synapses[N_SYN_X * N_SYN_Y];
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a1of1 synapses[N_SYN_X * N_SYN_Y];
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a1of1 neurons[N_NRN_X * N_NRN_Y];
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a1of1 neurons[N_NRN_X * N_NRN_Y];
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bool? nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y];
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bool? syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y];
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bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
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bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
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bool? loopback_en;
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bool? loopback_en;
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power supply;
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power supply;
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@ -84,17 +82,18 @@ defproc chip_texel (bd<N_IN> in, out;
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.supply = supply, .reset_B = reset_B);
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.supply = supply, .reset_B = reset_B);
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fifo<N_IN-2,N_BUFFERS> fifo_reg2mrg(.in = register.out, .reset_B = reset_B, .supply = supply);
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fifo<N_IN-2,N_BUFFERS> fifo_reg2mrg(.in = register.out, .reset_B = reset_B, .supply = supply);
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// TO ADD: nrn/syn mon decoders
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// Spike Decoder
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// Decoder
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pint NC_SYN;
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pint NC_SYN;
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NC_SYN = NC_SYN_X + NC_SYN_Y;
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NC_SYN = NC_SYN_X + NC_SYN_Y;
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slice_data<N_IN-1, 0, NC_SYN> slice_pre_dec(.in = _demux.out1, .supply = supply);
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slice_data<N_IN-1, 0, NC_SYN> slice_pre_dec(.in = _demux.out1, .supply = supply);
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fifo<NC_SYN,N_BUFFERS> fifo_dmx2dec(.in = slice_pre_dec.out, .reset_B = reset_B, .supply = supply);
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fifo<NC_SYN,N_BUFFERS> fifo_dmx2dec(.in = slice_pre_dec.out, .reset_B = reset_B, .supply = supply);
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decoder_2d_hybrid<NC_SYN_X, NC_SYN_Y, N_SYN_X, N_SYN_Y, N_SYN_DLY_CFG> decoder(.in = fifo_dmx2dec.out,
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decoder_2d_hybrid<NC_SYN_X, NC_SYN_Y, N_SYN_X, N_SYN_Y, N_SYN_DLY_CFG> decoder(.in = fifo_dmx2dec.out,
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.out = synapses,
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.out = synapses,
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.hs_en = register.data[0].d[0].t, // Defaults to handshake disable
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.hs_en = register.data[0].d[0].f, // Defaults to handshake disable
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.supply = supply, .reset_B = reset_B);
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.supply = supply, .reset_B = reset_B);
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(i:N_SYN_DLY_CFG: decoder.dly_cfg[i] = register.data[0].d[1 + i].f;) // Defaults to max delay
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(i:N_SYN_DLY_CFG: decoder.dly_cfg[i] = register.data[0].d[1 + i].t;) // Defaults to max delay
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// Neurons + encoder
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// Neurons + encoder
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pint NC_NRN;
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pint NC_NRN;
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@ -125,42 +124,6 @@ defproc chip_texel (bd<N_IN> in, out;
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qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg,
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qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg,
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.reset_B = reset_B, .supply = supply);
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.reset_B = reset_B, .supply = supply);
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// Neuron/synapse monitor targeters
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pint NC_NRN_MON_X = std::ceil_log2(N_NRN_MON_X);
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pint NC_NRN_MON_Y = std::ceil_log2(N_NRN_MON_Y);
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pint NC_SYN_MON_X = std::ceil_log2(N_SYN_MON_X);
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pint NC_SYN_MON_Y = std::ceil_log2(N_SYN_MON_Y);
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decoder_dualrail_en<NC_NRN_MON_X, N_NRN_MON_X, N_NRN_Y> nrn_mon_dec_x(.out = nrn_mon_x,
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.supply = supply);
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nrn_mon_dec_x.en = register.data[1].d[0].t;
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(i:NC_NRN_MON_X:
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nrn_mon_dec_x.in.d[i] = register.data[2].d[i];
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)
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decoder_dualrail_en<NC_NRN_MON_Y, N_NRN_MON_Y, N_NRN_X> nrn_mon_dec_y(.out = nrn_mon_y,
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.supply = supply);
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nrn_mon_dec_y.en = register.data[1].d[0].t;
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(i:NC_NRN_MON_Y:
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nrn_mon_dec_y.in.d[i] = register.data[2].d[i+NC_NRN_MON_X];
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)
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decoder_dualrail_en<NC_SYN_MON_X, N_SYN_MON_X, N_SYN_Y> syn_mon_dec_x(.out = syn_mon_x,
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.supply = supply);
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syn_mon_dec_x.en = register.data[1].d[1].t;
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(i:NC_SYN_MON_X:
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syn_mon_dec_x.in.d[i] = register.data[3].d[i];
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)
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decoder_dualrail_en<NC_SYN_MON_Y, N_SYN_MON_Y, N_SYN_X> syn_mon_dec_y(.out = syn_mon_y,
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.supply = supply);
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syn_mon_dec_y.en = register.data[1].d[1].t;
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(i:NC_SYN_MON_Y:
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syn_mon_dec_y.in.d[i] = register.data[3].d[i+NC_SYN_MON_X];
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)
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}
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}
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}
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}
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}
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}
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@ -39,6 +39,220 @@ open std::channel;
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namespace tmpl {
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namespace tmpl {
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namespace dataflow_neuro {
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namespace dataflow_neuro {
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// Circuit for storing registers using AER
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// The block has the parameters:
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// lognw -> log2(number of words), parameters you can store
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// wl -> word length, length of each word
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// N_dly_cfg -> the number of config bits in the ACK delay line
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// The block has the pins:
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// in -> input data,
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// - the first bit is write/read_B
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// - the next lognw bits describe the location,
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// - the last wl the word to write
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// data -> the data saved in the flip flop, sized wl x nw
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export template<pint lognw,wl,N_dly_cfg>
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defproc register_w (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
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bool _in_v_temp,_in_a_temp,_clock_temp,_clock,_clock_temp_inv;
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pint nw = 1<<lognw;
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//Validation of the input
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vtree<1+lognw+wl> val_input(.in = in.d,.out = _in_v_temp, .supply = supply);
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sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
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// Generation of the fake clock pulse (inverted because the ff clocks are low_active)
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delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp, .out = _clock_temp,.s = dly_cfg, .supply = supply);
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INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
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sigbuf_1output<4> clk_X(.in = _clock_temp,.out = _clock,.supply = supply);
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// Sending back to the ackowledge
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delayprog<N_dly_cfg> ack_dly(.in = _clock_temp_inv, .out = _in_a_temp,.s = dly_cfg, .supply = supply);
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sigbuf_1output<4> ack_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
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//Reset Buffers
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bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[nw*wl];
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BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
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BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
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sigbuf<nw*wl> reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
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// Creating the different flip flop arrays
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bool _out_encoder[nw],_clock_word_temp[nw],_clock_word[nw],_clock_buffer_out[nw*wl];
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andtree<lognw> atree[nw];
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AND2_X1 and_encoder[nw];
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sigbuf<wl> clock_buffer[nw];
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DFFQ_R_X1 ff[nw*wl];
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pint bitval;
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(k:nw:atree[k].supply = supply;)
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(word_idx:nw:
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// Decoding the bit pattern to understand which word we are looking at
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(pin_idx:lognw:
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bitval = (word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j
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[bitval = 1 ->
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atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].t;
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[] bitval = 0 ->
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atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].f;
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[]bitval >= 2 -> {false : "fuck"};
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]
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)
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// Activating the fake clock for the right word
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atree[word_idx].out = _out_encoder[word_idx];
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and_encoder[word_idx].a = _out_encoder[word_idx];
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and_encoder[word_idx].b = _clock;
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and_encoder[word_idx].y = _clock_word_temp[word_idx];
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and_encoder[word_idx].vdd = supply.vdd;
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and_encoder[word_idx].vss = supply.vss;
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clock_buffer[word_idx].in = _clock_word_temp[word_idx];
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clock_buffer[word_idx].supply = supply;
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// Describing all the FF and their connection
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(bit_idx:wl:
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ff[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx];
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ff[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].t;
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ff[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx];
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ff[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)];
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ff[bit_idx+word_idx*(wl)].vdd = supply.vdd;
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ff[bit_idx+word_idx*(wl)].vss = supply.vss;
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)
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)
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}
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// Circuit for storing and reading registers using AER
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// The block has the parameters:
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// lognw -> log2(number of words), parameters you can store
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// wl -> word length, length of each word
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// N_dly_cfg -> the number of config bits in the ACK delay line
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// The block has the pins:
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// in -> input data,
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// - the MSB is write/read_B
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// - the next MSB bits (size lognw) are the location,
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// - the LSB (size wl) are the word to write
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// out -> in case a reading phase is required, the output is used to show the stored data
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// - the MSB bits (size lognw) tell the read register
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// - the LSB bits (size wl) tell the word read
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// data -> the data saved in the flip flop, sized wl x nw
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export template<pint lognw,wl,N_dly_cfg>
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defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
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pint nw = 1<<lognw;
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bool _in_v_temp,_in_a_temp,_clock_temp,_clock[nw],_clock_temp_inv, _in_a_write, _in_a_read;
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//Validation of the input
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vtree<1+lognw+wl> val_input(.in = in.d,.out = _in_v_temp, .supply = supply);
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sigbuf_1output<12> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
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// Acknowledgment
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OR2_X1 ack_readwrite(.a = _in_a_write,.b = _in_a_read,.y = _in_a_temp,.vdd = supply.vdd,.vss = supply.vss);
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sigbuf_1output<12> ack_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
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// WRITE
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// Generation of the fake clock pulse if write is HIGH (inverted because the ff clocks are low_active)
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bool _in_v_temp_write;
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AND2_X1 clk_switch(.a = _in_v_temp,.b = in.d.d[lognw+wl].f,.y = _in_v_temp_write,.vdd = supply.vdd,.vss = supply.vss);
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delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp_write, .out = _clock_temp,.s = dly_cfg, .supply = supply);
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INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
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sigbuf<nw> clk_X(.in = _clock_temp_inv, .out = _clock,.supply = supply);
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sigbuf<wl> clock_buffer[nw];
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bool _clock_word_temp[nw],_clock_word[nw],_clock_buffer_out[nw*wl];
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// Sending back to the acknowledge
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bool _in_a_write_temp;
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delayprog<N_dly_cfg> ack_dly(.in = _clock_temp, .out = _in_a_write_temp,.s = dly_cfg, .supply = supply);
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AND2_X1 ack_write_and(.a = in.d.d[lognw+wl].f,.b = _in_a_write_temp,.y = _in_a_write,.vdd = supply.vdd, .vss = supply.vss);
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// READ
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//Outputing the word to read
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AND2_X1 word_to_read[nw];
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sigbuf<wl*2> word_to_read_X[nw];
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ortree<nw> bitselector_t[wl];
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ortree<nw> bitselector_f[wl];
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AND2_X1 word_selector_t[nw*wl];
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AND2_X1 word_selector_f[nw*wl];
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buffer_s<lognw+wl> output_buf(.out = out,.supply = supply, .reset_B = reset_B);
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AND2_X1 address_propagator_f[lognw],address_propagator_t[lognw];
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// Outputting the address if the read is true
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(i:lognw:
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address_propagator_t[i].a = in.d.d[lognw+wl].t;
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address_propagator_t[i].b = in.d.d[i+wl].t;
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address_propagator_t[i].y = output_buf.in.d.d[i+wl].t;
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address_propagator_t[i].vdd = supply.vdd;
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address_propagator_t[i].vss = supply.vss;
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address_propagator_f[i].a = in.d.d[lognw+wl].t;
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address_propagator_f[i].b = in.d.d[i+wl].f;
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address_propagator_f[i].y = output_buf.in.d.d[i+wl].f;
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address_propagator_f[i].vdd = supply.vdd;
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address_propagator_f[i].vss = supply.vss;
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)
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AND2_X1 ack_read_and(.a = in.d.d[lognw+wl].t,.b = output_buf.in.a,.y = _in_a_read,.vdd = supply.vdd, .vss = supply.vss);
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//Reset Buffers
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bool _reset_BX, _reset_BXX[nw],_reset_mem_BX,_reset_mem_BXX[nw*wl];
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BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
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BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
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sigbuf<nw*wl> reset_mem_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
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sigbuf<nw> reset_bufarray(.in=_reset_BX, .out=_reset_BXX,.supply=supply);
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//Creating the encoder
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andtree<lognw> atree[nw];
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OR2_X1 or_encoder[nw];
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INV_X1 inv_encoder[nw];
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// Creating the different flip flop arrays
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bool _out_encoder[nw];
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DFFQ_R_X1 ff[nw*wl];
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AND2_X1 val_chck[nw*wl];
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bool _val_chck_out[nw*wl];
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bool _in_v_temp_buf[nw*wl];
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sigbuf<nw*wl> v_buf(.in = _in_v_temp,.out = _in_v_temp_buf,.supply = supply);
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// For loop for assigning the different components
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pint bitval;
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(k:nw:atree[k].supply = supply;)
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(word_idx:nw:
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// Decoding the bit pattern to understand which word we are looking at
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(pin_idx:lognw:
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bitval = (word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j
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[bitval = 1 ->
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atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].t;
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[] bitval = 0 ->
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atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].f;
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[]bitval >= 2 -> {false : "fuck"};
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]
|
||||||
|
)
|
||||||
|
// WRITE: Activating the fake clock for the right word
|
||||||
|
atree[word_idx].out = _out_encoder[word_idx];
|
||||||
|
inv_encoder[word_idx].a = _out_encoder[word_idx];
|
||||||
|
inv_encoder[word_idx].y = or_encoder[word_idx].a;
|
||||||
|
inv_encoder[word_idx].vdd = supply.vdd;
|
||||||
|
inv_encoder[word_idx].vss = supply.vss;
|
||||||
|
or_encoder[word_idx].b = _clock[word_idx];
|
||||||
|
or_encoder[word_idx].y = _clock_word_temp[word_idx];
|
||||||
|
or_encoder[word_idx].vdd = supply.vdd;
|
||||||
|
or_encoder[word_idx].vss = supply.vss;
|
||||||
|
clock_buffer[word_idx].in = _clock_word_temp[word_idx];
|
||||||
|
clock_buffer[word_idx].supply = supply;
|
||||||
|
// READ: Selecting the right word to read if read is high
|
||||||
|
word_to_read[word_idx].a = in.d.d[lognw+wl].t;
|
||||||
|
word_to_read[word_idx].b = _out_encoder[word_idx];
|
||||||
|
word_to_read[word_idx].y = word_to_read_X[word_idx].in;
|
||||||
|
word_to_read[word_idx].vdd = supply.vdd;
|
||||||
|
word_to_read[word_idx].vss = supply.vss;
|
||||||
|
word_to_read_X[word_idx].supply = supply;
|
||||||
|
|
||||||
|
|
||||||
|
(bit_idx:wl:
|
||||||
|
// Describing all the FF and their connection
|
||||||
|
val_chck[bit_idx].a = _in_v_temp_buf[word_idx+bit_idx];
|
||||||
|
val_chck[bit_idx].b = in.d.d[bit_idx].t;
|
||||||
|
val_chck[bit_idx].y = _val_chck_out[bit_idx];
|
||||||
|
val_chck[bit_idx].vdd = supply.vdd;
|
||||||
|
val_chck[bit_idx].vss = supply.vss;
|
||||||
|
ff[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx];
|
||||||
|
ff[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].t;
|
||||||
|
ff[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx];
|
||||||
|
ff[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)];
|
||||||
|
ff[bit_idx+word_idx*(wl)].vdd = supply.vdd;
|
||||||
|
ff[bit_idx+word_idx*(wl)].vss = supply.vss;
|
||||||
|
// READ: creating the selectors for propagating the right word
|
||||||
|
word_to_read_X[word_idx].out[bit_idx] = word_selector_t[bit_idx+(word_idx*(wl))].a;
|
||||||
|
word_to_read_X[word_idx].out[bit_idx+wl] = word_selector_f[bit_idx+(word_idx*(wl))].a;
|
||||||
|
word_selector_t[bit_idx+word_idx*(wl)].b = ff[bit_idx+(word_idx*(wl))].q;
|
||||||
|
word_selector_t[bit_idx+word_idx*(wl)].y = bitselector_t[bit_idx].in[word_idx];
|
||||||
|
word_selector_f[bit_idx+word_idx*(wl)].b = ff[bit_idx+(word_idx*(wl))].q_B;
|
||||||
|
word_selector_f[bit_idx+word_idx*(wl)].y = bitselector_f[bit_idx].in[word_idx];
|
||||||
|
bitselector_t[bit_idx].out = output_buf.in.d.d[bit_idx].t;
|
||||||
|
bitselector_f[bit_idx].out = output_buf.in.d.d[bit_idx].f;
|
||||||
|
bitselector_t[bit_idx].supply = supply;
|
||||||
|
bitselector_f[bit_idx].supply = supply;
|
||||||
|
)
|
||||||
|
)
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
@ -85,8 +299,8 @@ BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
|
|||||||
|
|
||||||
//function
|
//function
|
||||||
bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B,_en_X_t[N],_en_X_f[N];
|
bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B,_en_X_t[N],_en_X_f[N];
|
||||||
A_1C2N_SB_X4 f_buf_func[N];
|
A_1C2N_RB_X4 f_buf_func[N];
|
||||||
A_1C2N_RB_X4 t_buf_func[N];
|
A_1C2N_SB_X4 t_buf_func[N];
|
||||||
sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
|
sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
|
||||||
sigbuf<N> en_buf_f(.in=_en, .out=_en_X_f, .supply=supply);
|
sigbuf<N> en_buf_f(.in=_en, .out=_en_X_f, .supply=supply);
|
||||||
// INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
|
// INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
|
||||||
@ -111,10 +325,10 @@ sigbuf<N> en_buf_f(.in=_en, .out=_en_X_f, .supply=supply);
|
|||||||
t_buf_func[i].vdd=supply.vdd;
|
t_buf_func[i].vdd=supply.vdd;
|
||||||
f_buf_func[i].vss=supply.vss;
|
f_buf_func[i].vss=supply.vss;
|
||||||
t_buf_func[i].vss=supply.vss;
|
t_buf_func[i].vss=supply.vss;
|
||||||
f_buf_func[i].pr = _reset;
|
t_buf_func[i].pr = _reset;
|
||||||
f_buf_func[i].sr = _reset;
|
t_buf_func[i].sr = _reset;
|
||||||
t_buf_func[i].pr_B = _reset_BXX[i];
|
f_buf_func[i].pr_B = _reset_BXX[i];
|
||||||
t_buf_func[i].sr_B = _reset_BXX[i];
|
f_buf_func[i].sr_B = _reset_BXX[i];
|
||||||
)
|
)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
@ -1,117 +0,0 @@
|
|||||||
/*************************************************************************
|
|
||||||
*
|
|
||||||
* This file is part of ACT dataflow neuro library.
|
|
||||||
* It's the testing facility for cell_lib_std.act
|
|
||||||
*
|
|
||||||
* Copyright (c) 2022 University of Groningen - Ole Richter
|
|
||||||
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
|
|
||||||
* Copyright (c) 2022 University of Groningen - Michele Mastella
|
|
||||||
* Copyright (c) 2022 University of Groningen - Madison Cotteret
|
|
||||||
*
|
|
||||||
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
|
|
||||||
*
|
|
||||||
* You may redistribute and modify this documentation and make products
|
|
||||||
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
|
|
||||||
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
|
|
||||||
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
|
|
||||||
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
|
|
||||||
* for applicable conditions.
|
|
||||||
*
|
|
||||||
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
|
|
||||||
*
|
|
||||||
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
|
|
||||||
* these sources, You must maintain the Source Location visible in its
|
|
||||||
* documentation.
|
|
||||||
*
|
|
||||||
**************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
import "../../dataflow_neuro/coders.act";
|
|
||||||
import "../../dataflow_neuro/primitives.act";
|
|
||||||
import "../../dataflow_neuro/chips.act";
|
|
||||||
|
|
||||||
import globals;
|
|
||||||
import std::data;
|
|
||||||
|
|
||||||
open std::data;
|
|
||||||
|
|
||||||
|
|
||||||
open tmpl::dataflow_neuro;
|
|
||||||
|
|
||||||
defproc chip_texel_in30 (bd<30> in; bd<30> out; Mx1of2<22> reg_data[64];
|
|
||||||
bool? nrn_mon_x[4], nrn_mon_y[8], syn_mon_x[4], syn_mon_y[8];
|
|
||||||
bool? bd_dly_cfg[4], bd_dly_cfg2[2], loopback_en){
|
|
||||||
|
|
||||||
bool _reset_B;
|
|
||||||
prs {
|
|
||||||
Reset => _reset_B-
|
|
||||||
}
|
|
||||||
power supply;
|
|
||||||
supply.vdd = Vdd;
|
|
||||||
supply.vss = GND;
|
|
||||||
|
|
||||||
pint N_IN = 30;
|
|
||||||
|
|
||||||
pint N_NRN_X = 4;
|
|
||||||
pint N_NRN_Y = 8;
|
|
||||||
// pint NC_NRN_X = std:ceil_log2(N_NRN_X);
|
|
||||||
// pint NC_NRN_Y = std:ceil_log2(N_NRN_Y);
|
|
||||||
pint NC_NRN_X = 2;
|
|
||||||
pint NC_NRN_Y = 3;
|
|
||||||
|
|
||||||
pint N_SYN_X = 4;
|
|
||||||
pint N_SYN_Y = 8;
|
|
||||||
// pint NC_SYN_X = std:ceil_log2(N_SYN_X);
|
|
||||||
// pint NC_SYN_Y = std:ceil_log2(N_SYN_Y);
|
|
||||||
pint NC_SYN_X = 2;
|
|
||||||
pint NC_SYN_Y = 3;
|
|
||||||
|
|
||||||
pint N_SYN_DLY_CFG = 4;
|
|
||||||
pint N_BD_DLY_CFG = 4;
|
|
||||||
pint N_BD_DLY_CFG2 = 2;
|
|
||||||
|
|
||||||
pint N_NRN_MON_X = 4;
|
|
||||||
pint N_NRN_MON_Y = 8;
|
|
||||||
pint N_SYN_MON_X = 4;
|
|
||||||
pint N_SYN_MON_Y = 8;
|
|
||||||
|
|
||||||
pint N_BUFFERS = 3;
|
|
||||||
|
|
||||||
pint N_LINE_PD_DLY = 3;
|
|
||||||
|
|
||||||
pint REG_NCA = 6;
|
|
||||||
pint REG_M = 1<<REG_NCA;
|
|
||||||
pint REG_NCW = 22;
|
|
||||||
|
|
||||||
chip_texel<N_IN,
|
|
||||||
N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,
|
|
||||||
NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
|
|
||||||
N_SYN_DLY_CFG,
|
|
||||||
N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
|
|
||||||
N_BUFFERS,
|
|
||||||
N_LINE_PD_DLY,
|
|
||||||
N_BD_DLY_CFG, N_BD_DLY_CFG2,
|
|
||||||
REG_NCA, REG_NCW, REG_M> c(.in = in, .out = out, .reg_data = reg_data,
|
|
||||||
.nrn_mon_x = nrn_mon_x, .nrn_mon_y = nrn_mon_y,
|
|
||||||
.syn_mon_x = syn_mon_x, .syn_mon_y = syn_mon_y,
|
|
||||||
.bd_dly_cfg = bd_dly_cfg, .bd_dly_cfg2 = bd_dly_cfg2, .loopback_en = loopback_en,
|
|
||||||
.reset_B = _reset_B, .supply = supply);
|
|
||||||
|
|
||||||
// Spawn in some buffers as a conduit between neurons and synapses.
|
|
||||||
pint N_SYNS = N_SYN_X * N_SYN_Y;
|
|
||||||
BUF_X4 syn2nrns_r[N_SYNS];
|
|
||||||
BUF_X4 syn2nrns_a[N_SYNS];
|
|
||||||
(i:N_SYNS:
|
|
||||||
syn2nrns_r[i].a = c.synapses[i].r;
|
|
||||||
syn2nrns_r[i].y = c.neurons[i].r;
|
|
||||||
|
|
||||||
syn2nrns_a[i].a = c.neurons[i].a;
|
|
||||||
syn2nrns_a[i].y = c.synapses[i].a;
|
|
||||||
)
|
|
||||||
// c.synapses = c.neurons; // Connect each synapse hs to a neuron hs
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
// fifo_decoder_neurons_encoder_fifo e;
|
|
||||||
chip_texel_in30 c;
|
|
||||||
@ -1,157 +0,0 @@
|
|||||||
watchall
|
|
||||||
|
|
||||||
|
|
||||||
set c.bd_dly_cfg[0] 1
|
|
||||||
set c.bd_dly_cfg[1] 1
|
|
||||||
set c.bd_dly_cfg[2] 1
|
|
||||||
set c.bd_dly_cfg[3] 1
|
|
||||||
|
|
||||||
set c.bd_dly_cfg2[0] 1
|
|
||||||
set c.bd_dly_cfg2[1] 1
|
|
||||||
|
|
||||||
set-bd-channel-neutral "c.in" 30
|
|
||||||
set c.out.a 0
|
|
||||||
set c.loopback_en 1
|
|
||||||
set Reset 1
|
|
||||||
|
|
||||||
cycle
|
|
||||||
|
|
||||||
mode run
|
|
||||||
status X
|
|
||||||
system "echo '[] Set reset 0'"
|
|
||||||
status X
|
|
||||||
set Reset 0
|
|
||||||
cycle
|
|
||||||
|
|
||||||
# Reading address 0
|
|
||||||
set-bd-data-valid "c.in" 30 536870912
|
|
||||||
cycle
|
|
||||||
set c.in.r 1
|
|
||||||
cycle
|
|
||||||
assert c.in.a 1
|
|
||||||
|
|
||||||
|
|
||||||
# Remove input
|
|
||||||
set-bd-channel-neutral "c.in" 30
|
|
||||||
cycle
|
|
||||||
assert c.in.a 0
|
|
||||||
|
|
||||||
# Should first get loopback
|
|
||||||
assert-bd-channel-valid "c.out" 30 536870912
|
|
||||||
set c.out.a 1
|
|
||||||
cycle
|
|
||||||
assert-bd-channel-neutral "c.out" 30
|
|
||||||
set c.out.a 0
|
|
||||||
cycle
|
|
||||||
|
|
||||||
# Expect register read packet to arrive
|
|
||||||
# Receiving output 0 from register 0
|
|
||||||
assert-bd-channel-valid "c.out" 30 0
|
|
||||||
set c.out.a 1
|
|
||||||
cycle
|
|
||||||
assert-bd-channel-neutral "c.out" 30
|
|
||||||
set c.out.a 0
|
|
||||||
cycle
|
|
||||||
|
|
||||||
# Disable loopback cus it's annoying
|
|
||||||
set c.loopback_en 0
|
|
||||||
cycle
|
|
||||||
|
|
||||||
# Enables hs, disable synapse delays
|
|
||||||
# Writing 255 to address 0
|
|
||||||
set-bd-data-valid "c.in" 30 805322688
|
|
||||||
cycle
|
|
||||||
set c.in.r 1
|
|
||||||
cycle
|
|
||||||
assert c.in.a 1
|
|
||||||
|
|
||||||
|
|
||||||
# Remove input
|
|
||||||
set-bd-channel-neutral "c.in" 30
|
|
||||||
cycle
|
|
||||||
assert c.in.a 0
|
|
||||||
|
|
||||||
# Sending spike to synapse [2,3]
|
|
||||||
set-bd-data-valid "c.in" 30 8
|
|
||||||
cycle
|
|
||||||
set c.in.r 1
|
|
||||||
cycle
|
|
||||||
assert c.in.a 1
|
|
||||||
|
|
||||||
# Receiving output spike [2,3]
|
|
||||||
assert-bd-channel-valid "c.out" 30 8
|
|
||||||
set c.out.a 1
|
|
||||||
cycle
|
|
||||||
assert-bd-channel-neutral "c.out" 30
|
|
||||||
set c.out.a 0
|
|
||||||
cycle
|
|
||||||
|
|
||||||
# Remove input
|
|
||||||
set-bd-channel-neutral "c.in" 30
|
|
||||||
cycle
|
|
||||||
assert c.in.a 0
|
|
||||||
|
|
||||||
|
|
||||||
# Writing 3 to address 1 (enable targeting)
|
|
||||||
set-bd-data-valid "c.in" 30 805306561
|
|
||||||
cycle
|
|
||||||
set c.in.r 1
|
|
||||||
cycle
|
|
||||||
assert c.in.a 1
|
|
||||||
|
|
||||||
# Remove input
|
|
||||||
set-bd-channel-neutral "c.in" 30
|
|
||||||
cycle
|
|
||||||
assert c.in.a 0
|
|
||||||
|
|
||||||
# Writing 511 to address 2 (change nrn targ)
|
|
||||||
set-bd-data-valid "c.in" 30 805339074
|
|
||||||
cycle
|
|
||||||
set c.in.r 1
|
|
||||||
cycle
|
|
||||||
assert c.in.a 1
|
|
||||||
|
|
||||||
assert c.nrn_mon_x[0] 0
|
|
||||||
assert c.nrn_mon_x[1] 0
|
|
||||||
assert c.nrn_mon_x[2] 0
|
|
||||||
assert c.nrn_mon_x[3] 1
|
|
||||||
|
|
||||||
assert c.nrn_mon_y[0] 0
|
|
||||||
assert c.nrn_mon_y[1] 0
|
|
||||||
assert c.nrn_mon_y[2] 0
|
|
||||||
assert c.nrn_mon_y[3] 0
|
|
||||||
assert c.nrn_mon_y[4] 0
|
|
||||||
assert c.nrn_mon_y[5] 0
|
|
||||||
assert c.nrn_mon_y[6] 0
|
|
||||||
assert c.nrn_mon_y[7] 1
|
|
||||||
|
|
||||||
# Remove input
|
|
||||||
set-bd-channel-neutral "c.in" 30
|
|
||||||
cycle
|
|
||||||
assert c.in.a 0
|
|
||||||
|
|
||||||
# Writing 0 to address 1 (disable targetting)
|
|
||||||
set-bd-data-valid "c.in" 30 805306369
|
|
||||||
cycle
|
|
||||||
set c.in.r 1
|
|
||||||
cycle
|
|
||||||
assert c.in.a 1
|
|
||||||
|
|
||||||
assert c.nrn_mon_x[0] 0
|
|
||||||
assert c.nrn_mon_x[1] 0
|
|
||||||
assert c.nrn_mon_x[2] 0
|
|
||||||
assert c.nrn_mon_x[3] 0
|
|
||||||
|
|
||||||
assert c.nrn_mon_y[0] 0
|
|
||||||
assert c.nrn_mon_y[1] 0
|
|
||||||
assert c.nrn_mon_y[2] 0
|
|
||||||
assert c.nrn_mon_y[3] 0
|
|
||||||
assert c.nrn_mon_y[4] 0
|
|
||||||
assert c.nrn_mon_y[5] 0
|
|
||||||
assert c.nrn_mon_y[6] 0
|
|
||||||
assert c.nrn_mon_y[7] 0
|
|
||||||
|
|
||||||
# Remove input
|
|
||||||
set-bd-channel-neutral "c.in" 30
|
|
||||||
cycle
|
|
||||||
assert c.in.a 0
|
|
||||||
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
@ -1,107 +0,0 @@
|
|||||||
/*************************************************************************
|
|
||||||
*
|
|
||||||
* This file is part of ACT dataflow neuro library.
|
|
||||||
* It's the testing facility for cell_lib_std.act
|
|
||||||
*
|
|
||||||
* Copyright (c) 2022 University of Groningen - Ole Richter
|
|
||||||
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
|
|
||||||
* Copyright (c) 2022 University of Groningen - Michele Mastella
|
|
||||||
* Copyright (c) 2022 University of Groningen - Madison Cotteret
|
|
||||||
*
|
|
||||||
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
|
|
||||||
*
|
|
||||||
* You may redistribute and modify this documentation and make products
|
|
||||||
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
|
|
||||||
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
|
|
||||||
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
|
|
||||||
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
|
|
||||||
* for applicable conditions.
|
|
||||||
*
|
|
||||||
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
|
|
||||||
*
|
|
||||||
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
|
|
||||||
* these sources, You must maintain the Source Location visible in its
|
|
||||||
* documentation.
|
|
||||||
*
|
|
||||||
**************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
import "../../dataflow_neuro/coders.act";
|
|
||||||
import "../../dataflow_neuro/primitives.act";
|
|
||||||
import "../../dataflow_neuro/chips.act";
|
|
||||||
|
|
||||||
import globals;
|
|
||||||
import std::data;
|
|
||||||
|
|
||||||
open std::data;
|
|
||||||
|
|
||||||
|
|
||||||
open tmpl::dataflow_neuro;
|
|
||||||
|
|
||||||
defproc chip_texel_in30 (bd<30> in; bd<30> out; Mx1of2<22> reg_data[64];
|
|
||||||
a1of1 synapses[6];
|
|
||||||
a1of1 neurons[6];
|
|
||||||
bool? nrn_mon_x[4], nrn_mon_y[8], syn_mon_x[4], syn_mon_y[8];
|
|
||||||
bool? bd_dly_cfg[4], bd_dly_cfg2[2], loopback_en){
|
|
||||||
|
|
||||||
bool _reset_B;
|
|
||||||
prs {
|
|
||||||
Reset => _reset_B-
|
|
||||||
}
|
|
||||||
power supply;
|
|
||||||
supply.vdd = Vdd;
|
|
||||||
supply.vss = GND;
|
|
||||||
|
|
||||||
pint N_IN = 30;
|
|
||||||
|
|
||||||
pint N_NRN_X = 2;
|
|
||||||
pint N_NRN_Y = 3;
|
|
||||||
// pint NC_NRN_X = std:ceil_log2(N_NRN_X);
|
|
||||||
// pint NC_NRN_Y = std:ceil_log2(N_NRN_Y);
|
|
||||||
pint NC_NRN_X = 1;
|
|
||||||
pint NC_NRN_Y = 2;
|
|
||||||
|
|
||||||
pint N_SYN_X = 2;
|
|
||||||
pint N_SYN_Y = 3;
|
|
||||||
// pint NC_SYN_X = std:ceil_log2(N_SYN_X);
|
|
||||||
// pint NC_SYN_Y = std:ceil_log2(N_SYN_Y);
|
|
||||||
pint NC_SYN_X = 1;
|
|
||||||
pint NC_SYN_Y = 2;
|
|
||||||
|
|
||||||
pint N_SYN_DLY_CFG = 4;
|
|
||||||
pint N_BD_DLY_CFG = 4;
|
|
||||||
pint N_BD_DLY_CFG2 = 2;
|
|
||||||
|
|
||||||
pint N_NRN_MON_X = 4;
|
|
||||||
pint N_NRN_MON_Y = 8;
|
|
||||||
pint N_SYN_MON_X = 4;
|
|
||||||
pint N_SYN_MON_Y = 8;
|
|
||||||
|
|
||||||
pint N_BUFFERS = 3;
|
|
||||||
|
|
||||||
pint N_LINE_PD_DLY = 3;
|
|
||||||
|
|
||||||
pint REG_NCA = 6;
|
|
||||||
pint REG_M = 1<<REG_NCA;
|
|
||||||
pint REG_NCW = 22;
|
|
||||||
|
|
||||||
chip_texel<N_IN,
|
|
||||||
N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,
|
|
||||||
NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
|
|
||||||
N_SYN_DLY_CFG,
|
|
||||||
N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
|
|
||||||
N_BUFFERS,
|
|
||||||
N_LINE_PD_DLY,
|
|
||||||
N_BD_DLY_CFG, N_BD_DLY_CFG2,
|
|
||||||
REG_NCA, REG_NCW, REG_M> c(.in = in, .out = out, .reg_data = reg_data,
|
|
||||||
.synapses = synapses, .neurons = neurons,
|
|
||||||
.nrn_mon_x = nrn_mon_x, .nrn_mon_y = nrn_mon_y,
|
|
||||||
.syn_mon_x = syn_mon_x, .syn_mon_y = syn_mon_y,
|
|
||||||
.bd_dly_cfg = bd_dly_cfg, .bd_dly_cfg2 = bd_dly_cfg2, .loopback_en = loopback_en,
|
|
||||||
.reset_B = _reset_B, .supply = supply);
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
// fifo_decoder_neurons_encoder_fifo e;
|
|
||||||
chip_texel_in30 c;
|
|
||||||
@ -1,186 +0,0 @@
|
|||||||
watchall
|
|
||||||
|
|
||||||
|
|
||||||
set c.bd_dly_cfg[0] 1
|
|
||||||
set c.bd_dly_cfg[1] 1
|
|
||||||
set c.bd_dly_cfg[2] 1
|
|
||||||
set c.bd_dly_cfg[3] 1
|
|
||||||
|
|
||||||
set c.bd_dly_cfg2[0] 1
|
|
||||||
set c.bd_dly_cfg2[1] 1
|
|
||||||
|
|
||||||
set c.synapses[0].a 0
|
|
||||||
set c.synapses[1].a 0
|
|
||||||
set c.synapses[2].a 0
|
|
||||||
set c.synapses[3].a 0
|
|
||||||
set c.synapses[4].a 0
|
|
||||||
set c.synapses[5].a 0
|
|
||||||
|
|
||||||
set c.neurons[0].r 0
|
|
||||||
set c.neurons[1].r 0
|
|
||||||
set c.neurons[2].r 0
|
|
||||||
set c.neurons[3].r 0
|
|
||||||
set c.neurons[4].r 0
|
|
||||||
set c.neurons[5].r 0
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
set-bd-channel-neutral "c.in" 30
|
|
||||||
set c.out.a 0
|
|
||||||
set c.loopback_en 1
|
|
||||||
set Reset 1
|
|
||||||
|
|
||||||
cycle
|
|
||||||
|
|
||||||
mode run
|
|
||||||
status X
|
|
||||||
system "echo '[] Set reset 0'"
|
|
||||||
status X
|
|
||||||
set Reset 0
|
|
||||||
cycle
|
|
||||||
|
|
||||||
# Reading address 0
|
|
||||||
set-bd-data-valid "c.in" 30 536870912
|
|
||||||
cycle
|
|
||||||
set c.in.r 1
|
|
||||||
cycle
|
|
||||||
assert c.in.a 1
|
|
||||||
|
|
||||||
|
|
||||||
# Remove input
|
|
||||||
set-bd-channel-neutral "c.in" 30
|
|
||||||
cycle
|
|
||||||
assert c.in.a 0
|
|
||||||
|
|
||||||
# Should first get loopback
|
|
||||||
assert-bd-channel-valid "c.out" 30 536870912
|
|
||||||
set c.out.a 1
|
|
||||||
cycle
|
|
||||||
assert-bd-channel-neutral "c.out" 30
|
|
||||||
set c.out.a 0
|
|
||||||
cycle
|
|
||||||
|
|
||||||
# Expect register read packet to arrive
|
|
||||||
# Receiving output 0 from register 0
|
|
||||||
assert-bd-channel-valid "c.out" 30 0
|
|
||||||
set c.out.a 1
|
|
||||||
cycle
|
|
||||||
assert-bd-channel-neutral "c.out" 30
|
|
||||||
set c.out.a 0
|
|
||||||
cycle
|
|
||||||
|
|
||||||
# Disable loopback cus it's annoying
|
|
||||||
set c.loopback_en 0
|
|
||||||
cycle
|
|
||||||
|
|
||||||
# Enables hs, disable synapse delays
|
|
||||||
# Writing 255 to address 0
|
|
||||||
set-bd-data-valid "c.in" 30 805322688
|
|
||||||
cycle
|
|
||||||
set c.in.r 1
|
|
||||||
cycle
|
|
||||||
assert c.in.a 1
|
|
||||||
|
|
||||||
|
|
||||||
# Remove input
|
|
||||||
set-bd-channel-neutral "c.in" 30
|
|
||||||
cycle
|
|
||||||
assert c.in.a 0
|
|
||||||
|
|
||||||
# Sending spike to synapse [1,2]
|
|
||||||
set-bd-data-valid "c.in" 30 5
|
|
||||||
cycle
|
|
||||||
set c.in.r 1
|
|
||||||
cycle
|
|
||||||
assert c.in.a 1
|
|
||||||
|
|
||||||
assert c.synapses[5].r 1
|
|
||||||
set c.neurons[5].r 1
|
|
||||||
cycle
|
|
||||||
assert c.neurons[5].a 1
|
|
||||||
set c.synapses[5].a 1
|
|
||||||
cycle
|
|
||||||
assert c.synapses[5].r 0
|
|
||||||
set c.neurons[5].r 0
|
|
||||||
cycle
|
|
||||||
assert c.neurons[5].a 0
|
|
||||||
|
|
||||||
|
|
||||||
# Receiving output spike [1,2]
|
|
||||||
assert-bd-channel-valid "c.out" 30 5
|
|
||||||
set c.out.a 1
|
|
||||||
cycle
|
|
||||||
assert-bd-channel-neutral "c.out" 30
|
|
||||||
set c.out.a 0
|
|
||||||
cycle
|
|
||||||
|
|
||||||
|
|
||||||
# # Remove input
|
|
||||||
# set-bd-channel-neutral "c.in" 30
|
|
||||||
# cycle
|
|
||||||
# assert c.in.a 0
|
|
||||||
|
|
||||||
|
|
||||||
# # Writing 3 to address 1 (enable targeting)
|
|
||||||
# set-bd-data-valid "c.in" 30 805306561
|
|
||||||
# cycle
|
|
||||||
# set c.in.r 1
|
|
||||||
# cycle
|
|
||||||
# assert c.in.a 1
|
|
||||||
|
|
||||||
# # Remove input
|
|
||||||
# set-bd-channel-neutral "c.in" 30
|
|
||||||
# cycle
|
|
||||||
# assert c.in.a 0
|
|
||||||
|
|
||||||
# # Writing 511 to address 2 (change nrn targ)
|
|
||||||
# set-bd-data-valid "c.in" 30 805339074
|
|
||||||
# cycle
|
|
||||||
# set c.in.r 1
|
|
||||||
# cycle
|
|
||||||
# assert c.in.a 1
|
|
||||||
|
|
||||||
# assert c.nrn_mon_x[0] 0
|
|
||||||
# assert c.nrn_mon_x[1] 0
|
|
||||||
# assert c.nrn_mon_x[2] 0
|
|
||||||
# assert c.nrn_mon_x[3] 1
|
|
||||||
|
|
||||||
# assert c.nrn_mon_y[0] 0
|
|
||||||
# assert c.nrn_mon_y[1] 0
|
|
||||||
# assert c.nrn_mon_y[2] 0
|
|
||||||
# assert c.nrn_mon_y[3] 0
|
|
||||||
# assert c.nrn_mon_y[4] 0
|
|
||||||
# assert c.nrn_mon_y[5] 0
|
|
||||||
# assert c.nrn_mon_y[6] 0
|
|
||||||
# assert c.nrn_mon_y[7] 1
|
|
||||||
|
|
||||||
# # Remove input
|
|
||||||
# set-bd-channel-neutral "c.in" 30
|
|
||||||
# cycle
|
|
||||||
# assert c.in.a 0
|
|
||||||
|
|
||||||
# # Writing 0 to address 1 (disable targetting)
|
|
||||||
# set-bd-data-valid "c.in" 30 805306369
|
|
||||||
# cycle
|
|
||||||
# set c.in.r 1
|
|
||||||
# cycle
|
|
||||||
# assert c.in.a 1
|
|
||||||
|
|
||||||
# assert c.nrn_mon_x[0] 0
|
|
||||||
# assert c.nrn_mon_x[1] 0
|
|
||||||
# assert c.nrn_mon_x[2] 0
|
|
||||||
# assert c.nrn_mon_x[3] 0
|
|
||||||
|
|
||||||
# assert c.nrn_mon_y[0] 0
|
|
||||||
# assert c.nrn_mon_y[1] 0
|
|
||||||
# assert c.nrn_mon_y[2] 0
|
|
||||||
# assert c.nrn_mon_y[3] 0
|
|
||||||
# assert c.nrn_mon_y[4] 0
|
|
||||||
# assert c.nrn_mon_y[5] 0
|
|
||||||
# assert c.nrn_mon_y[6] 0
|
|
||||||
# assert c.nrn_mon_y[7] 0
|
|
||||||
|
|
||||||
# # Remove input
|
|
||||||
# set-bd-channel-neutral "c.in" 30
|
|
||||||
# cycle
|
|
||||||
# assert c.in.a 0
|
|
||||||
Loading…
Reference in New Issue
Block a user