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c8412606b3
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0e9f2ae506
@ -44,7 +44,7 @@ namespace tmpl {
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* Thus NxC should be something like NxC = ceil(log2(Nx))
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* but my guess is that we can't do logs...
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* N_dly_cfg is the number of config bits in the ACK delay line,
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* with all bits high corresponding to 2**N_dly_cfg -1 DLY4_X1 cells.
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* with all bits high corresponding to 2**N_dly_cfg -1 DLY1_X4 cells.
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*/
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export template<pint NxC, NyC, Nx, Ny, N_dly_cfg>
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defproc decoder_2d_dly (avMx1of2<NxC+NyC> in; bool? outx[Nx], outy[Ny],
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@ -212,20 +212,6 @@ namespace tmpl {
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}
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export template<pint Nx, Ny>
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defproc and_grid(bool! out[Nx*Ny]; bool? inx[Nx], iny[Ny]; power supply) {
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AND2_X1 ands[Nx*Ny];
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(i:0..Nx*Ny-1:ands[i].vss = supply.vss; ands[i].vdd = supply.vdd;)
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(x:0..Nx-1:
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(y:0..Ny-1:
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ands[x + y*Nx].a = inx[x];
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ands[x + y*Nx].b = iny[y];
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ands[x + y*Nx].y = out[x + y*Nx];
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)
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)
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}
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template<pint N, pint M, pint ACK_STRENGTH>
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defproc encoder2D(a1of1 x[N]; a1of1 y[M] ;avMx1of2<X> addr; bool! out_a; power supply)
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{
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@ -258,6 +244,8 @@ namespace tmpl {
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}
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}
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}
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@ -48,9 +48,6 @@ defproc ortree (bool? in[N]; bool! out; power supply)
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{ N > 0 : "What?" };
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[N = 1 -> BUF_X1 b(.vss=supply.vss, .vdd = supply.vdd, .a = in[0], .y = out);
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[] N > 1 ->
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pint i, end, j;
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i = 0;
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end = N-1;
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@ -151,8 +148,6 @@ defproc ortree (bool? in[N]; bool! out; power supply)
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]
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out = tmp[end];
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]
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}
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export template<pint N>
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@ -162,11 +157,6 @@ defproc andtree (bool? in[N]; bool! out; power supply)
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{ N > 0 : "What?" };
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[N = 1 -> BUF_X1 b(.vss=supply.vss, .vdd = supply.vdd, .a = in[0], .y = out);
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[] N > 1 ->
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pint i, end, j;
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i = 0;
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end = N-1;
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@ -267,8 +257,6 @@ defproc andtree (bool? in[N]; bool! out; power supply)
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]
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out = tmp[end];
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]
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}
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/*
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@ -282,10 +270,6 @@ defproc ctree (bool? in[N]; bool! out; power supply)
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{ N > 0 : "What?" };
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bool meaningless_var;
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[N = 1 -> BUF_X1 b(.vss=supply.vss, .vdd = supply.vdd, .a = in[0], .y = out);
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[] N > 1 ->
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pint i, end, j;
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i = 0;
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end = N-1;
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@ -389,11 +373,6 @@ defproc ctree (bool? in[N]; bool! out; power supply)
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]
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out = tmp[end];
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]
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}
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