dataflow_neuro/cell_lib_async.act

@@ -33,6 +33,11 @@ namespace tmpl {
                 [weak=1] _y -> y-
                 [weak=1] ~_y -> y+
 
+                }
+            sizing {
+                leak_adjust <- 1; 
+                p_n_mode <- 1;
+                y {-1}; _y{-1} 
                 }
         }
 
@@ -564,7 +569,6 @@ namespace tmpl {
             mk_excllo(_y1, _y2)
           }
         }
-        export
         defproc PULLDOWN_X4(bool? a; bool! y; bool? vdd, vss)
         {
         prs{
@@ -572,7 +576,6 @@ namespace tmpl {
         }
         }
 
-        export
         defproc PULLDOWN2_X4(bool? a, b; bool! y; bool? vdd, vss)
         {
         prs{
@@ -580,7 +583,6 @@ namespace tmpl {
         }
         }
         
-        export
         defproc PULLUP_X4(bool? a; bool! y; bool? vdd, vss)
         {
         prs{

dataflow_neuro/coders.act

@@ -190,7 +190,7 @@ namespace tmpl {
 
 			// Acknowledge pull down time
 
-			// Pull DOWNs on the reqB lines by synapses (easier to invert).
+			// Pull UPs on the reqB lines by synapses (easier to invert).
 			bool _out_reqsB[Nx], _out_acksB[Nx]; // The vertical output ack lines from each syn.
 			PULLDOWN2_X4 req_pulldowns[Nx*Ny];
 			pint index;
@@ -214,33 +214,23 @@ namespace tmpl {
 			)
 
 			// req-ack buffers
-			// Delay needed here, since otherwise the pull up of reqB happens too quickly.
-			// Means that the pull up may start fighting the synapse, 
-			// since the synapse has not yet retracted its ack.
-			// Also there is the possibility, if really fast, that the line pull up block
-			// doesn't yet see that the input is valid, and starts pulling up.
-			// In any case, this delay is important.
 			sigbuf<Ny> req_bufs[Nx];
-			delay_chain<N_dly> ack_delays[Nx];
 			(i:Nx:
-				ack_delays[i].in = _out_reqsB[i];
+				req_bufs[i].in = _out_reqsB[i];
-				ack_delays[i].supply = supply;
-
-				// req_bufs[i].in = _out_reqsB[i];
-				req_bufs[i].in = ack_delays[i].out;
 				req_bufs[i].out[0] = _out_acksB[i]; // DANGER DANGER
 				req_bufs[i].supply = supply;
-
-
-
 			)
 
 			// Line end pull UPs (triggered once synapse reqs removed)
+			delay_fifo<N_dly> pu_dlys[Nx];
 			OR2_X1 pu_ORs[Nx];
 			PULLUP_X4 pu[Nx]; // TODO probably replace this with variable strength PU
 			AND2_X1 pu_ANDs[Nx];
 			(i:Nx:
-				pu_ORs[i].a = _out_acksB[i];
+				pu_dlys[i].in = _out_acksB[i];
+				pu_dlys[i].supply = supply;
+
+				pu_ORs[i].a = pu_dlys[i].out;
 				pu_ORs[i].b = d_dr_x.out[i];
 				pu_ORs[i].vdd = supply.vdd;
 				pu_ORs[i].vss = supply.vss;
@@ -739,8 +729,8 @@ namespace tmpl {
 			// Create delay fifos to emulate the fact that the line pull downs
 			// are at the end of the line, and thus slow.
 			// Note that if N_dly = 0, delay fifo is just a pipe.
-			delay_chain<N_dly> dly_x[Nx];
+			delay_fifo<N_dly> dly_x[Nx];
-			delay_chain<N_dly> dly_y[Ny];	
+			delay_fifo<N_dly> dly_y[Ny];	
 			
 			// Create x line req pull downs
 			nrn_line_end_pull_down pd_x[Nx];

test/unit_tests/decoder_2d_hs/test.act

@@ -1,76 +0,0 @@
-/*************************************************************************
- *
- *  This file is part of ACT dataflow neuro library.
- * It's the testing facility for cell_lib_std.act
- *
- *  Copyright (c) 2022 University of Groningen - Ole Richter  
- *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
- *  Copyright (c) 2022 University of Groningen - Michele Mastella
- *  Copyright (c) 2022 University of Groningen - Madison Cotteret
- *
- *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
- *
- *  You may redistribute and modify this documentation and make products
- *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
- *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
- *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
- *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
- *  for applicable conditions.
- *
- *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
- *
- *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
- *  these sources, You must maintain the Source Location visible in its
- *  documentation.
- *
- **************************************************************************
- */
-
-import "../../dataflow_neuro/coders.act";
-import "../../dataflow_neuro/primitives.act";
-import "../../dataflow_neuro/cell_lib_async.act";
-import "../../dataflow_neuro/cell_lib_std.act";
-
-
-import globals;
-import std::data;
-
-open std::data;
-
-open tmpl::dataflow_neuro;
-
-defproc decoder_2d_hs_2x4 (avMx1of2<3> in; a1of1 out[8]){
-    bool _reset_B; 
-    prs {
-        Reset => _reset_B-
-    }
-    power supply;
-    supply.vdd = Vdd;
-    supply.vss = GND;
-
-    decoder_2d_hs<1,2,2,4,3> decoder(.in = in, .out = out,
-        .reset_B = _reset_B, .supply = supply);
-
-    // model the synapse as having automatic pulldown of ack.
-    // Needed since still have the timing assumption,
-    // that the synapse ack is pulled down pretty soon after its req is removed.
-    // Otherwise it starts fighting the line pull down.
-    INV_X1 synapses[8];
-    PULLDOWN_X4 synapses2[8];
-    (i:8:
-        synapses[i].a = decoder.out[i].r;
-        synapses2[i].a = synapses[i].y; 
-        synapses2[i].y = decoder.out[i].a;
-
-        synapses[i].vss = supply.vss;
-        synapses[i].vdd = supply.vdd;
-        synapses2[i].vss = supply.vss;
-        synapses2[i].vdd = supply.vdd;
-
-    )
-
-}
-
-
-// fifo_decoder_neurons_encoder_fifo e;
-decoder_2d_hs_2x4 e; 

test/unit_tests/decoder_2d_hs/test.prsim

@@ -1,153 +0,0 @@
-watchall
-
-set e.out[0].a 0
-set e.out[1].a 0
-set e.out[2].a 0
-set e.out[3].a 0
-set e.out[4].a 0
-set e.out[5].a 0
-set e.out[6].a 0
-set e.out[7].a 0
-
-set-qdi-channel-neutral "e.in" 3
-set Reset 1
-
-cycle
-
-mode run
-system "echo '[] Set reset 0'"
-status X
-set Reset 0
-cycle
-
-system "echo '[] Sending in a 7 packet'"
-set-qdi-channel-valid "e.in" 3 7
-cycle
-assert e.out[0].r 0
-assert e.out[1].r 0
-assert e.out[2].r 0
-assert e.out[3].r 0
-assert e.out[4].r 0
-assert e.out[5].r 0
-assert e.out[6].r 0
-assert e.out[7].r 1
-assert e.in.a 1
-assert e.in.v 1
-
-system "echo '[] Removing input'"
-set-qdi-channel-neutral "e.in" 3
-
-
-system "echo '[] Synapse [7] gives ack'"
-set e.out[7].a 1
-cycle
-assert e.out[0].r 0
-assert e.out[1].r 0
-assert e.out[2].r 0
-assert e.out[3].r 0
-assert e.out[4].r 0
-assert e.out[5].r 0
-assert e.out[6].r 0
-assert e.out[7].r 0
-assert e.in.a 0
-assert e.in.v 0
-assert e.out[0].a 0
-assert e.out[1].a 0
-assert e.out[2].a 0
-assert e.out[3].a 0
-assert e.out[4].a 0
-assert e.out[5].a 0
-assert e.out[6].a 0
-assert e.out[7].a 0
-
-
-
-
-
-system "echo '[] Sending in a 5 packet'"
-set-qdi-channel-valid "e.in" 3 5
-cycle
-assert e.out[0].r 0
-assert e.out[1].r 0
-assert e.out[2].r 0
-assert e.out[3].r 0
-assert e.out[4].r 0
-assert e.out[5].r 1
-assert e.out[6].r 0
-assert e.out[7].r 0
-assert e.in.a 1
-assert e.in.v 1
-
-system "echo '[] Removing input'"
-set-qdi-channel-neutral "e.in" 3
-
-
-system "echo '[] Synapse [5] gives ack'"
-set e.out[5].a 1
-cycle
-assert e.out[0].r 0
-assert e.out[1].r 0
-assert e.out[2].r 0
-assert e.out[3].r 0
-assert e.out[4].r 0
-assert e.out[5].r 0
-assert e.out[6].r 0
-assert e.out[7].r 0
-assert e.in.a 0
-assert e.in.v 0
-assert e.out[0].a 0
-assert e.out[1].a 0
-assert e.out[2].a 0
-assert e.out[3].a 0
-assert e.out[4].a 0
-assert e.out[5].a 0
-assert e.out[6].a 0
-assert e.out[7].a 0
-
-
-
-system "echo '[] Sending in a 1 packet'"
-set-qdi-channel-valid "e.in" 3 1
-cycle
-assert e.out[0].r 0
-assert e.out[1].r 1
-assert e.out[2].r 0
-assert e.out[3].r 0
-assert e.out[4].r 0
-assert e.out[5].r 0
-assert e.out[6].r 0
-assert e.out[7].r 0
-assert e.in.a 1
-assert e.in.v 1
-
-
-system "echo '[] Synapse [5] gives ack'"
-set e.out[1].a 1
-cycle
-assert e.out[0].r 0
-assert e.out[1].r 0
-assert e.out[2].r 0
-assert e.out[3].r 0
-assert e.out[4].r 0
-assert e.out[5].r 0
-assert e.out[6].r 0
-assert e.out[7].r 0
-
-assert e.out[0].a 0
-assert e.out[1].a 0
-assert e.out[2].a 0
-assert e.out[3].a 0
-assert e.out[4].a 0
-assert e.out[5].a 0
-assert e.out[6].a 0
-assert e.out[7].a 0
-
-assert e.in.a 1
-assert e.in.v 1
-
-system "echo '[] Removing input'"
-set-qdi-channel-neutral "e.in" 3
-cycle
-assert e.in.a 0
-assert e.in.v 0
-