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Author SHA1 Message Date
Michele 4dcd975554 register_rw continued 2022-03-09 20:02:41 +01:00
Michele 6f1a970cfd register_rw (formerly register_rw_v2) compiles 2022-03-09 16:44:44 +01:00
5 changed files with 2733 additions and 19 deletions
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84
dataflow_neuro/registers.act
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@ -39,7 +39,7 @@ open std::channel;
namespace tmpl {
namespace dataflow_neuro {
// Circuit for storing, reading and writing registers using AER
// Circuit for storing registers using AER
// The block has the parameters:
// lognw -> log2(number of words), parameters you can store
// wl -> word length, length of each word
@ -51,7 +51,7 @@ namespace tmpl {
// - the last wl the word to write
// data -> the data saved in the flip flop, sized wl x nw
export template<pint lognw,wl,N_dly_cfg>
defproc register_rw (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
defproc register_w (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
bool _in_v_temp,_in_a_temp,_clock_temp,_clock,_clock_temp_inv;
pint nw = 1<<lognw;
//Validation of the input
@ -110,40 +110,63 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power sup
)
)
}
// Circuit for storing and reading registers using AER
// The block has the parameters:
// lognw -> log2(number of words), parameters you can store
// wl -> word length, length of each word
// N_dly_cfg -> the number of config bits in the ACK delay line
// The block has the pins:
// in -> input data,
// - the MSB is write/read_B
// - the next MSB bits (size lognw) are the location,
// - the LSB (size wl) are the word to write
// out -> in case a reading phase is required, the output is used to show the stored data
// - the MSB bits (size lognw) tell the read register
// - the LSB bits (size wl) tell the word read
// data -> the data saved in the flip flop, sized wl x nw
export template<pint lognw,wl,N_dly_cfg>
defproc register_rw_v2 (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
bool _in_v_temp,_in_a_temp,_clock_temp,_clock,_clock_temp_inv;
bool _ff_v;
pint nw = 1<<lognw;
//Validation of the input
avMx1of2<lognw+wl> _in_temp2,_in_read,_in_write;
avMx1of2<1>_in_flag;
// bool _in_stable;
// (i:1+lognw+wl:_in_temp.d[i] = in.d.d[i];)
// vtree<1+lognw+wl> val_input(.in = _in_temp,.out = _in_v_temp, .supply = supply);
// sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
// Read or write?
AND2_X1 ack_and(.a = _in_temp2.a,.b = _in_flag.a,.y = in.a,.vdd = supply.vdd,.vss = supply.vss);
AND2_X1 ack_and(.a = _in_temp2.a,.b = _ff_v,.y = in.a,.vdd = supply.vdd,.vss = supply.vss);
in.v = _in_temp2.v;
_in_flag.d.d[0] = in.d.d[lognw+wl];
(i:lognw+wl:_in_temp2.d.d[i] = in.d.d[i];)
demux<lognw+wl> read_write_demux(.in = _in_temp2,.out1 = _in_write, .out2 = _in_read, .cond = _in_flag,.reset_B = reset_B);
demux<lognw+wl> read_write_demux(.in = _in_temp2,.out1 = _in_read, .out2 = _in_write, .cond = _in_flag,.reset_B = reset_B);
read_write_demux.supply= supply;
//WRITE PATH
// Validation
vtree<lognw+wl> val_input(.in = _in_write,.out = _in_write.v, .supply = supply);
vtree<wl>
Mx1of2<lognw+wl> _in_write_temp;
(i:lognw+wl:_in_write_temp.d[i] = _in_write.d.d[i];)
vtree<lognw+wl> val_input_write(.in = _in_write_temp,.out = _in_write.v, .supply = supply);
// Acknowledgment
//delayprog<N_dly_cfg> ack_dly(.in = _clock, .out = _in_write.a,.s = dly_cfg, .supply = supply);
// Generation of the fake clock pulse (inverted because the ff clocks are low_active)
delayprog<N_dly_cfg> clk_dly(.in = _in_write.v, .out = _clock_temp,.s = dly_cfg, .supply = supply);
INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
sigbuf_1output<4> clk_X(.in = _clock_temp_inv,.out = _clock,.supply = supply);
//READ PATH
//Validation
vtree<lognw+wl> val_input(.in = _in_read,.out = _in_read.v, .supply = supply);
// Sending signal to the output
Mx1of2<lognw+wl> _in_read_temp;
(i:lognw+wl:_in_read_temp.d[i] = _in_read.d.d[i];)
vtree<lognw+wl> val_input_read(.in = _in_read_temp,.out = _in_read.v, .supply = supply);
vtree<wl> ff_validator;
Mx1of2<wl> _out_temp;
(i:wl:_out_temp.d[i] = out.d.d[i];)
ff_validator.in = _out_temp;
ff_validator.out = _ff_v;
ff_validator.supply = supply;
// Acknowledgment
_in_read.a = _ff_v; //The circuit is ack when flip flop data are valid
//Reset Buffers
bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[nw*wl];
bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[nw*wl*2];
BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<nw*wl*2> reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
@ -152,8 +175,13 @@ defproc register_rw_v2 (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power
andtree<lognw> atree[nw];
d1of<wl> _data_f;
AND2_X1 and_encoder[nw];
AND3_X1 reading_activator_t[nw*wl],reading_activator_f[nw*wl];
sigbuf<wl*2> clock_buffer[nw];
DFFQ_R_X1 ff_t[2*nw*wl],ff_f[2*nw*wl];
DFFQ_R_X1 ff_t[nw*wl],ff_f[nw*wl];
OR2_X1 ff_val[wl];
(i:wl..lognw:out.d.d[i] = in.d.d[i];)
bool __ffout_dualrail[nw*wl];
pint bitval;
(k:nw:atree[k].supply = supply;)
(word_idx:nw:
@ -167,8 +195,11 @@ defproc register_rw_v2 (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power
[]bitval >= 2 -> {false : "fuck"};
]
)
// Activating the fake clock for the right word
// Encode which work is the right one
atree[word_idx].out = _out_encoder[word_idx];
// READ: use the encoder selection to read the value
// WRITE: Activating the fake clock for the right word
and_encoder[word_idx].a = _out_encoder[word_idx];
and_encoder[word_idx].b = _clock;
and_encoder[word_idx].y = _clock_word_temp[word_idx];
@ -184,12 +215,27 @@ defproc register_rw_v2 (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power
ff_t[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)];
ff_t[bit_idx+word_idx*(wl)].vdd = supply.vdd;
ff_t[bit_idx+word_idx*(wl)].vss = supply.vss;
ff_f[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx+nw-1].out[bit_idx];
ff_f[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx+wl-1];
ff_f[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].f;
ff_f[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx];
ff_f[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)+nw-1];
ff_f[bit_idx+word_idx*(wl)].vdd = supply.vdd;
ff_f[bit_idx+word_idx*(wl)].vss = supply.vss;
reading_activator_t[bit_idx+word_idx*(wl)].a = _in_flag.d.d[0].t;
reading_activator_t[bit_idx+word_idx*(wl)].b = ff_t[bit_idx+word_idx*(wl)].q;
reading_activator_t[bit_idx+word_idx*(wl)].c = _out_encoder[word_idx];
reading_activator_t[bit_idx+word_idx*(wl)].y = out.d.d[bit_idx].t;
reading_activator_t[bit_idx+word_idx*(wl)].vdd = supply.vdd;
reading_activator_t[bit_idx+word_idx*(wl)].vss = supply.vss;
reading_activator_f[bit_idx+word_idx*(wl)].a = _in_flag.d.d[0].f;
reading_activator_f[bit_idx+word_idx*(wl)].b = ff_f[bit_idx+word_idx*(wl)].q;
reading_activator_f[bit_idx+word_idx*(wl)].y = out.d.d[bit_idx].f;
reading_activator_f[bit_idx+word_idx*(wl)].vdd = supply.vdd;
reading_activator_f[bit_idx+word_idx*(wl)].vss = supply.vss;
reading_activator_f[bit_idx+word_idx*(wl)].c = _out_encoder[word_idx];
)
)
}

243
test/unit_tests/register_wrw/run/prsim.out Normal file
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@ -0,0 +1,243 @@
t.registers.read_write_demux.vc.ct.in[0] t.registers.ff_f[4].clk_B t.registers._clock_word_temp[0] t.registers._clock_temp_inv t.registers._clock t.dly_cfg[1] t.registers.atree[2].in[1] t.registers.read_write_demux._in_v t.registers.read_write_demux._c_v t.registers.reading_activator_f[0].a t.registers.ff_t[0].d t.registers.ff_f[4].__clk_B t.registers.ff_t[0]._clk_B t.registers.ff_f[5]._clk_B t.registers.atree[0].in[1] t.registers.atree[0].in[0] t.registers.ff_f[6].clk_B t.registers.clock_buffer[1].buf1._y t.registers._out_encoder[2] t.registers._out_encoder[1] t.registers.clk_dly.and2[1]._y t.registers.ff_t[1]._clk_B t.registers.ff_f[0].d t.registers.atree[1].in[0] t.in.v t.registers.ff_t[4]._clk_B t.registers.ff_t[1].d t.registers.ff_f[0].clk_B t.registers.read_write_demux._c_t_buf[0] t.registers.clk_dly.dly[1].a t.registers._clock_word_temp[3] t.registers.read_write_demux._out2_a_BX_t[0] t.registers.ff_val[1].y t.registers.read_write_demux._out2_a_BX_f[0] t.registers.clock_buffer[0].buf1._y t.registers._out_encoder[0] t.registers.ff_f[1].d t.registers.ff_t[5]._clk_B t.registers.ff_t[4].__clk_B t.registers.reading_activator_t[0].a t.registers.clk_X.buf1._y t.registers.read_write_demux._c_f_buf[0] t.registers._clock_temp t.registers.read_write_demux.out2_a_B_buf_f.buf1._y t.registers._out_encoder[3] t.registers.read_write_demux.vc.ct.in[1] t.registers.clk_dly.dly[1]._y t.registers.read_write_demux.c_f_c_t_or._y t.registers.ff_t[0].__clk_B t.registers.ff_t[2]._clk_B t.registers.ff_val[1]._y t.registers.read_write_demux.vc.ct.in[2] t.registers._clock_word_temp[1] t.registers.clk_dly.mu2[0]._s t.registers.clock_buffer[2].buf1._y t.registers.ff_t[1].__clk_B t.registers.read_write_demux.in_v_buf._y t.registers.clk_dly.dly[1].__y t.registers.ff_f[7]._clk_B t.registers.clk_dly.mu2[0]._y t.registers.clock_buffer[3].buf1._y t.registers.read_write_demux._out2_a_B t.dly_cfg[0] t.registers.and_encoder[0]._y t.registers.clk_dly._a[1] t.registers.read_write_demux._in_c_v_ t.registers.ff_f[2].__clk_B t.registers.read_write_demux.vc.ct.in[3] t.registers.clk_dly.dly[2].__y t.registers.atree[3].and2s[0]._y t.registers.read_write_demux.vc.ct.tmp[4] t.registers.read_write_demux.c_el._y t.registers.ff_f[7].__clk_B t.registers.read_write_demux.vc.OR2_tf[2]._y t.registers._clock_word_temp[2] t.registers.atree[2].and2s[0]._y t.registers.ff_f[0].__clk_B t.registers._in_write.a t.registers.ff_val[0].y t.registers.ff_t[6]._clk_B t.registers.read_write_demux.vc.ct.C2Els[1]._y t.registers.ff_f[4]._clk_B t.registers.read_write_demux.vc.OR2_tf[0]._y t.registers.clk_dly.dly[2].___y t.registers.read_write_demux.vc.ct.C2Els[2]._y t.registers.ff_f[2].clk_B t.registers.read_write_demux.out2_a_B_buf_t.buf1._y t.registers.clk_dly.dly[2]._y t.registers.ff_val[0].b t.registers.read_write_demux.vc.ct.tmp[5] t.registers.read_write_demux.vc.ct.C2Els[0]._y t.registers.clk_dly.dly[1].y t.registers.ff_f[2]._clk_B t.registers.clk_dly.dly[2].y t.registers.read_write_demux.c_buf_f.buf1._y t.registers.ff_val[1].b t.registers.ff_val[0].a t.registers.ff_t[2].__clk_B t.registers.atree[1].and2s[0]._y t.registers.ff_f[3].__clk_B t.registers.ff_f[6].__clk_B t.registers.and_encoder[2]._y t.registers.ff_f[6]._clk_B t.registers.clk_dly.dly[1].___y t.registers.clk_dly.mu2[1]._s t.registers.ff_f[0]._clk_B t.registers.read_write_demux.c_buf_t.buf1._y t.registers.ff_val[1].a t.registers.ff_t[3]._clk_B t.registers.atree[0].and2s[0]._y t.registers.clk_dly.mu2[1]._y t.registers.ff_f[1]._clk_B t.registers.ff_val[0]._y t.registers.ff_t[7].__clk_B t.registers.ff_t[7]._clk_B t.registers.read_write_demux.vc.OR2_tf[1]._y t.registers.ff_f[5].__clk_B t.registers.ff_f[1].__clk_B t.registers.and_encoder[1]._y t.registers.ff_t[5].__clk_B t.registers.ff_t[6].__clk_B t.registers.and_encoder[3]._y t.registers.read_write_demux.vc.OR2_tf[3]._y t.registers.ff_t[3].__clk_B t.registers.ff_f[3]._clk_B
[0] start test
----------------------------------------------------------
t.registers._clock_temp_inv t.registers._clock t.dly_cfg[1] t.registers.clk_dly.and2[1]._y t.registers.clk_dly.dly[1].a t.registers.read_write_demux._out2_a_BX_t[0] t.registers.ff_val[1].y t.registers.read_write_demux._out2_a_BX_f[0] t.registers.clk_X.buf1._y t.registers._clock_temp t.registers.read_write_demux.out2_a_B_buf_f.buf1._y t.registers.clk_dly.dly[1]._y t.registers.ff_val[1]._y t.registers.clk_dly.mu2[0]._s t.registers.clk_dly.dly[1].__y t.registers.clk_dly.mu2[0]._y t.registers.read_write_demux._out2_a_B t.dly_cfg[0] t.registers.clk_dly._a[1] t.registers.clk_dly.dly[2].__y t.registers._in_write.a t.registers.ff_val[0].y t.registers.clk_dly.dly[2].___y t.registers.read_write_demux.out2_a_B_buf_t.buf1._y t.registers.clk_dly.dly[2]._y t.registers.ff_val[0].b t.registers.clk_dly.dly[1].y t.registers.clk_dly.dly[2].y t.registers.ff_val[1].b t.registers.ff_val[0].a t.registers.clk_dly.dly[1].___y t.registers.clk_dly.mu2[1]._s t.registers.ff_val[1].a t.registers.clk_dly.mu2[1]._y t.registers.ff_val[0]._y
[1] reset completed
----------------------------------------------------------
[2] delay line set
----------------------------------------------------------
WARNING: weak-interference `t.registers._in_write_temp.d[0].t'
>> cause: t.registers.read_write_demux.out2_t_buf_func[0]._y (val: X)
>> time: 555402
WARNING: weak-interference `t.registers._in_write_temp.d[1].t'
>> cause: t.registers.read_write_demux.out2_t_buf_func[1]._y (val: X)
>> time: 555410
WARNING: weak-interference `t.registers._in_write_temp.d[2].f'
>> cause: t.registers.read_write_demux.out2_f_buf_func[2]._y (val: X)
>> time: 555426
WARNING: weak-interference `t.registers.val_input_write.OR2_tf[1]._y'
>> cause: t.registers._in_write_temp.d[1].t (val: X)
>> time: 555555
WARNING: weak-interference `t.registers.val_input_write.ct.in[1]'
>> cause: t.registers.val_input_write.OR2_tf[1]._y (val: X)
>> time: 555785
WARNING: weak-interference `t.registers.val_input_write.OR2_tf[0]._y'
>> cause: t.registers._in_write_temp.d[0].t (val: X)
>> time: 558923
WARNING: weak-interference `t.registers.val_input_write.ct.in[0]'
>> cause: t.registers.val_input_write.OR2_tf[0]._y (val: X)
>> time: 558937
WARNING: weak-interference `t.registers.val_input_write.ct.C2Els[0]._y'
>> cause: t.registers.val_input_write.ct.in[0] (val: X)
>> time: 560480
WARNING: weak-interference `t.registers.val_input_write.ct.tmp[4]'
>> cause: t.registers.val_input_write.ct.C2Els[0]._y (val: X)
>> time: 562091
WARNING: weak-interference `t.registers._in_write_temp.d[3].f'
>> cause: t.registers.read_write_demux.out2_f_buf_func[3]._y (val: X)
>> time: 565654
WARNING: weak-interference `t.registers.val_input_write.OR2_tf[3]._y'
>> cause: t.registers._in_write_temp.d[3].f (val: X)
>> time: 565665
WARNING: weak-interference `t.registers.val_input_write.ct.in[3]'
>> cause: t.registers.val_input_write.OR2_tf[3]._y (val: X)
>> time: 565666
WARNING: weak-interference `t.registers.val_input_write.OR2_tf[2]._y'
>> cause: t.registers._in_write_temp.d[2].f (val: X)
>> time: 571594
WARNING: weak-interference `t.registers.val_input_write.ct.in[2]'
>> cause: t.registers.val_input_write.OR2_tf[2]._y (val: X)
>> time: 578095
WARNING: weak-interference `t.registers.val_input_write.ct.C2Els[1]._y'
>> cause: t.registers.val_input_write.ct.in[2] (val: X)
>> time: 578734
WARNING: weak-interference `t.registers.val_input_write.ct.tmp[5]'
>> cause: t.registers.val_input_write.ct.C2Els[1]._y (val: X)
>> time: 580527
WARNING: weak-interference `t.registers.val_input_write.ct.C2Els[2]._y'
>> cause: t.registers.val_input_write.ct.tmp[5] (val: X)
>> time: 580659
WARNING: weak-interference `t.registers.clk_dly.in'
>> cause: t.registers.val_input_write.ct.C2Els[2]._y (val: X)
>> time: 580660
WARNING: weak-interference `t.registers.clk_dly.and2[0]._y'
>> cause: t.registers.clk_dly.in (val: X)
>> time: 580677
WARNING: weak-interference `t.registers.read_write_demux.out_or._y'
>> cause: t.registers.clk_dly.in (val: X)
>> time: 580677
WARNING: weak-interference `t.registers.clk_dly.dly[0].a'
>> cause: t.registers.clk_dly.and2[0]._y (val: X)
>> time: 580829
WARNING: weak-interference `t.registers.clk_dly.dly[0]._y'
>> cause: t.registers.clk_dly.dly[0].a (val: X)
>> time: 580832
WARNING: weak-interference `t.registers.clk_dly.dly[0].__y'
>> cause: t.registers.clk_dly.dly[0]._y (val: X)
>> time: 581256
WARNING: weak-interference `t.registers.clk_dly.dly[0].___y'
>> cause: t.registers.clk_dly.dly[0].__y (val: X)
>> time: 581262
WARNING: weak-interference `t.registers.read_write_demux._out_v'
>> cause: t.registers.read_write_demux.out_or._y (val: X)
>> time: 583660
WARNING: weak-interference `t.registers.clk_dly.dly[0].y'
>> cause: t.registers.clk_dly.dly[0].___y (val: X)
>> time: 583850
WARNING: weak-interference `t.registers.clk_dly.mu2[0]._y'
>> cause: t.registers.clk_dly.dly[0].y (val: X)
>> time: 584680
WARNING: weak-interference `t.registers.ack_and.a'
>> cause: t.registers.read_write_demux.inack_ctl._y (val: X)
>> time: 586123
WARNING: weak-interference `t.registers.read_write_demux._en'
>> cause: t.registers.ack_and.a (val: X)
>> time: 586317
WARNING: weak-interference `t.registers.read_write_demux.out2_en_buf_f.buf1._y'
>> cause: t.registers.read_write_demux._en (val: X)
>> time: 586920
WARNING: weak-interference `t.registers.read_write_demux.out1_en_buf_t.buf1._y'
>> cause: t.registers.read_write_demux._en (val: X)
>> time: 586920
WARNING: weak-interference `t.registers.read_write_demux.out2_en_buf_t.buf1._y'
>> cause: t.registers.read_write_demux._en (val: X)
>> time: 586920
WARNING: weak-interference `t.registers.read_write_demux.out1_en_buf_f.buf1._y'
>> cause: t.registers.read_write_demux._en (val: X)
>> time: 586920
WARNING: weak-interference `t.registers.read_write_demux._en1_X_t[0]'
>> cause: t.registers.read_write_demux.out1_en_buf_t.buf1._y (val: X)
>> time: 586937
WARNING: weak-interference `t.registers.read_write_demux._en2_X_t[0]'
>> cause: t.registers.read_write_demux.out2_en_buf_t.buf1._y (val: X)
>> time: 586937
WARNING: weak-interference `t.registers.read_write_demux._en2_X_f[0]'
>> cause: t.registers.read_write_demux.out2_en_buf_f.buf1._y (val: X)
>> time: 587058
WARNING: weak-interference `t.registers.read_write_demux._en1_X_f[0]'
>> cause: t.registers.read_write_demux.out1_en_buf_f.buf1._y (val: X)
>> time: 587346
WARNING: weak-interference `t.registers.clk_dly._a[1]'
>> cause: t.registers.clk_dly.mu2[0]._y (val: X)
>> time: 607612
WARNING: weak-interference `t.registers.clk_dly.and2[1]._y'
>> cause: t.registers.clk_dly._a[1] (val: X)
>> time: 607619
WARNING: weak-interference `t.registers.clk_dly.dly[1].a'
>> cause: t.registers.clk_dly.and2[1]._y (val: X)
>> time: 608033
WARNING: weak-interference `t.registers.clk_dly.dly[1]._y'
>> cause: t.registers.clk_dly.dly[1].a (val: X)
>> time: 608037
WARNING: weak-interference `t.registers.clk_dly.dly[1].__y'
>> cause: t.registers.clk_dly.dly[1]._y (val: X)
>> time: 609816
WARNING: weak-interference `t.registers.clk_dly.dly[1].___y'
>> cause: t.registers.clk_dly.dly[1].__y (val: X)
>> time: 632690
WARNING: weak-interference `t.registers.clk_dly.dly[1].y'
>> cause: t.registers.clk_dly.dly[1].___y (val: X)
>> time: 641335
WARNING: weak-interference `t.registers.clk_dly.dly[2]._y'
>> cause: t.registers.clk_dly.dly[1].y (val: X)
>> time: 642268
WARNING: weak-interference `t.registers.clk_dly.dly[2].__y'
>> cause: t.registers.clk_dly.dly[2]._y (val: X)
>> time: 643124
WARNING: weak-interference `t.registers.clk_dly.dly[2].___y'
>> cause: t.registers.clk_dly.dly[2].__y (val: X)
>> time: 643263
WARNING: weak-interference `t.registers.clk_dly.dly[2].y'
>> cause: t.registers.clk_dly.dly[2].___y (val: X)
>> time: 669472
WARNING: weak-interference `t.registers.clk_dly.mu2[1]._y'
>> cause: t.registers.clk_dly.dly[2].y (val: X)
>> time: 669474
WARNING: weak-interference `t.registers._clock_temp'
>> cause: t.registers.clk_dly.mu2[1]._y (val: X)
>> time: 722923
WARNING: weak-interference `t.registers._clock_temp_inv'
>> cause: t.registers._clock_temp (val: X)
>> time: 722929
WARNING: weak-interference `t.registers.clk_X.buf1._y'
>> cause: t.registers._clock_temp_inv (val: X)
>> time: 723183
WARNING: weak-interference `t.registers._clock'
>> cause: t.registers.clk_X.buf1._y (val: X)
>> time: 723191
WARNING: weak-interference `t.registers.and_encoder[0]._y'
>> cause: t.registers._clock (val: X)
>> time: 723192
WARNING: weak-interference `t.registers._clock_word_temp[0]'
>> cause: t.registers.and_encoder[0]._y (val: X)
>> time: 723198
WARNING: weak-interference `t.registers.clock_buffer[0].buf1._y'
>> cause: t.registers._clock_word_temp[0] (val: X)
>> time: 774234
WARNING: weak-interference `t.registers.ff_f[0].clk_B'
>> cause: t.registers.clock_buffer[0].buf1._y (val: X)
>> time: 777324
WARNING: weak-interference `t.registers.ff_f[0]._clk_B'
>> cause: t.registers.ff_f[0].clk_B (val: X)
>> time: 777550
WARNING: weak-interference `t.registers.ff_f[1]._clk_B'
>> cause: t.registers.ff_f[0].clk_B (val: X)
>> time: 777550
WARNING: weak-interference `t.registers.ff_t[0]._clk_B'
>> cause: t.registers.ff_f[0].clk_B (val: X)
>> time: 777550
WARNING: weak-interference `t.registers.ff_t[1]._clk_B'
>> cause: t.registers.ff_f[0].clk_B (val: X)
>> time: 777550
WARNING: weak-interference `t.registers.ff_f[1].__clk_B'
>> cause: t.registers.ff_f[1]._clk_B (val: X)
>> time: 777551
WARNING: weak-interference `t.registers.ff_t[1].__clk_B'
>> cause: t.registers.ff_t[1]._clk_B (val: X)
>> time: 777552
WARNING: weak-interference `t.registers.ff_t[1]._sqib'
>> cause: t.registers.ff_t[1]._clk_B (val: X)
>> time: 777552
WARNING: weak-interference `t.registers.ff_t[0].__clk_B'
>> cause: t.registers.ff_t[0]._clk_B (val: X)
>> time: 777556
WARNING: weak-interference `t.registers.ff_t[0]._sqib'
>> cause: t.registers.ff_t[0]._clk_B (val: X)
>> time: 777556
WARNING: weak-interference `t.registers.ff_t[0]._sqi'
>> cause: t.registers.ff_t[0]._sqib (val: X)
>> time: 777649
WARNING: weak-interference `t.data[0].d[0]'
>> cause: t.registers.ff_t[0]._sqib (val: X)
>> time: 777649
WARNING: weak-interference `t.registers.ff_f[0].__clk_B'
>> cause: t.registers.ff_f[0]._clk_B (val: X)
>> time: 778369
WARNING: weak-interference `t.registers.ff_t[1]._sqi'
>> cause: t.registers.ff_t[1]._sqib (val: X)
>> time: 798353
WARNING: weak-interference `t.data[0].d[1]'
>> cause: t.registers.ff_t[1]._sqib (val: X)
>> time: 798353
WRONG ASSERT: "t.registers._in_write.d.d[0].t" has value X and not 1.
WRONG ASSERT: "t.registers._in_write.d.d[1].t" has value X and not 1.
WRONG ASSERT: "t.registers._in_write.d.d[2].f" has value X and not 1.
WRONG ASSERT: "t.registers._in_write.d.d[3].f" has value X and not 1.
WRONG ASSERT: "t.registers._clock" has value X and not 0.
WARNING: weak-interference `t.registers.ff_t[0]._mqib'
>> cause: t.registers.ff_t[0].d (val: 0)
>> time: 800976
WARNING: weak-interference `t.registers.ff_t[1]._mqib'
>> cause: t.registers.ff_t[1].d (val: 0)
>> time: 800976
WARNING: weak-interference `t.registers.ff_t[0]._mqi'
>> cause: t.registers.ff_t[0]._mqib (val: X)
>> time: 800977
WARNING: weak-interference `t.registers.ff_t[1]._mqi'
>> cause: t.registers.ff_t[1]._mqib (val: X)
>> time: 800982
WRONG ASSERT: "t.registers._clock" has value X and not 1.
WRONG ASSERT: "t.registers.ff_t[0].q" has value X and not 1.
WRONG ASSERT: "t.registers.ff_t[1].q" has value X and not 1.
[3] first writing done
----------------------------------------------------------

2324
test/unit_tests/register_wrw/run/test.prs Normal file
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test/unit_tests/register_wrw/test.act Normal file
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/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/registers.act";
import globals;
open tmpl::dataflow_neuro;
// 2 bits encoder, 2 bits long words, 2 delays????
defproc register_test (avMx1of2<1+2+2> in; avMx1of2<2+2> out;d1of<2> data[1<<2]; bool? dly_cfg[2]){
register_rw<2,2,2> registers(.in=in,.data = data,.out = out);
//Low active Reset
bool _reset_B;
power _supply;
prs {
Reset => _reset_B-
}
registers.supply = _supply;
_supply.vss = GND;
_supply.vdd = Vdd;
registers.reset_B = _reset_B;
registers.reset_mem_B = _reset_B;
registers.dly_cfg = dly_cfg;
}
register_test t;

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#watchall
system "echo '[0] start test'"
system "echo '----------------------------------------------------------'"
set-qdi-channel-neutral "t.in" 5
set t.data[0].d[0] 0
set t.data[0].d[1] 0
set t.data[1].d[0] 0
set t.data[1].d[1] 0
set t.out.a 0
set Reset 0
cycle
status X
mode run
assert-qdi-channel-neutral "t.in" 5
assert t.data[0].d[0] 0
assert t.data[0].d[1] 0
assert t.data[1].d[0] 0
assert t.data[1].d[1] 0
cycle
system "echo '[1] reset completed'"
system "echo '----------------------------------------------------------'"
# Set delay config lines
set t.dly_cfg[0] 1
set t.dly_cfg[1] 1
cycle
system "echo '[2] delay line set'"
system "echo '----------------------------------------------------------'"
set-qdi-channel-valid "t.in" 5 3
cycle
assert-qdi-channel-valid "t.registers._in_write" 4 3
assert t.registers._clock 0
assert t.registers._out_encoder[0] 1
assert t.registers._out_encoder[1] 0
assert t.registers._out_encoder[2] 0
assert t.registers._out_encoder[3] 0
cycle
set-qdi-channel-neutral "t.in" 5
cycle
assert t.registers._clock 1
assert t.registers.ff_t[0].q 1
assert t.registers.ff_t[1].q 1
system "echo '[3] first writing done'"
system "echo '----------------------------------------------------------'"