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1 Commits
dev ... 115eede67d

Author SHA1 Message Date
Ole Richter
115eede67d added license, moved cell libs into repo 
added buffer (not tested),
 2022-02-21 00:21:22 +01:00
450 changed files with 453 additions and 579830 deletions
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2
.gitignore vendored
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@@ -6,5 +6,3 @@ arm64_*
*.arm64_*
*~
*.deps
test/unit_tests/**/run/

4
Makefile
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@@ -20,8 +20,8 @@
# -----------------------------------------------------------------------------
TARGETACT=LICENSE
# tmpl because its a template based appoach no syntesis so it would be wrong in syn
TARGETACTSUBDIR=tmpl/dataflow_neuro
# template because its a template based appoach no syntesis so it would be wrong in syn
TARGETACTSUBDIR=template/dataflow
SUBDIRS=dataflow_neuro

16
README.md
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@@ -1,18 +1,10 @@
# ARCHIVED REPOSITORY
# The classical dataflow template library for mixed signal neuromoric processors
further development and new versions => https://github.com/async-ic/actlib-neurosynaptic-perifery
# A dataflow template library for mixed signal neuromoric processors
the library will be installed in `$ACT_HOME/act/template/dataflow`. This path is part of the default search path for any ACT tool.
the library will be installed in `$ACT_HOME/act/tmpl/dataflow_neuro`.
This path is part of the default search path for any ACT tool.
this library depends on stdlib (https://github.com/asyncvlsi/stdlib)
this library depends on stdlib
## Installation
Set `$ACT_HOME` to the root of your ACT installation, and then run `make install`.
## Unit tests
After installation, you can run `make runtest` to execute the unit tests
Set `$ACT_HOME` to the root of your ACT installation, and then run `make install`

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dataflow_neuro/.DS_Store vendored
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4
dataflow_neuro/Makefile
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@@ -19,10 +19,10 @@
#
# -----------------------------------------------------------------------------
TARGETACT=__all__.act cell_lib_std.act cell_lib_async.act primitives.act
TARGETACT=__all__.act stdcells.act acells.act primitives.act
SUBDIRS=
# template because its a template based appoach no syntesis so it would be wrong in syn
TARGETACTSUBDIR=tmpl/dataflow_neuro
TARGETACTSUBDIR=template/dataflow_neuro
include $(ACT_HOME)/scripts/Makefile.std

6
dataflow_neuro/__all__.act
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@@ -22,6 +22,6 @@
**************************************************************************
*/
import tmpl::dataflow_neuro::cell_lib_std;
import tmpl::dataflow_neuro::cell_lib_async;
import tmpl::dataflow_neuro::primitives;
import template::dataflow_neuro::cell_lib_std;
import template::dataflow_neuro::cell_lib_async;
import template::dataflow_neuro::primitives;

357
dataflow_neuro/cell_lib_async.act
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@@ -24,33 +24,10 @@
**************************************************************************
*/
namespace tmpl {
namespace dataflow_neuro{
export defcell KEEP (bool y; bool vdd, vss) {
bool _y;
prs{
// y => _y-
// [weak=1] _y -> y-
// [weak=1] ~_y -> y+
namespace template {
namespace dataflow_neuro {
}
}
export defcell A_1C2N_RB_X1 (bool! y; bool? c1,n1,n2,pr_B, sr_B; bool vdd, vss) {
bool _y;
prs{
(~c1)|~pr_B -> _y+
c1 & n1 & n2 & sr_B -> _y-
_y => y-
}
sizing {
leak_adjust <- 1;
p_n_mode <- 1;
y {-1}; _y{-1}
}
}
export defcell A_1C1P2N_RB_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B; bool vdd, vss) {
export defcell A_1C1P2N_RB_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B, vdd, vss) {
bool _y;
prs{
(~p1 & ~c1)|~pr_B -> _y+
@@ -65,23 +42,7 @@ namespace tmpl {
}
}
export defcell A_2C1P1N_RB_X1 (bool! y; bool? c1,c2,p1,n1,pr_B,sr_B; bool vdd, vss) {
bool _y;
prs{
(~p1 & ~c1 & ~c2)|~pr_B -> _y+
c1 & c2 & n1 & sr_B -> _y-
_y => y-
}
sizing {
leak_adjust <- 1;
p_n_mode <- 1;
y {-1}; _y{-1}
}
}
export defcell A_1C1P2N_R_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B; bool vdd, vss) {
export defcell A_1C1P2N_R_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B, vdd, vss) {
prs{
(~p1 & ~c1)|~pr_B -> y-
c1 & n1 & n2 & sr_B -> y+
@@ -94,7 +55,7 @@ namespace tmpl {
}
export defcell A_1C1P_1N_X1 (bool! y; bool? c1, p1, n1; bool vdd, vss)
export defcell A_1C1P_1N_X1 (bool! y; bool? c1, p1, n1, vdd, vss)
{
prs{
~p1 & ~c1 -> y+
@@ -104,9 +65,8 @@ namespace tmpl {
p_n_mode <- 1;
y {-1}}
}
//Maybe deprecated?
//@TODO Check if it exist, otherwise delete
export defcell A_1C1P_B (bool! y; bool? c1, p1; bool vdd, vss)
export defcell A_1C1P_B (bool! y; bool? c1, p1, vdd, vss)
{
bool _y;
prs{
@@ -120,7 +80,7 @@ namespace tmpl {
}
export defcell A_1C1P_X1 (bool! y; bool? c1, p1; bool vdd, vss)
export defcell A_1C1P (bool! y; bool? c1, p1, vdd, vss)
{
prs{
~p1 & ~c1 -> y+
@@ -131,95 +91,7 @@ namespace tmpl {
y {-1}}
}
export defcell A_1C1N_X1 (bool! y; bool? c1, n1; bool vdd, vss)
{
prs{
~c1 -> y+
c1&n1-> y-
}
sizing {leak_adjust <- 1;
p_n_mode <- 1;
y {-1}}
}
// export defcell A_1C1N_RB_X4 (bool! y; bool? c1, n1, pr_B, sr_B; bool vdd, vss)
// {
// bool _y;
// prs{
// ~c1 | ~pr_B-> _y+
// c1&n1&sr_B -> _y-
// _y => y-
// }
// sizing {leak_adjust <- 1;
// p_n_mode <- 1;
// y {-4}; _y{-1}}
// }
// export defcell A_1C1N_SB_X4 (bool! y; bool? c1, n1, pr, sr; bool vdd, vss)
// {
// bool _y;
// prs{
// ~c1 & ~sr-> _y+
// c1&n1 | pr -> _y-
// _y => y-
// }
// sizing {leak_adjust <- 1;
// p_n_mode <- 1;
// y {-4}; _y{-1}}
// }
export defcell A_1C2N_R_X1 (bool! y; bool? c1, n1, n2, pr_B, sr_B; bool vdd, vss)
{
prs{
~c1 | ~pr_B-> y+
c1&n1&n2&sr_B -> y-
}
sizing {leak_adjust <- 1;
p_n_mode <- 1;
y {-4}}
}
export defcell A_1C2N_RB_X4 (bool! y; bool? c1, n1, n2, pr_B, sr_B; bool vdd, vss)
{
bool _y;
prs{
~c1 | ~pr_B-> _y+
c1&n1&n2&sr_B -> _y-
_y => y-
}
sizing {leak_adjust <- 1;
p_n_mode <- 1;
y {-4}; _y{-1}}
}
export defcell A_1C2N_SB_X4 (bool! y; bool? c1, n1, n2, pr, sr; bool vdd, vss)
{
bool _y;
prs{
~c1 & ~sr-> _y+
c1&n1&n2 | pr -> _y-
_y => y-
}
sizing {leak_adjust <- 1;
p_n_mode <- 1;
y {-4}; _y{-1}}
}
export defcell A_2C1N_SB_X4 (bool! y; bool? c1, c2, n1, pr, sr; bool vdd, vss)
{
bool _y;
prs{
~c1 & ~c2 & ~sr-> _y+
c1&c2&n1 | pr -> _y-
_y => y-
}
sizing {leak_adjust <- 1;
p_n_mode <- 1;
y {-4}; _y{-1}}
}
export defcell A_1C2P1N_X1 (bool! y; bool? c1, p1, p2, n1; bool vdd, vss)
export defcell A_1C2P1N_X1 (bool! y; bool? c1, p1, p2, n1, vdd, vss)
{
prs{
~p1 & ~p2 & ~c1 -> y+
@@ -230,7 +102,7 @@ namespace tmpl {
y {-1}}
}
export defcell A_1C2P_B_X1 (bool! y; bool? c1, p1, p2; bool vdd, vss)
export defcell A_1C2P_B_X1 (bool! y; bool? c1, p1, p2, vdd, vss)
{
bool _y;
prs{
@@ -242,9 +114,9 @@ namespace tmpl {
p_n_mode <- 1;
y {-1}; _y{-1} }
}
}
export defcell A_1C2P_X1 (bool! y; bool? c1, p1, p2; bool vdd, vss)
export defcell A_1C2P (bool! y; bool? c1, p1, p2, vdd, vss)
{
prs{
~p1 & ~p2 & ~c1 -> y+
@@ -255,7 +127,7 @@ namespace tmpl {
y {-1}}
}
export defcell A_1C3P2P2N_R_X1 (bool! y; bool? c1, p1, p2, p3, p4, p5, n1, n2, pr_B, sr_B; bool vdd, vss)
export defcell A_1C3P2P2N_R_X1 (bool! y; bool? c1, p1, p2, p3, p4, p5 n1, n2, pr_B, sr_B, vdd, vss)
{
prs{
(~p1 & ~p2 & ~p3 & ~c1)|(~p4&~p5&~c1)|~pr_B -> y+
@@ -266,12 +138,12 @@ namespace tmpl {
y {-1}}
}
export defcell A_2C2N2N_RB_X1 (bool ! y; bool? c1, c2, na1, na2, nb1, nb2, pr_B, sr_B; bool vdd, vss)
export defcell A_2C2N2N_RB_X1 (bool ! y; bool? c1, c2, n1, n2, n3, n4, pr_B, sr_B; bool? vdd, vss)
{
bool _y;
prs{
(~c1 & ~c2) | ~pr_B -> _y+
c1 & c2 & ((na1 & na2) | (nb1 & nb2)) & sr_B -> _y-
c1 & c2 & ((n1 & n2) | (n3 & n4)) & sr_B -> _y-
_y => y-
}
sizing {
@@ -280,7 +152,7 @@ namespace tmpl {
y {-1}; _y{-1}}
}
export defcell A_2C2N2N_RB_X2 (bool ! y; bool? c1, c2, n1, n2, n3, n4, pr_B, sr_B; bool vdd, vss)
export defcell A_2C2N2N_RB_X2 (bool ! y; bool? c1, c2, n1, n2, n3, n4, pr_B, sr_B; bool? vdd, vss)
{
bool _y;
prs{
@@ -322,12 +194,12 @@ namespace tmpl {
y {-1}}
}
export defcell A_2C2N_RB_X1 (bool ! y; bool? c1, c2, n1, n2, pr_B, sr_B; bool? vdd, vss)
export defcell A_2C2N_R_B_X1 (bool ! y; bool? c1, c2, n1, n2, rp_B, rs_B; bool? vdd, vss)
{
bool _y;
prs{
(~c1 & ~c2) | ~pr_B -> _y+
c1 & c2 & n1 & n2 & sr_B -> _y-
(~c1 & ~c2) | ~rp_B -> _y+
c1 & c2 & n1 & n2 & rs_B -> _y-
_y => y-
}
sizing {
@@ -336,12 +208,12 @@ namespace tmpl {
y {-1}; _y{-1}}
}
export defcell A_2C2N_RB_X2 (bool ! y; bool? c1, c2, n1, n2, pr_B, sr_B; bool? vdd, vss)
export defcell A_2C2N_R_B_X2 (bool ! y; bool? c1, c2, n1, n2, rp_B, rs_B; bool? vdd, vss)
{
bool _y;
prs{
(~c1 & ~c2) | ~pr_B -> _y+
c1 & c2 & n1 & n2 & sr_B -> _y-
(~c1 & ~c2) | ~rp_B -> _y+
c1 & c2 & n1 & n2 & rs_B -> _y-
_y => y-
}
sizing {
@@ -350,12 +222,12 @@ namespace tmpl {
y {-2}; _y{-1}}
}
export defcell A_2C2N_RB_X4 (bool ! y; bool? c1, c2, n1, n2, pr_B, sr_B; bool? vdd, vss)
export defcell A_2C2N_R_B_X4 (bool ! y; bool? c1, c2, n1, n2, rp_B, rs_B; bool? vdd, vss)
{
bool _y;
prs{
(~c1 & ~c2) | ~pr_B -> _y+
c1 & c2 & n1 & n2 & sr_B -> _y-
(~c1 & ~c2) | ~rp_B -> _y+
c1 & c2 & n1 & n2 & rs_B -> _y-
_y => y-
}
sizing {
@@ -365,11 +237,11 @@ namespace tmpl {
}
export defcell A_2C2N_R_X1 (bool ! y; bool? c1, c2, n1, n2, pr_B, sr_B; bool? vdd, vss)
export defcell A_2C2N_R_X1 (bool ! y; bool? c1, c2, n1, n2, rp_B, rs_B; bool? vdd, vss)
{
prs{
(~c1 & ~c2) | ~pr_B -> y+
c1 & c2 & n1 & n2 & sr_B -> y-
(~c1 & ~c2) | ~rp_B -> y+
c1 & c2 & n1 & n2 & rs_B -> y-
}
sizing {
leak_adjust <- 1;
@@ -405,20 +277,6 @@ namespace tmpl {
y {-1}; _y{-1}}
}
export defcell A_2C_RB_X4 (bool ! y; bool? c1, c2, pr_B, sr_B; bool? vdd, vss)
{
bool _y;
prs{
(~c1 & ~c2) | ~pr_B -> _y+
c1 & c2 & sr_B -> _y-
_y => y-
}
sizing {
leak_adjust <- 1;
p_n_mode <- 1;
y {-4}; _y{-1}}
}
export defcell A_2C_R_X1 (bool ! y; bool? c1, c2, pr_B, sr_B; bool? vdd, vss)
{
prs{
@@ -430,45 +288,7 @@ namespace tmpl {
p_n_mode <- 1;
y {-1}}
}
export defcell A_2C1N_RB_X1(bool ! y; bool? c1, c2, n1, pr_B, sr_B; bool? vdd, vss)
{
bool _y;
prs{
(~c1 & ~c2) | ~pr_B -> _y+
c1 & c2 & n1 & sr_B -> _y-
_y => y-
}
sizing {
leak_adjust <- 1;
p_n_mode <- 1;
y {-1}; _y{-1}}
}
export defcell A_2C1N_R_X1(bool ! y; bool? c1, c2, n1, pr_B, sr_B; bool? vdd, vss)
{
prs{
(~c1 & ~c2) | ~pr_B -> y+
c1 & c2 & n1 & sr_B -> y-
}
sizing {
leak_adjust <- 1;
p_n_mode <- 1;
y {-1}}
}
export defcell A_2C1N_RB_X4(bool ! y; bool? c1, c2, n1, pr_B, sr_B; bool? vdd, vss)
{
bool _y;
prs{
(~c1 & ~c2) | ~pr_B -> _y+
c1 & c2 & n1 & sr_B -> _y-
_y => y-
}
sizing {
leak_adjust <- 1;
p_n_mode <- 1;
y {-4}; _y{-1}}
}
export defcell A_2C_X1 (bool ! y; bool? c1, c2; bool? vdd, vss)
{
prs{
@@ -481,20 +301,6 @@ namespace tmpl {
y {-1}}
}
export defcell A_3C_B_X1 (bool ! y; bool? c1, c2, c3; bool? vdd, vss)
{
bool _y;
prs{
~c1 & ~c2 & ~c3 -> _y+
c1 & c2 & c3 -> _y-
_y => y-
}
sizing {
leak_adjust <- 1;
p_n_mode <- 1;
y {-1}; _y{-1}}
}
export defcell A_3C_RB_X1 (bool ! y; bool? c1, c2, c3, pr_B, sr_B; bool? vdd, vss)
{
bool _y;
@@ -561,7 +367,7 @@ namespace tmpl {
y {-1}}
}
export defcell A_4C_RB_X1 (bool! y; bool? c1, c2, c3, c4, pr_B, sr_B; bool? vdd, vss)
export deffcell A_4C_RB_X1 (bool! y; bool? c1, c2, c3, c4, pr_B, sr_B; bool? vdd, vss)
{
bool _y;
prs{
@@ -574,7 +380,7 @@ namespace tmpl {
y {-1}; _y{-1}}
}
export defcell A_4C_RB_X2 (bool! y; bool? c1, c2, c3, c4, pr_B, sr_B; bool? vdd, vss)
export deffcell A_4C_RB_X2 (bool! y; bool? c1, c2, c3, c4, pr_B, sr_B; bool? vdd, vss)
{
bool _y;
prs{
@@ -587,7 +393,7 @@ namespace tmpl {
y {-2}; _y{-1}}
}
export defcell A_4C_RB_X4 (bool! y; bool? c1, c2, c3, c4, pr_B, sr_B; bool? vdd, vss)
export deffcell A_4C_RB_X4 (bool! y; bool? c1, c2, c3, c4, pr_B, sr_B; bool? vdd, vss)
{
bool _y;
prs{
@@ -600,7 +406,7 @@ namespace tmpl {
y {-4}; _y{-1}}
}
export defcell A_4C_R_X1 (bool! y; bool? c1, c2, c3, c4, pr_B, sr_B; bool? vdd, vss)
export deffcell A_4C_R_X1 (bool! y; bool? c1, c2, c3, c4, pr_B, sr_B; bool? vdd, vss)
{
prs{
(~c1 & ~c2 & ~c3 & ~c4) | ~pr_B -> y+
@@ -624,110 +430,17 @@ namespace tmpl {
y {-1}; _y{-1} }
}
export defcell A_4P1N1N_X1 (bool! y; bool? na1, nb1, p1, p2, p3, p4; bool? vdd, vss)
export defcell A_4P1N1N_X1 (bool! y; bool? n1, n2, p1, p2, p3, p4; bool? vdd, vss)
{
prs{
~p1 & ~p2 & ~p3 & ~p4 -> y+
na1 | nb1 -> y-
n1 | n2 -> y-
}
sizing {leak_adjust <- 1;
p_n_mode <- 1;
y {-1}}
}
//Rajit example
defproc arbiter_Rajit (bool a, b, u, v)
{
bool _u, _v;
prs {
[keeper=0] a & _v -> _u-
[keeper=0] ~a | ~_v -> _u+
[keeper=0] b & _u -> _v-
[keeper=0] ~b | ~_u -> _v+
[keeper=0] _u => u-
[keeper=0] _v => v-
}
spec {
mk_excllo(_u, _v)
}
}
defproc ARBITER (bool? a, b, c, d; bool! y1,y2; bool? vdd, vss)
{
bool _y1, _y2;
prs {
[keeper=0] a & _y2 -> _y1-
[keeper=0] ~a | ~_y2 -> _y1+
[keeper=0] b & _y1 -> _y2-
[keeper=0] ~b | ~_y1 -> _y2+
[keeper=0] _y1 | c => y1-
[keeper=0] _y2 | d => y2-
}
spec {
mk_excllo(_y1, _y2)
}
}
export
defproc A_1N_U_X4(bool? n1; bool! y; bool? vdd, vss)
{
prs{
[keeper=0] n1 -> y-
}
}
export
defproc A_2N_U_X4(bool? n1, n2; bool! y; bool? vdd, vss)
{
prs{
[keeper=0] n1 & n2 -> y-
}
}
export
defproc A_1P_U_X4(bool? p1; bool! y; bool? vdd, vss)
{
prs{
[keeper=0] ~p1 -> y+
}
}
export
defproc A_2P_U_X4(bool? p1, p2; bool! y; bool? vdd, vss)
{
prs{
[keeper=0] ~p1 & ~p2 -> y+
}
}
export
defproc A_3P_U_X4(bool? p1, p2, p3; bool! y; bool? vdd, vss)
{
prs{
[keeper=0] ~p1 & ~p2 & ~p3-> y+
}
}
export
defproc PULLDOWN_X4(bool? a; bool! y; bool? vdd, vss) {
A_1N_U_X4 cell(.n1 = a, .y = y, .vdd = vdd, .vss = vss);
}
export
defproc PULLUP_X4(bool? a; bool! y; bool? vdd, vss) {
A_1P_U_X4 cell(.p1 = a, .y = y, .vdd = vdd, .vss = vss);
}
defproc A_2C2P_RB_X1(bool! y;bool? c1,c2,p1,p2,reset_B,vdd,vss){
bool _y;
prs{
(~p1 & ~p2 & ~c1 & ~c2)|~reset_B -> _y+
(c1 & c2 & reset_B) -> _y-
_y => y-
}
sizing {leak_adjust <- 1;
p_n_mode <- 1;
y {-1}; _y{-1} }
}
}}
xp018_cell_lib_async::A_1C1P_B_X1 cell1;

665
dataflow_neuro/cell_lib_std.act
View File

@@ -24,431 +24,256 @@
**************************************************************************
*/
namespace tmpl {
namespace dataflow_neuro {
namespace dataflow {
export defproc TIELO_X1(bool! y; bool? vdd, vss)
{
y = vss;
}
// We have to add a pretend buffer in here
// to ensure that act2v doesn't simplify things
// and just connect y to vss/vdd lol
export defproc TIELO_X1(bool! y; bool vdd, vss)
{
bool _y, a;
a = vss;
prs {
a => _y-
_y => y-
}
export defproc TIEHI_X1(bool! y; bool? vdd, vss)
{
y = vdd;
}
}
/*-- inverters --*/
export defproc TIEHI_X1(bool! y; bool vdd, vss)
{
bool _y, a;
a = vdd;
prs {
a => _y-
_y => y-
}
}
/*-- inverters --*/
defproc inv (bool! y; bool? a, vdd, vss)
{
prs {
a => y-
}
}
template<pint nf>
defproc szinv <: inv()
{
[nf = 0 -> sizing { y {-1} }
[] else -> sizing { y {-2*nf,svt,nf} }
]
}
export defcell INV_X1<: szinv<0>() { }
export defcell INV_X2<: szinv<1>() { }
export defcell INV_X4<: szinv<2>() { }
export defcell INV_X8<: szinv<4>() { }
/*-- signal buffers --*/
defproc buf (bool! y; bool? a, vdd, vss)
{
bool _y;
prs {
a => _y-
_y => y-
}
}
export defcell BUF_X1<: buf()
{
sizing { _y {-1}; y {-1} }
}
export defcell BUF_X2<: buf()
{
sizing { _y {-1}; y {-2} }
}
export defcell BUF_X3<: buf()
{
sizing { _y {-1.5}; y {-3} }
}
export defcell BUF_X4<: buf()
{
sizing { _y {-1.5}; y {-4,2} }
}
export defcell BUF_X6<: buf()
{
sizing { _y {-3}; y {-6,2} }
}
export defcell BUF_X8<: buf()
{
sizing { _y {-4,2}; y {-8,4} }
}
export defcell BUF_X12<: buf()
{
sizing { _y {-6,2}; y {-12,4} }
}
export defcell BUF_X16<: buf()
{
sizing { _y {-6,2}; y {-12,4} }
}
export defcell BUF_X24<: buf()
{
sizing { _y {-6,2}; y {-12,4} }
}
export defcell BUF_X32<: buf()
{
sizing { _y {-6,2}; y {-12,4} }
}
/*-- delay cells --*/
// TODO properly
// export defcell DLY4_X1(bool! y; bool? a, vdd, vss)
// {
// bool _y, __y, ___y;
// prs {
// a => _y-
// _y => __y-
// __y => ___y-
// ___y => y-
// }
// }
export defcell DLY4_X1(bool! y; bool? a, vdd, vss)
{
BUF_X1 bufchain[16];
(i:0..14: bufchain[i].y = bufchain[i+1].a;)
bufchain[0].a = a;
bufchain[15].y = y;
}
/*-- simple gates --*/
export defcell NOR2_X1(bool! y; bool? a, b, vdd, vss)
{
prs {
a | b => y-
}
sizing { y {-1} }
}
export defcell NOR3_X1(bool! y; bool? a, b, c, vdd, vss)
{
prs {
a | b | c => y-
}
sizing { y {-1} }
}
export defcell NOR4_X1(bool! y; bool? a, b, c, d, vdd, vss)
{
prs {
a | b | c | d => y-
}
sizing { y {-1} }
}
export defcell OR2_X1(bool! y; bool? a, b, vdd, vss)
{
bool _y;
prs {
a | b => _y-
_y => y-
}
sizing { _y{-1}; y{-1} }
}
export defcell OR2_X2(bool! y; bool? a, b, vdd, vss)
{
bool _y;
prs {
a | b => _y-
_y => y-
}
sizing { _y{-1}; y{-2} }
}
export defcell OR3_X1(bool! y; bool? a, b, c, vdd, vss)
{
bool _y;
prs {
a | b | c => _y-
_y => y-
}
sizing { _y{-1}; y{-1} }
}
export defcell OR4_X1(bool! y; bool? a, b, c, d, vdd, vss)
{
bool _y;
prs {
a | b | c | d => _y-
_y => y-
}
sizing { _y{-1}; y{-1} }
}
export defcell NAND2_X1(bool! y; bool? a, b, vdd, vss)
{
prs {
a & b => y-
}
sizing { y{-1} }
}
export defcell NAND3_X1(bool! y; bool? a, b, c, vdd, vss)
{
prs {
a & b & c => y-
}
sizing { y{-1} }
}
export defcell NAND4_X1(bool! y; bool? a, b, c, d, vdd, vss)
{
prs {
a & b & c & d => y-
}
sizing { y{-1} }
}
export defcell AND2_X1(bool! y; bool? a, b, vdd, vss)
{
bool _y;
prs {
a & b => _y-
_y => y-
}
sizing { _y{-1}; y{-1} }
}
export defcell AND2_X2(bool! y; bool? a, b, vdd, vss)
{
bool _y;
prs {
a & b => _y-
_y => y-
}
sizing { _y{-1}; y{-2} }
}
export defcell AND3_X1(bool! y; bool? a, b, c, vdd, vss)
{
bool _y;
prs {
a & b & c => _y-
_y => y-
}
sizing { _y{-1}; y{-1} }
}
export defcell AND4_X1(bool! y; bool? a, b, c, d, vdd, vss)
{
bool _y;
prs {
a & b & c & d => _y-
_y => y-
}
sizing { _y{-1}; y{-1} }
}
export defcell XOR2_X1(bool! y; bool? a, b, vdd, vss)
{
bool _a, _b;
prs {
a => _a-
b => _b-
[keeper=0] ~b & ~_a | ~_b & ~a -> y+
_b & _a | b & a -> y-
}
sizing { _a{-1}; _b{-1}; y{-1} }
}
export defcell XNOR2_X1(bool! y; bool? a, b, vdd, vss)
{
bool _a, _b;
prs {
a => _a-
b => _b-
[keeper=0] ~b & ~a | ~_b & ~_a -> y+
b & _a | _b & a -> y-
}
sizing { _a{-1}; _b{-1}; y{-1} }
}
export defcell MUX2_X1(bool! y; bool? a, b, s, vdd, vss)
{
// y = !( S ? b : a )
// Actually looks more like
// if s = 0 -> use A
// Adjusted to fit the XFAB Muxes
bool _s;
bool _y;
prs {
s => _s-
[keeper=0] ~a & ~s | ~b & ~_s -> _y+
a & _s | b & s -> _y-
_y => y-
}
sizing { _s{-1}; y{-1}; _y{-1}}
}
export defcell MUX4_X1(bool! y; bool? a, b, c, d, s0, s1, vdd, vss)
{
// y = !( S ? a : b )
bool _s0;
bool _s1;
bool _yab;
bool _ycd;
prs {
s0 => _s0-
s1 => _s1-
[keeper=0] a & _s0 | b & s0 -> _yab-
~a & ~s0 | ~b & ~_s0 -> _yab+
[keeper=0] c & _s0 | d & s0 -> _ycd-
~c & ~s0 | ~d & ~_s0 -> _ycd+
[keeper=0]_yab & _s1 | _ycd & s1 -> y-
~_yab & ~s1 | ~_ycd & ~_s1 -> y+
}
sizing {_s0{-1}; _s1{-1}; y{-1}; _yab{-1}; _ycd{-1}}
}
export defcell OAI21_X1(bool! y; bool? a, b, c, vdd, vss)
{
prs {
(a | b) & c => y-
}
sizing { y{-1} }
}
export defcell AOI21_X1(bool! y; bool? a, b, c, vdd, vss)
{
prs {
a & b | c => y-
}
sizing { y{-1} }
}
export defcell OAI22_X1(bool! y; bool? a, b, c, d, vdd, vss)
{
// y = !((a|b) & (c|d))
prs {
(a | b) & (c | d) => y-
}
sizing { y{-1} }
}
export defcell AOI22_X1(bool! y; bool? a, b, c, d, vdd, vss)
{
prs {
a & b | c & d => y-
}
sizing { y{-1} }
}
/*--- buffered transmission gates ---*/
export defcell TBUF1_X1 (bool! y; bool? a, en, vdd, vss)
{
bool _en;
prs {
en => _en-
~a & ~_en -> y-
a & en -> y+
}
sizing { _en{-1}; y{-1} }
}
export defcell TBUF_X2 (bool! y; bool? a, en, vdd, vss)
{
bool _en;
prs {
en => _en-
~a & ~_en -> y-
a & en -> y+
}
sizing { _en{-2}; y{-2,2} }
}
export defcell TBUF_X4 (bool! y; bool? a, en, vdd, vss)
{
bool _en;
prs {
en => _en-
~a & ~_en -> y-
a & en -> y+
}
sizing { _en{-4}; y{-4,4} }
}
export defproc DFFQ_R_X1 (bool? clk_B, reset_B, d; bool! q,q_B; bool? vdd,vss)
{
bool _clk_B, __clk_B, _mqi,_mqib,_sqi,_sqib;
prs {
// Creating delayed versions of the clock
clk_B => _clk_B-
_clk_B => __clk_B-
(~d & ~_clk_B)|(~reset_B)|(~__clk_B&~_mqi) -> _mqib+
((d & __clk_B)|(_mqi & _clk_B))&reset_B -> _mqib-
_mqib => _mqi-
(~_mqi &~__clk_B)|(~reset_B)|(~_sqi&~_clk_B) -> _sqib+
((_mqi &_clk_B)|(_sqi&__clk_B))&reset_B -> _sqib-
_sqib => _sqi-
_sqib => q-
q => q_B-
}
}
defproc inv (bool! y; bool? a, vdd, vss)
{
prs {
a => y-
}
}
template<pint nf>
defproc szinv <: inv()
{
[nf = 0 -> sizing { y {-1} }
[] else -> sizing { y {-2*nf,svt,nf} }
]
}
export defcell INV_X1<: szinv<0>() { }
export defcell INV_X2<: szinv<1>() { }
export defcell INV_X4<: szinv<2>() { }
export defcell INV_X8<: szinv<4>() { }
/*-- clock delay buffers --*/
template<pint N>
defproc dbuf (bool! y; bool? a, vdd, vss)
{
{N > 0 : "Delay buffer needs at least one stage!"};
bool sig[2*N+1];
sig[0] = a;
sig[2*N] = y;
prs {
(i:2*N: ~sig[i] <80;2> -> sig[i+1]+
sig[i] <40;2> -> sig[i+1]-
)
}
}
export defproc CLKBUF1 <: dbuf<2>() { }
export defproc CLKBUF2 <: dbuf<3>() { }
export defproc CLKBUF3 <: dbuf<4>() { }
/*-- signal buffers --*/
defproc buf (bool! y; bool? a, vdd, vss)
{
bool _y;
prs {
a => _y-
_y => y-
}
}
export defcell BUF_X2<: buf()
{
sizing { _y {-1}; y {-2} }
}
export defcell BUF_X4<: buf()
{
sizing { _y {-1.5}; y {-4,2} }
}
/*-- simple gates --*/
export defcell NOR2_X1(bool! y; bool? a, b, vdd, vss)
{
prs {
a | b => y-
}
sizing { y {-1} }
}
export defcell NOR3_X1(bool! y; bool? a, b, c, vdd, vss)
{
prs {
a | b | c => y-
}
sizing { y {-1} }
}
export defcell OR2_X1(bool! y; bool? a, b, vdd, vss)
{
bool _y;
prs {
a | b => _y-
_y => y-
}
sizing { _y{-1}; y{-1} }
}
export defcell OR2_X2(bool! y; bool? a, b, vdd, vss)
{
bool _y;
prs {
a | b => _y-
_y => y-
}
sizing { _y{-1}; y{-2} }
}
export defcell NAND2_X1(bool! y; bool? a, b, vdd, vss)
{
prs {
a & b => y-
}
sizing { y{-1} }
}
export defcell NAND3_X1(bool! y; bool? a, b, c, vdd, vss)
{
prs {
a & b & c => y-
}
sizing { y{-1} }
}
export defcell AND2_X1(bool! y; bool? a, b, vdd, vss)
{
bool _y;
prs {
a & b => _y-
_y => y-
}
sizing { _y{-1}; y{-1} }
}
export defcell AND2_X2(bool! y; bool? a, b, vdd, vss)
{
bool _y;
prs {
a & b => _y-
_y => y-
}
sizing { _y{-1}; y{-2} }
}
export defcell XOR2_X1(bool! y; bool? a, b, vdd, vss)
{
bool _a, _b;
prs {
a => _a-
b => _b-
[keeper=0] ~b & ~_a | ~_b & ~a -> y+
_b & _a | b & a -> y-
}
sizing { _a{-1}; _b{-1}; y{-1} }
}
export defcell XNOR2_X1(bool! y; bool? a, b, vdd, vss)
{
bool _a, _b;
prs {
a => _a-
b => _b-
[keeper=0] ~b & ~a | ~_b & ~_a -> y+
b & _a | _b & a -> y-
}
sizing { _a{-1}; _b{-1}; y{-1} }
}
export defcell MUX2_X1(bool! y; bool? a, b, S, vdd, vss)
{
// y = !( S ? a : b )
bool _S;
prs {
S => _S-
[keeper=0] ~a & ~_S | ~b & ~S -> y+
a & S | b & _S -> y-
}
sizing { _S{-1}; y{-1} }
}
export defcell OAI21_X1(bool! y; bool? a, b, c, vdd, vss)
{
prs {
(a | b) & c => y-
}
sizing { y{-1} }
}
export defcell AOI21_X1(bool! y; bool? a, b, c, vdd, vss)
{
prs {
a & b | c => y-
}
sizing { y{-1} }
}
export defcell OAI22_X1(bool! y; bool? a, b, c, d, vdd, vss)
{
// y = !((a|b) & (c|d))
prs {
(a | b) & (c | d) => y-
}
sizing { y{-1} }
}
export defcell AOI22_X1(bool! y; bool? a, b, c, d, vdd, vss)
{
prs {
a & b | c & d => y-
}
sizing { y{-1} }
}
/*--- buffered transmission gates ---*/
export defcell TBUF1_X1 (bool! y; bool? a, en, vdd, vss)
{
bool _en;
prs {
en => _en-
~a & ~_en -> y+
a & en -> y-
}
sizing { _en{-1}; y{-1} }
}
export defcell TBUF_X2 (bool! y; bool? a, en, vdd, vss)
{
bool _en;
prs {
en => _en-
~a & ~_en -> y+
a & en -> y-
}
sizing { _en{-2}; y{-2,2} }
}

479
dataflow_neuro/chips.act
View File

@@ -1,479 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import "../../dataflow_neuro/treegates.act";
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/registers.act";
import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/interfaces.act";
// import tmpl::dataflow_neuro;
// import tmpl::dataflow_neuro;
import std::channel;
open std::channel;
namespace tmpl {
namespace dataflow_neuro {
export template<pint N_IN, // Size of input data from outside world
N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
N_SYN_DLY_CFG,
N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
N_BUFFERS,
N_LINE_PD_DLY, // Number of dummy delays to add line pull down
REG_NCA, REG_NCW, REG_M>
defproc texel_core (avMx1of2<N_IN> in, out;
Mx1of2<REG_NCW> reg_data[REG_M];
// Dummy synapses and neurons in the handshake blocks
// should be removed pre-innovus, else they are floating.
// a1of1 synapses[N_SYN_X * N_SYN_Y];
// a1of1 neurons[N_NRN_X * N_NRN_Y];
// Synapse decoder stuff
// The analogue core and connects to these to replace the above synapses.
bool! dec_req_x[N_SYN_X], dec_req_y[N_SYN_Y];
bool? dec_ackB[N_SYN_X];
a1of1 syn_pu[N_SYN_X];
// Neuron encoder stuff
a1of1 enc_inx[N_NRN_X], enc_iny[N_NRN_Y];
a1of1 nrn_pd_x[N_NRN_X], nrn_pd_y[N_NRN_Y];
// Monitors and flags to/from core, and selected mon out.
bool! nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y];
bool! syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y];
bool? syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
bool! syn_mon_AMZO[N_MON_AMZO_PER_SYN], nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
bool! syn_flags_EFO[N_FLAGS_PER_SYN], nrn_flags_EFO[N_FLAGS_PER_NRN];
power supply;
bool? reset_B, reset_reg_B, reset_syn_stge_BI;
bool! reset_nrn_hs_BO[N_NRN_X], reset_syn_hs_BO[N_SYN_X],
reset_nrn_stge_BO[N_NRN_X], reset_syn_stge_BO[N_SYN_X]){
bool _reset_BX;
BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
pint index = 0; // Just useful
// Onwards
fifo<N_IN,N_BUFFERS> fifo_in(.in = in, .reset_B = _reset_BX, .supply = supply);
demux_bit_msb<N_IN-1> _demux(.in = fifo_in.out, .reset_B = _reset_BX, .supply = supply);
// Register
fifo<N_IN-1,N_BUFFERS> fifo_dmx2reg(.in = _demux.out2, .reset_B = _reset_BX, .supply = supply);
register_wr_array<REG_NCA, REG_NCW, REG_M> register(.in = fifo_dmx2reg.out, .data = reg_data,
.supply = supply, .reset_B = reset_reg_B);
fifo<N_IN-2,N_BUFFERS> fifo_reg2mrg(.in = register.out, .reset_B = _reset_BX, .supply = supply);
// Spike Decoder
pint NC_SYN;
NC_SYN = NC_SYN_X + NC_SYN_Y;
slice_data<N_IN-1, 0, NC_SYN> slice_pre_dec(.in = _demux.out1, .supply = supply);
fifo<NC_SYN,N_BUFFERS> fifo_dmx2dec(.in = slice_pre_dec.out, .reset_B = _reset_BX, .supply = supply);
decoder_2d_hybrid<NC_SYN_X, NC_SYN_Y, N_SYN_X, N_SYN_Y, N_SYN_DLY_CFG> decoder(.in = fifo_dmx2dec.out,
.hs_en = register.data[0].d[0].t, // Defaults to handshake disable
.ack_disable = register.data[1].d[2].t, // Defaults to ack enabled
.out_req_x = dec_req_x, .out_req_y = dec_req_y,
.to_pu = syn_pu,
.in_ackB_decoder = dec_ackB,
.supply = supply, .reset_B = _reset_BX);
INV_X1 dly_cfg_inverters[N_SYN_DLY_CFG];
(i:N_SYN_DLY_CFG:
dly_cfg_inverters[i].a = register.data[0].d[1+i].t; // iff t is high, is the delay disabled.
dly_cfg_inverters[i].vdd = supply.vdd;
dly_cfg_inverters[i].vss = supply.vss;
decoder.dly_cfg[i] = dly_cfg_inverters[i].y;
)
// Synapse handshake circuits, to be removed for innovus
// decoder_2d_synapse_hs<N_SYN_X, N_SYN_Y> _synapses(
// .synapses = synapses,
// .in_req_x = dec_req_x, .in_req_y = dec_req_y,
// .to_pu = syn_pu,
// .out_ackB_decoder = dec_ackB,
// .supply = supply);
// Neurons + encoder
pint NC_NRN;
NC_NRN = NC_NRN_X + NC_NRN_Y;
encoder2d_simple<NC_NRN_X, NC_NRN_Y, N_NRN_X, N_NRN_Y, N_LINE_PD_DLY> encoder(
.inx = enc_inx, .iny = enc_iny,
.reset_B = _reset_BX, .supply = supply,
.to_pd_x = nrn_pd_x, .to_pd_y = nrn_pd_y);
fifo<NC_NRN, N_BUFFERS> fifo_enc2mrg(.in = encoder.out,
.reset_B = _reset_BX, .supply = supply);
// Neuron handshake circuits, to be removed for innovus
// nrn_hs_2d_array<N_NRN_X,N_NRN_Y> nrn_grid(.in = neurons,
// .outx = enc_inx, .outy = enc_iny,
// .to_pd_x = nrn_pd_x, .to_pd_y = nrn_pd_y,
// .supply = supply, .reset_B = _reset_BX);
// Merge
append<NC_NRN, N_IN-NC_NRN, 0> append_enc(.in = fifo_enc2mrg.out, .supply = supply);
append<N_IN-2, 2, 2> append_reg(.in = fifo_reg2mrg.out, .supply = supply);
merge<N_IN> merge_enc8reg(.in1 = append_enc.out, .in2 = append_reg.out,
.supply = supply, .reset_B = _reset_BX);
// Output
fifo<N_IN, N_BUFFERS> fifo_out(.in = merge_enc8reg.out, .out = out,
.reset_B = _reset_BX, .supply = supply);
// Neuron/synapse monitor targeters
pint NC_NRN_MON_X = std::ceil_log2(N_NRN_MON_X);
pint NC_NRN_MON_Y = std::ceil_log2(N_NRN_MON_Y);
pint NC_SYN_MON_X = std::ceil_log2(N_SYN_MON_X);
pint NC_SYN_MON_Y = std::ceil_log2(N_SYN_MON_Y);
decoder_dualrail_en<NC_NRN_MON_X, N_NRN_MON_X> nrn_mon_dec_x(.supply = supply);
nrn_mon_dec_x.en = register.data[1].d[0].t;
(i:NC_NRN_MON_X:
nrn_mon_dec_x.in.d[i] = register.data[2].d[i];
)
sigbuf_boolarray<N_NRN_MON_X, 13> nrn_mon_x_buf(.in = nrn_mon_dec_x.out, .out = nrn_mon_x, .supply = supply);
decoder_dualrail_en<NC_NRN_MON_Y, N_NRN_MON_Y> nrn_mon_dec_y(.supply = supply);
nrn_mon_dec_y.en = register.data[1].d[0].t;
(i:NC_NRN_MON_Y:
nrn_mon_dec_y.in.d[i] = register.data[2].d[i+NC_NRN_MON_X];
)
sigbuf_boolarray<N_NRN_MON_Y, 48> nrn_mon_y_buf(.in = nrn_mon_dec_y.out, .out = nrn_mon_y, .supply = supply);
decoder_dualrail_en<NC_SYN_MON_X, N_SYN_MON_X> syn_mon_dec_x(
.supply = supply);
syn_mon_dec_x.en = register.data[1].d[1].t;
(i:NC_SYN_MON_X:
syn_mon_dec_x.in.d[i] = register.data[3].d[i];
)
sigbuf_boolarray<N_SYN_MON_X, 13> syn_mon_x_buf(.out = syn_mon_x, .supply = supply);
decoder_dualrail_en<NC_SYN_MON_Y, N_SYN_MON_Y> syn_mon_dec_y(.supply = supply);
syn_mon_dec_y.en = register.data[1].d[1].t;
(i:NC_SYN_MON_Y:
syn_mon_dec_y.in.d[i] = register.data[3].d[i+NC_SYN_MON_X];
)
sigbuf_boolarray<N_SYN_MON_Y, 48> syn_mon_y_buf(.out = syn_mon_y, .in = syn_mon_dec_y.out, .supply = supply);
// Device debug hard-wired safety (reg0, b05 = DEV_DEBUG)
// Stops the possibility of dev_mon being high while some other sig is high.
// Otherwise boom.
// Also the 4th monitor line to each synapse is active LOW, needs inverter.
bool DEV_DEBUG;
pint NSMX4 = N_SYN_MON_X/4; // Self explanatory
sigbuf<std::max(NSMX4,4)> sb_DEV_DEBUG(.in = register.data[0].d[5].t,
.supply = supply);
DEV_DEBUG = sb_DEV_DEBUG.out[0];
INV_X1 syn_targ_set_high_inv[NSMX4];
[NSMX4 >= 1 ->
AND2_X1 ands_devmon[NSMX4];
(i:NSMX4:
ands_devmon[i].a = syn_mon_dec_x.out[1+i*4];
ands_devmon[i].b = DEV_DEBUG;
ands_devmon[i].y = syn_mon_x_buf.in[1+i*4];
ands_devmon[i].vdd = supply.vdd;
ands_devmon[i].vss = supply.vss;
syn_targ_set_high_inv[i].a = syn_mon_dec_x.out[3+i*4];
syn_targ_set_high_inv[i].y = syn_mon_x_buf.in[3+i*4];
syn_targ_set_high_inv[i].vdd = supply.vdd;
syn_targ_set_high_inv[i].vss = supply.vss;
)
// Wire up the remaining lines.
(i:N_SYN_MON_X:
[(~(i%4 = 1)) & (~(i%4=3))->
syn_mon_x_buf.in[i] = syn_mon_dec_x.out[i];
]
)
]
// Create TBUFs for each synapse column,
// ctrl wired to mon line (first in each 4).
TBUF_X4 syn_x_AMZI_tbuf[N_SYN_X * N_MON_AMZO_PER_SYN];
KEEP syn_AMZO_keeps[N_MON_AMZO_PER_SYN];
sigbuf_boolarray<N_MON_AMZO_PER_SYN, 40> syn_mon_AMZO_sb(.out = syn_mon_AMZO, .supply = supply);
(j:N_MON_AMZO_PER_SYN:
(i:N_SYN_X:
index = i*N_MON_AMZO_PER_SYN + j;
syn_x_AMZI_tbuf[index].a = syn_mon_AMZI[index];
syn_x_AMZI_tbuf[index].en = syn_mon_x[i*4];
syn_x_AMZI_tbuf[index].y = syn_mon_AMZO_sb.in[j];
)
syn_AMZO_keeps[j].y = syn_mon_AMZO_sb.in[j];
syn_AMZO_keeps[j].vdd = supply.vdd;
syn_AMZO_keeps[j].vss = supply.vss;
)
// Create TBUFs for each neuron column, and add keeps.
// ctrl wired to mon line (first in each 4).
TBUF_X4 nrn_x_AMZI_tbuf[N_NRN_X * N_MON_AMZO_PER_NRN];
KEEP nrn_AMZO_keeps[N_MON_AMZO_PER_NRN];
sigbuf_boolarray<N_MON_AMZO_PER_NRN, 40> nrn_mon_AMZO_sb(.out = nrn_mon_AMZO, .supply = supply);
(j:N_MON_AMZO_PER_NRN:
(i:N_NRN_X:
index = i*N_MON_AMZO_PER_NRN + j;
nrn_x_AMZI_tbuf[index].a = nrn_mon_AMZI[index];
nrn_x_AMZI_tbuf[index].en = nrn_mon_x[i*2];
nrn_x_AMZI_tbuf[index].y = nrn_mon_AMZO_sb.in[j];
)
nrn_AMZO_keeps[j].y = nrn_mon_AMZO_sb.in[j];
nrn_AMZO_keeps[j].vdd = supply.vdd;
nrn_AMZO_keeps[j].vss = supply.vss;
)
// Create buffered signals from register to nrns.
sigbuf_boolarray<N_FLAGS_PER_NRN, 31> sb_nrn_EFO(.out = nrn_flags_EFO, .supply = supply);
(i:N_FLAGS_PER_NRN:
sb_nrn_EFO.in[i] = register.data[5].d[i].t;
)
// Create buffered signals from register to synapses.
// Includes safety on the first 3 flags with dev mon.
sigbuf_boolarray<N_FLAGS_PER_SYN, 31> sb_syn_EFO(.out = syn_flags_EFO, .supply = supply);
(i:3..N_FLAGS_PER_SYN-1:
sb_syn_EFO.in[i] = register.data[4].d[i].t;
)
AND2_X1 syn_flags_dev_safety[3];
(i:0..2:
syn_flags_dev_safety[i].a = register.data[4].d[i].t; // syn flag bit
syn_flags_dev_safety[i].b = register.data[0].d[5].f; // no device is being monitored.
sb_syn_EFO.in[i] = syn_flags_dev_safety[i].y;
syn_flags_dev_safety[i].vdd = supply.vdd;
syn_flags_dev_safety[i].vss = supply.vss;
)
// Create non-buffered reset signals for the neuron/syn handshakes
// Since sigs are buffered before each neuron.
sigbuf<N_SYN_X> rsb_syn_hs(.in = _reset_BX, .out = reset_syn_hs_BO, .supply = supply);
sigbuf<N_NRN_X> rsb_nrn_hs(.in = _reset_BX, .out = reset_nrn_hs_BO, .supply = supply);
sigbuf<N_SYN_X> rsb_syn_storage(.in = reset_syn_stge_BI, .out = reset_syn_stge_BO, .supply = supply);
INV_X1 nrn_reset_stge_inv(.a = register.data[0].d[6].t, .vdd = supply.vdd, .vss = supply.vss);
sigbuf<N_NRN_X> rsb_nrn_storage(.in = nrn_reset_stge_inv.y, .out = reset_nrn_stge_BO, .supply = supply);
}
export template<pint N_IN, // Size of input data from outside world
N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
N_SYN_DLY_CFG,
N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
N_BUFFERS,
N_LINE_PD_DLY, // Number of dummy delays to add line pull down
N_BD_DLY_CFG, N_BD_DLY_CFG2,
REG_NCA, REG_NCW, REG_M>
defproc texel_dualcore (bd<N_IN> in, out;
Mx1of2<REG_NCW> c1_reg_data[REG_M];
bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
bool? c1_dec_ackB[N_SYN_X];
a1of1 c1_syn_pu[N_SYN_X];
a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y];
a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y];
bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
bool! c1_reset_nrn_hs_BO[N_NRN_X], c1_reset_syn_hs_BO[N_SYN_X],
c1_reset_nrn_stge_BO[N_NRN_X], c1_reset_syn_stge_BO[N_SYN_X];
Mx1of2<REG_NCW> c2_reg_data[REG_M];
bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
bool? c2_dec_ackB[N_SYN_X];
a1of1 c2_syn_pu[N_SYN_X];
a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y];
a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y];
bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
bool! c2_reset_nrn_hs_BO[N_NRN_X], c2_reset_syn_hs_BO[N_SYN_X],
c2_reset_nrn_stge_BO[N_NRN_X], c2_reset_syn_stge_BO[N_SYN_X];
bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
bool? loopback_en;
power supply;
bool? reset_B, reset_reg_B, reset_syn_stge_BI
){
// Reset buffers
bool _reset_BX;
BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
.reset_B = _reset_BX, .supply = supply);
fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = _reset_BX, .supply = supply);
fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = _reset_BX, .supply = supply);
// Loopback
fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = _reset_BX, .supply = supply);
dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en,
.supply = supply);
fifo<N_IN,N_BUFFERS> fifo_drop2mrg(.in = _loopback_dropper.out, .reset_B = _reset_BX, .supply = supply);
// Onwards to core demux
fifo<N_IN,N_BUFFERS> fifo_fork2dmx(.in = _fork.out2, .reset_B = _reset_BX, .supply = supply);
demux_bit_msb<N_IN-1> core_dmx(.in = fifo_fork2dmx.out, .reset_B = _reset_BX, .supply = supply);
fifo<N_IN-1,N_BUFFERS> fifo_dmx2core1(.in = core_dmx.out1, .reset_B = _reset_BX, .supply = supply);
fifo<N_IN-1,N_BUFFERS> fifo_dmx2core2(.in = core_dmx.out2, .reset_B = _reset_BX, .supply = supply);
// Cores
texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
core1(.in = fifo_dmx2core1.out,
.reg_data = c1_reg_data,
// .synapses = c1_synapses,
// .neurons = c1_neurons,
.dec_req_x = c1_dec_req_x, .dec_req_y = c1_dec_req_y,
.dec_ackB = c1_dec_ackB,
.syn_pu = c1_syn_pu,
.enc_inx = c1_enc_inx, .enc_iny = c1_enc_iny,
.nrn_pd_x = c1_nrn_pd_x, .nrn_pd_y = c1_nrn_pd_y,
.nrn_mon_x = c1_nrn_mon_x, .nrn_mon_y = c1_nrn_mon_y,
.syn_mon_x = c1_syn_mon_x, .syn_mon_y = c1_syn_mon_y,
.syn_mon_AMZI = c1_syn_mon_AMZI, .nrn_mon_AMZI = c1_nrn_mon_AMZI,
.syn_mon_AMZO = c1_syn_mon_AMZO, .nrn_mon_AMZO = c1_nrn_mon_AMZO,
.syn_flags_EFO = c1_syn_flags_EFO, .nrn_flags_EFO = c1_nrn_flags_EFO,
.reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
.reset_syn_hs_BO = c1_reset_syn_hs_BO, .reset_syn_stge_BO = c1_reset_syn_stge_BO,
.reset_nrn_hs_BO = c1_reset_nrn_hs_BO, .reset_nrn_stge_BO = c1_reset_nrn_stge_BO,
.supply = supply
);
texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
core2(.in = fifo_dmx2core2.out,
.reg_data = c2_reg_data,
// .synapses = c2_synapses,
// .neurons = c2_neurons,
.dec_req_x = c2_dec_req_x, .dec_req_y = c2_dec_req_y,
.dec_ackB = c2_dec_ackB,
.syn_pu = c2_syn_pu,
.enc_inx = c2_enc_inx, .enc_iny = c2_enc_iny,
.nrn_pd_x = c2_nrn_pd_x, .nrn_pd_y = c2_nrn_pd_y,
.nrn_mon_x = c2_nrn_mon_x, .nrn_mon_y = c2_nrn_mon_y,
.syn_mon_x = c2_syn_mon_x, .syn_mon_y = c2_syn_mon_y,
.syn_mon_AMZI = c2_syn_mon_AMZI, .nrn_mon_AMZI = c2_nrn_mon_AMZI,
.syn_mon_AMZO = c2_syn_mon_AMZO, .nrn_mon_AMZO = c2_nrn_mon_AMZO,
.syn_flags_EFO = c2_syn_flags_EFO, .nrn_flags_EFO = c2_nrn_flags_EFO,
.reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
.reset_syn_hs_BO = c2_reset_syn_hs_BO, .reset_syn_stge_BO = c2_reset_syn_stge_BO,
.reset_nrn_hs_BO = c2_reset_nrn_hs_BO, .reset_nrn_stge_BO = c2_reset_nrn_stge_BO,
.supply = supply
);
fifo<N_IN-1,N_BUFFERS> fifo_core1out(.in = core1.out, .reset_B = _reset_BX, .supply = supply);
fifo<N_IN-1,N_BUFFERS> fifo_core2out(.in = core2.out, .reset_B = _reset_BX, .supply = supply);
// Merge cores
append<N_IN-1, 1, 0> append_core1(.in = fifo_core1out.out, .supply = supply);
append<N_IN-1, 1, 1> append_core2(.in = fifo_core2out.out, .supply = supply);
merge<N_IN> merge_core1x2(.in1 = append_core1.out, .in2 = append_core2.out,
.supply = supply, .reset_B = _reset_BX);
// Merge cores and loopback
merge<N_IN> merge_drop8core(.in1 = merge_core1x2.out, .in2 = fifo_drop2mrg.out,
.reset_B = _reset_BX, .supply = supply);
// qdi2bd
fifo<N_IN, N_BUFFERS> fifo_mrg2bd(.in = merge_drop8core.out,
.reset_B = _reset_BX, .supply = supply);
qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg,
.reset_B = _reset_BX, .supply = supply);
}
}
}

1146
dataflow_neuro/coders.act
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94
dataflow_neuro/dummy.act
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@@ -1,94 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import "../../dataflow_neuro/treegates.act";
import "../../dataflow_neuro/primitives.act";
// import tmpl::dataflow_neuro;
// import tmpl::dataflow_neuro;
import std::channel;
open std::channel;
namespace tmpl {
namespace dataflow_neuro {
/**
* Creates a synapse-neuron dummy block,
* where any synapse being triggered makes the neuron "spike".
*/
export template<pint N_SYN>
defproc dummy_neuron_block (a1of1 synapses[N_SYN], neuron; power supply){
// OR over reqs from syn in to neuron out
ortree<N_SYN> _ortree(.out = neuron.r, .supply = supply);
(i:N_SYN: _ortree.in[i] = synapses[i].r;)
// ANDs piping the ack back to the proper synapse
BUF_X12 nrn_ack_buf(.a = neuron.a, .vdd = supply.vdd, .vss = supply.vss);
AND2_X1 ands[N_SYN];
(i:N_SYN:
ands[i].a = nrn_ack_buf.y;
ands[i].b = synapses[i].r;
ands[i].y = synapses[i].a;
ands[i].vss = supply.vss;
ands[i].vdd = supply.vdd;
)
}
/**
* Create an array of neuron dummy blocks.
* Note that this is custom made for the indexing on the texel chip.
* And so should be reused *with care*.
*/
export template<pint N_SYN_PER_NRN, N_NRN, N_NRN_X>
defproc dummy_neuron_core (a1of1 synapses[N_SYN_PER_NRN * N_NRN], neurons[N_NRN]; power supply){
dummy_neuron_block<N_SYN_PER_NRN> blocks[N_NRN];
pint Xn, Yn, Xs, Ys;
(i:N_NRN:
Yn = i/N_NRN_X;
Xn = i-Yn*N_NRN_X;
neurons[i] = blocks[i].neuron;
blocks[i].supply = supply;
(j:N_SYN_PER_NRN: // moron, need to think about neuron indexxing too
Xs = Xn;
Ys = Yn*N_SYN_PER_NRN + j;
blocks[i].synapses[j] = synapses[Ys*N_NRN_X + Xs];
)
)
}
}
}

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dataflow_neuro/interfaces.act
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@@ -1,174 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import "../../dataflow_neuro/treegates.act";
import "../../dataflow_neuro/primitives.act";
import std::channel;
open std::channel;
// import std::func;
open std;
import std::data;
open std::data;
namespace tmpl {
namespace dataflow_neuro {
/**
* Bundled data (non dual rail, with req)
* 2
* quasi delay insensitive channel (dual rail).
* Basically a buffer with a bitwise conversion in front of it.
*/
export template<pint N, N_dly_cfg, N_dly_cfg2>
defproc bd2qdi(bd<N> in; avMx1of2<N> out; bool? dly_cfg[N_dly_cfg], dly_cfg2[N_dly_cfg2];
power supply; bool? reset_B) {
// Delay on req_in
bool _req;
delayprog<N_dly_cfg> dly(.in = in.r, .out = _req, .s = dly_cfg, .supply = supply);
// sig buff the reset signal
bool _reset_BX, _reset_BXX[N*2];
BUF_X4 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N*2> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
// sig buff the req
bool _reqX, _reqXX[N*2];
BUF_X4 req_buf(.a=_req, .y=_reqX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N*2> req_bufarray(.in=_reqX, .out=_reqXX, .supply=supply);
// For reasons of pure spice, the control circuitry
// requires a req signal that FALLS SLOWER than the req going to the function block.
// Thus need another delay prog.
bool _req_slowfall;
delayprog<N_dly_cfg2> dly2(.in = _reqX, .s = dly_cfg2, .supply = supply);
OR2_X1 req_dly_or(.a = _reqX, .b = dly2.out, .y = _req_slowfall,
.vss = supply.vss, .vdd = supply.vdd);
// bd2qdi conversion
// Each line goes to a t pin, its not to an f.
bool _inB[N];
INV_X1 input_invs[N];
(i:N:
input_invs[i].a = in.d[i];
input_invs[i].y = _inB[i];
input_invs[i].vss = supply.vss;
input_invs[i].vdd = supply.vdd;
)
// BUFFER
// Basically the buffer_s but with the validity tree ripped out
// and just connected to in_req instead.
// And probably need a delay on the in_ack to ensure en has time to disable
// before the inputs go to another state.
// Actually apparently no: there is a fixed, huge delay, already incurred
// by communicating with pads-> uC -> windows 95 and back again.
// Since the input is never invalid, also need a mechanism
// for the output to become invalid, when an out_ack is received.
//control
bool _en;
A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_req_slowfall,.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
//function
bool _out_a_B;
A_2C2N_RB_X4 f_buf_func[N];
A_2C2N_RB_X4 t_buf_func[N];
sigbuf<N*2> en_buf(.in=_en, .supply=supply);
INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N*2> out_a_B_buf(.in=_out_a_B, .supply=supply);
// check if you can also do single var to array connect a=b[N]
// and remove them from the loop
(i:N:
f_buf_func[i].y=out.d.d[i].f;
t_buf_func[i].y=out.d.d[i].t;
f_buf_func[i].c1=en_buf.out[i];
t_buf_func[i].c1=en_buf.out[i+N];
f_buf_func[i].c2=out_a_B_buf.out[i];
t_buf_func[i].c2=out_a_B_buf.out[i+N];
f_buf_func[i].n1=_inB[i];
t_buf_func[i].n1=in.d[i];
f_buf_func[i].n2=_reqXX[i];
t_buf_func[i].n2=_reqXX[i+N];
f_buf_func[i].vdd=supply.vdd;
t_buf_func[i].vdd=supply.vdd;
f_buf_func[i].vss=supply.vss;
t_buf_func[i].vss=supply.vss;
t_buf_func[i].pr_B = _reset_BXX[i];
t_buf_func[i].sr_B = _reset_BXX[i];
f_buf_func[i].pr_B = _reset_BXX[i+N];
f_buf_func[i].sr_B = _reset_BXX[i+N];
)
}
/**
* quasi delay insensitive channel (dual rail).
* 2
* Bundled data (non dual rail, with req)
*/
export template<pint N, N_dly_cfg>
defproc qdi2bd(avMx1of2<N> in; bd<N> out; bool? dly_cfg[N_dly_cfg]; power supply; bool? reset_B) {
// Buffer
buffer<N> buf(.in = in, .supply = supply, .reset_B = reset_B);
buf.out.a = out.a;
// Vtree
vtree<N> out_vtree(.supply = supply);
(i:N:
out_vtree.in.d[i].t = buf.out.d.d[i].t;
out_vtree.in.d[i].f = buf.out.d.d[i].f;
)
buf.out.v = out_vtree.out;
// Delay
delayprog<N_dly_cfg> dly(.in = out_vtree.out, .out = out.r, .s = dly_cfg, .supply = supply);
out_vtree.out = dly.in;
// Wire output data bits to buffer True lines
(i:N:
buf.out.d.d[i].t = out.d[i];
)
}
}
}

826
dataflow_neuro/primitives.act
View File

@@ -3,10 +3,6 @@
* This file is part of ACT dataflow neuro library
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
@@ -25,18 +21,12 @@
*
**************************************************************************
*/
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import "../../dataflow_neuro/treegates.act";
// import tmpl::dataflow_neuro;
// import tmpl::dataflow_neuro;
import template::dataflow_neuro::cell_lib_std;
import template::dataflow_neuro::cell_lib_async;
import std::channel;
open std::channel;
// import std::func;
namespace tmpl {
namespace template {
namespace dataflow_neuro {
// @ole talk to rajit, we use valid the wrong way arround according to stdlib
@@ -78,8 +68,8 @@ namespace tmpl {
[(&i:M: d.d[i].t | d.d[i].f)];
self := 0;
(;i:M: [ d.d[i].t -> self := self | (1 << i)
[] else -> skip
]
[] else -> skip
]
)
}
@@ -109,810 +99,46 @@ namespace tmpl {
*
*/
export template<pint N>
defproc buffer (avMx1of2<N> in; avMx1of2<N> out; bool? reset_B; power supply) {
defproc buffer (avMx1of2<N> in; avMx1of2<N> out; rsp reset; power supply) {
//control
bool _en, _reset_BX,_reset_BXX[N*2];
A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.v,.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N*2> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
bool _en,_en_X,_preset_X,_sreset_X;
A_3C_RB_X4 inack_ctl(c1=en_X,c2=in.v,c3=out.v,y=in.a,pr_B=_preset_X,sr_B=_sreset_X,vdd=supply.vdd,vss=supply.vss);
A_1C1P_X1 en_ctl(c1=in.a,p1=out.v,y=_en,vdd=supply.vdd,vss=supply.vss);
sigbuf en_buf<N*2>(a=_en, y=_en_X, power=supply);
sigbuf preset_buf<N*2>(a=reset.p,y=preset_X, power=supply);
sigbuf sreset_buf<N*2>(a=reset.s,y=sreset_X, power=supply);
//validity
bool _in_v;
vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
ctree vc<N>(in=in.d,y=_in_v, power=supply);
sigbuf in_v_buf<12>(a=_in_v, y=in.v);
//function
bool _out_a_BX[N*2],_out_a_B;
bool _out_a_BX, _out_a_B;
A_2C1N_RB_X4 f_buf_func[N];
A_2C1N_RB_X4 t_buf_func[N];
sigbuf<N*2> en_buf(.in=_en, .supply=supply);
INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N*2> out_a_B_buf(.in=_out_a_B,.out=_out_a_BX, .supply = supply);
INV_X1 out_a_inv(a=out.a,y=_out_a_B);
sigbuf out_a_B_buf<N*2>(a=_out_a_B,y=_out_a_BX);
// check if you can also do single var to array connect a=b[N]
// and remove them from the loop
(i:N:
f_buf_func[i].y=out.d.d[i].f;
t_buf_func[i].y=out.d.d[i].t;
f_buf_func[i].c1=en_buf.out[i];
t_buf_func[i].c1=en_buf.out[i+N];
f_buf_func[i].c2=_out_a_BX[i];
t_buf_func[i].c2=_out_a_BX[i+N];
f_buf_func[i].c1=_en_X;
t_buf_func[i].c1=_en_X;
f_buf_func[i].c2=_out_a_BX;
t_buf_func[i].c2=_out_a_BX;
f_buf_func[i].n1=in.d.d[i].f;
t_buf_func[i].n1=in.d.d[i].t;
f_buf_func[i].pr_B=_preset_X;
t_buf_func[i].pr_B=_preset_X;
f_buf_func[i].sr_B=_sreset_X;
t_buf_func[i].sr_B=_sreset_X;
f_buf_func[i].vdd=supply.vdd;
t_buf_func[i].vdd=supply.vdd;
f_buf_func[i].vss=supply.vss;
t_buf_func[i].vss=supply.vss;
t_buf_func[i].pr_B = _reset_BXX[i];
t_buf_func[i].sr_B = _reset_BXX[i];
f_buf_func[i].pr_B = _reset_BXX[i+N];
f_buf_func[i].sr_B = _reset_BXX[i+N];
)
}
// A template creating a FIFO of M buffers with N bits each
export template<pint N;pint M>
defproc fifo(avMx1of2<N> in; avMx1of2<N> out; bool? reset_B; power supply)
{
buffer<N> fifo_element[M];
bool _reset_BXX[M];
fifo_element[0].in = in ;
fifo_element[0].supply = supply;
fifo_element[0].reset_B = _reset_BXX[0];
(i:1..M-1:
fifo_element[i].in = fifo_element[i-1].out;
fifo_element[i].supply = supply;
fifo_element[i].reset_B = _reset_BXX[i];
)
fifo_element[M-1].out = out;
// reset buffers
bool _reset_BX;
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<M> reset_bufarray(.in=_reset_BX, .out=_reset_BXX,.supply = supply);
}
/**
* Buffer_S template.
* S maybe stands for special.
* Like a buffer, except that the output function block does not load the data in
* until the input data is valid.
* Not entirely sure what the point of it is,
* Ole says is useful for funky timing scenarios.
*/
export template<pint N>
defproc buffer_s (avMx1of2<N> in; avMx1of2<N> out; bool? reset_B; power supply) {
//control
bool _en, _reset_BX,_reset_BXX[N];
A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.v,.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
//validity
bool _in_v;
vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
BUF_X4 in_v_buf4(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N*2> in_v_bufN(.in = in.v, .supply = supply);
//function
bool _out_a_B;
A_2C2N_RB_X4 f_buf_func[N];
A_2C2N_RB_X4 t_buf_func[N];
sigbuf<N*2> en_buf(.in=_en, .supply=supply);
INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N*2> out_a_B_buf(.in=_out_a_B, .supply=supply);
// check if you can also do single var to array connect a=b[N]
// and remove them from the loop
(i:N:
f_buf_func[i].y=out.d.d[i].f;
t_buf_func[i].y=out.d.d[i].t;
f_buf_func[i].c1=en_buf.out[i];
t_buf_func[i].c1=en_buf.out[i+N];
f_buf_func[i].c2=out_a_B_buf.out[i];
t_buf_func[i].c2=out_a_B_buf.out[i+N];
f_buf_func[i].n1=in.d.d[i].f;
t_buf_func[i].n1=in.d.d[i].t;
f_buf_func[i].n2=in_v_bufN.out[i];
t_buf_func[i].n2=in_v_bufN.out[i+N];
f_buf_func[i].vdd=supply.vdd;
t_buf_func[i].vdd=supply.vdd;
f_buf_func[i].vss=supply.vss;
t_buf_func[i].vss=supply.vss;
t_buf_func[i].pr_B = _reset_BXX[i];
t_buf_func[i].sr_B = _reset_BXX[i];
f_buf_func[i].pr_B = _reset_BXX[i];
f_buf_func[i].sr_B = _reset_BXX[i];
)
}
// Note that in token false/0 is send on out1, true/1 is send on out2.
// test
export template<pint N>
defproc demux (avMx1of2<N> in; avMx1of2<N> out1; avMx1of2<N> out2; bool? reset_B; avMx1of2<1> cond; power supply) {
//control
bool _en, _reset_BX,_reset_BXX[2*N], _out_v, _in_c_v_;
OR2_X1 out_or(.a=out1.v, .b=out2.v, .y=_out_v,.vdd=supply.vdd,.vss=supply.vss);
A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_in_c_v_,.c3=_out_v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
cond.a = in.a; // @TODO THIS SHOULD BE IMPROVED UPON IN FUTURE VERSIONS
// actually it might be fine
cond.v = _in_c_v_;
A_1C1P_X1 en_ctl(.c1=in.a,.p1=_out_v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<2*N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
//validity
bool _in_v, _c_f_buf[N], _c_t_buf[N], _c_v;
sigbuf<N> c_buf_t(.in=cond.d.d[0].t, .out=_c_t_buf, .supply=supply);
sigbuf<N> c_buf_f(.in=cond.d.d[0].f, .out=_c_f_buf, .supply=supply);
OR2_X1 c_f_c_t_or(.a=cond.d.d[0].t, .b=cond.d.d[0].f, .y=_c_v,.vdd=supply.vdd,.vss=supply.vss);
vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
A_2C_B_X1 c_el(.c1=_c_v, .c2=_in_v, .y=_in_c_v_,.vdd=supply.vdd,.vss=supply.vss);
BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
//function
//func buffer out1
bool _out1_a_B;
A_2C2N_RB_X4 out1_f_buf_func[N];
A_2C2N_RB_X4 out1_t_buf_func[N];
sigbuf<N*4> out_en_buf(.in=_en, .supply=supply);
INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B, .vdd = supply.vdd, .vss = supply.vss);
sigbuf<N*2> out1_a_B_buf(.in=_out1_a_B, .supply=supply);
(i:N:
out1_f_buf_func[i].y=out1.d.d[i].f;
out1_t_buf_func[i].y=out1.d.d[i].t;
out1_f_buf_func[i].c1=out_en_buf.out[i];
out1_t_buf_func[i].c1=out_en_buf.out[i+N];
out1_f_buf_func[i].c2=out1_a_B_buf.out[i];
out1_t_buf_func[i].c2=out1_a_B_buf.out[i+N];
out1_f_buf_func[i].n1=in.d.d[i].f;
out1_t_buf_func[i].n1=in.d.d[i].t;
out1_f_buf_func[i].vdd=supply.vdd;
out1_t_buf_func[i].vdd=supply.vdd;
out1_f_buf_func[i].vss=supply.vss;
out1_t_buf_func[i].vss=supply.vss;
out1_t_buf_func[i].pr_B = _reset_BXX[i];
out1_t_buf_func[i].sr_B = _reset_BXX[i];
out1_f_buf_func[i].pr_B = _reset_BXX[i];
out1_f_buf_func[i].sr_B = _reset_BXX[i];
out1_f_buf_func[i].n2=_c_f_buf[i];
out1_t_buf_func[i].n2=_c_f_buf[i];
)
//func buffer out2
bool _out2_a_B;
A_2C2N_RB_X4 out2_f_buf_func[N];
A_2C2N_RB_X4 out2_t_buf_func[N];
// sigbuf<N*2> out2_en_buf(.in=_en, .supply=supply);
INV_X1 out2_a_inv(.a=out2.a,.y=_out2_a_B, .vdd = supply.vdd, .vss = supply.vss);
sigbuf<N*2> out2_a_B_buf(.in=_out2_a_B);
(i:N:
out2_f_buf_func[i].y=out2.d.d[i].f;
out2_t_buf_func[i].y=out2.d.d[i].t;
out2_f_buf_func[i].c1=out_en_buf.out[i+2*N];
out2_t_buf_func[i].c1=out_en_buf.out[i+3*N];
out2_f_buf_func[i].c2=out2_a_B_buf.out[i];
out2_t_buf_func[i].c2=out2_a_B_buf.out[i+N];
out2_f_buf_func[i].n1=in.d.d[i].f;
out2_t_buf_func[i].n1=in.d.d[i].t;
out2_f_buf_func[i].vdd=supply.vdd;
out2_t_buf_func[i].vdd=supply.vdd;
out2_f_buf_func[i].vss=supply.vss;
out2_t_buf_func[i].vss=supply.vss;
out2_t_buf_func[i].pr_B = _reset_BXX[i+N];
out2_t_buf_func[i].sr_B = _reset_BXX[i+N];
out2_f_buf_func[i].pr_B = _reset_BXX[i+N];
out2_f_buf_func[i].sr_B = _reset_BXX[i+N];
out2_f_buf_func[i].n2=_c_t_buf[i];
out2_t_buf_func[i].n2=_c_t_buf[i];
)
}
export template<pint N>
defproc fork (avMx1of2<N> in; avMx1of2<N> out1; avMx1of2<N> out2 ; bool? reset_B; power supply) {
// control
bool _en, _reset_BX,_reset_BXX[N*2];
A_4C_RB_X4 inack_ctl(.c1=_en,.c2=in.v,.c3=out1.v,.c4=out2.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_1C2P_X1 en_ctl(.c1=in.a,.p1=out1.v,.p2=out2.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
//reset_buffers
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N*2> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
//validity
bool _in_v;
vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
//function
//func buffer out1
bool _out1_a_B;
A_2C1N_RB_X4 out1_f_buf_func[N];
A_2C1N_RB_X4 out1_t_buf_func[N];
sigbuf<N*2> out1_en_buf(.in=_en, .supply=supply);
INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B);
sigbuf<N*2> out1_a_B_buf(.in=_out1_a_B);
(i:N:
out1_f_buf_func[i].y=out1.d.d[i].f;
out1_t_buf_func[i].y=out1.d.d[i].t;
out1_f_buf_func[i].c1=out1_en_buf.out[i];
out1_t_buf_func[i].c1=out1_en_buf.out[i+N];
out1_f_buf_func[i].c2=out1_a_B_buf.out[i];
out1_t_buf_func[i].c2=out1_a_B_buf.out[i+N];
out1_f_buf_func[i].n1=in.d.d[i].f;
out1_t_buf_func[i].n1=in.d.d[i].t;
out1_f_buf_func[i].vdd=supply.vdd;
out1_t_buf_func[i].vdd=supply.vdd;
out1_f_buf_func[i].vss=supply.vss;
out1_t_buf_func[i].vss=supply.vss;
out1_t_buf_func[i].pr_B = _reset_BXX[i];
out1_t_buf_func[i].sr_B = _reset_BXX[i];
out1_f_buf_func[i].pr_B = _reset_BXX[i];
out1_f_buf_func[i].sr_B = _reset_BXX[i];
)
//func buffer out2
bool _out2_a_B;
A_2C1N_RB_X4 out2_f_buf_func[N];
A_2C1N_RB_X4 out2_t_buf_func[N];
sigbuf<N*2> out2_en_buf(.in=_en, .supply=supply);
INV_X1 out2_a_inv(.a=out2.a,.y=_out2_a_B);
sigbuf<N*2> out2_a_B_buf(.in=_out2_a_B);
(i:N:
out2_f_buf_func[i].y=out2.d.d[i].f;
out2_t_buf_func[i].y=out2.d.d[i].t;
out2_f_buf_func[i].c1=out2_en_buf.out[i];
out2_t_buf_func[i].c1=out2_en_buf.out[i+N];
out2_f_buf_func[i].c2=out2_a_B_buf.out[i];
out2_t_buf_func[i].c2=out2_a_B_buf.out[i+N];
out2_f_buf_func[i].n1=in.d.d[i].f;
out2_t_buf_func[i].n1=in.d.d[i].t;
out2_f_buf_func[i].vdd=supply.vdd;
out2_t_buf_func[i].vdd=supply.vdd;
out2_f_buf_func[i].vss=supply.vss;
out2_t_buf_func[i].vss=supply.vss;
out2_t_buf_func[i].pr_B = _reset_BXX[i];
out2_t_buf_func[i].sr_B = _reset_BXX[i];
out2_f_buf_func[i].pr_B = _reset_BXX[i];
out2_f_buf_func[i].sr_B = _reset_BXX[i];
)
}
// Demux
export template<pint N; pbool CONDITION_SIGN>
// @TODO docs
// also note this is not used in the final texel chip
defproc demux_td (avMx1of2<N> in; avMx1of2<N> out; a1of1 token; bool? reset_B; avMx1of2<1> cond; power supply) {
//control
bool _en, _reset_BX,_reset_BXX[N], _out_v, _in_c_v_, _reset_BXt;
avMx1of2<N> out1 = out;
OR2_X1 out_or(.a=out1.v, .b=token.r, .y=_out_v,.vdd=supply.vdd,.vss=supply.vss);
A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_in_c_v_,.c3= _out_v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_1C1P_X1 en_ctl(.c1=in.a,.p1=_out_v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf_token(.a=_reset_BX, .y=_reset_BXt,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
//validity
bool _in_v, _c_tk_buf, _c_d_buf[N], _c_v, cond_inv_t, cond_inv_f;
cond.a = in.a;
cond.v = _c_v;
OR2_X1 c_f_c_t_or(.a=cond.d.d[0].t, .b=cond.d.d[0].f, .y=_c_v,.vdd=supply.vdd,.vss=supply.vss);
//orientation of condition
[ CONDITION_SIGN ->
BUF_X1 c_buf_tk(.a=cond.d.d[0].t, .y=_c_tk_buf, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N> c_buf_d(.in=cond.d.d[0].f, .out=_c_d_buf, .supply=supply);
[] else ->
BUF_X1 c_buf_tk(.a=cond.d.d[0].f, .y=_c_tk_buf, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N> c_buf_d(.in=cond.d.d[0].t, .out=_c_d_buf, .supply=supply);
]
vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
A_2C_B_X1 c_el(.c1=_c_v, .c2=_in_v, .y=_in_c_v_,.vdd=supply.vdd,.vss=supply.vss);
BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
//function
//func buffer out1
bool _out1_a_B;
A_2C2N_RB_X4 out1_f_buf_func[N];
A_2C2N_RB_X4 out1_t_buf_func[N];
sigbuf<N*2> out1_en_buf(.in=_en, .supply=supply);
INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N*2> out1_a_B_buf(.in=_out1_a_B, .supply=supply);
(i:N:
out1_f_buf_func[i].y=out1.d.d[i].f;
out1_t_buf_func[i].y=out1.d.d[i].t;
out1_f_buf_func[i].c1=out1_en_buf.out[i];
out1_t_buf_func[i].c1=out1_en_buf.out[i+N];
out1_f_buf_func[i].c2=out1_a_B_buf.out[i];
out1_t_buf_func[i].c2=out1_a_B_buf.out[i+N];
out1_f_buf_func[i].n1=in.d.d[i].f;
out1_t_buf_func[i].n1=in.d.d[i].t;
out1_f_buf_func[i].vdd=supply.vdd;
out1_t_buf_func[i].vdd=supply.vdd;
out1_f_buf_func[i].vss=supply.vss;
out1_t_buf_func[i].vss=supply.vss;
out1_t_buf_func[i].pr_B = _reset_BXX[i];
out1_t_buf_func[i].sr_B = _reset_BXX[i];
out1_f_buf_func[i].pr_B = _reset_BXX[i];
out1_f_buf_func[i].sr_B = _reset_BXX[i];
out1_f_buf_func[i].n2=_c_d_buf[i];
out1_t_buf_func[i].n2=_c_d_buf[i];
)
//token out
bool token_a_out;
A_2C2N_RB_X4 token_buf;
INV_X1 outt_a_inv(.a=token.a,.y=token_a_out, .vss = supply.vss, .vdd = supply.vdd);
token_buf.y = token.r;
token_buf.c1 = _en;
token_buf.c2 = token_a_out;
token_buf.n1 = _c_tk_buf;
token_buf.n2 = _in_v;
token_buf.vdd = supply.vdd;
token_buf.vss = supply.vss;
token_buf.pr_B = _reset_BXt;
token_buf.sr_B = _reset_BXt;
}
/**
* Drops a packet if condition is met, otherwise passes it on.
* This is a very lazy implementation, where the cond MUST NOT CHANGE DURING OPERATION.
* Means that this should be used in a very small set of circumstances.
*
* params:
* N: size of packet
* CONDITION_DROP: value of cond when packets are dropped.
*/
export template<pint N; pbool CONDITION_DROP>
defproc dropper_static (avMx1of2<N> in; avMx1of2<N> out; bool? cond; power supply) {
bool _drop, _dropB;
INV_X1 inv(.a = cond, .vss = supply.vss, .vdd = supply.vdd);
[~CONDITION_DROP ->
_dropB = cond;
_drop = inv.y;
[] CONDITION_DROP ->
_drop = cond;
_dropB = inv.y;
]
bool _in_vX;
vtree<N> vt(.in = in.d, .supply = supply);
BUF_X4 in_v_buf(.a = vt.out, .y = _in_vX, .vss = supply.vss, .vdd = supply.vdd);
AND2_X1 and2(.a = _drop, .b = _in_vX, .vss = supply.vss, .vdd = supply.vdd);
OR2_X1 or2(.a = out.a, .b = and2.y, .vss = supply.vss, .vdd = supply.vdd);
A_2C_B_X1 ack_Cel(.c1 = or2.y, .c2 = _in_vX, .y = in.a);
// _in_vX = in.v;
// Sigbufs
sigbuf<N*2> sb_dropB(.in = _dropB, .supply = supply);
sigbuf<N*2+1> sb_in_v(.in = _in_vX, .supply = supply);
sb_in_v.out[2*N] = in.v;
AND3_X1 and_t[N];
AND3_X1 and_f[N];
(i:N:
and_t[i].a = in.d.d[i].t;
and_f[i].a = in.d.d[i].f;
and_t[i].y = out.d.d[i].t;
and_f[i].y = out.d.d[i].f;
and_t[i].b = sb_dropB.out[i];
and_f[i].b = sb_dropB.out[i+N];
and_t[i].c = sb_in_v.out[i];
and_f[i].c = sb_in_v.out[i+N];
and_t[i].vss = supply.vss;
and_t[i].vdd = supply.vdd;
)
}
export
defproc arbiter_handshake(a1of1 in1; a1of1 in2; a1of1 out; power supply)
{
bool _y1_arb,_y2_arb;
A_2C_B_X1 ack_cell1(.c1 = out.a,.c2 = _y1_arb,.y = in1.a,.vdd = supply.vdd, .vss = supply.vss);
A_2C_B_X1 ack_cell2(.c1 = out.a,.c2 = _y2_arb,.y = in2.a,.vdd = supply.vdd, .vss = supply.vss);
OR2_X1 or_cell(.a = _y1_arb, .b = _y2_arb, .y = out.r,.vdd = supply.vdd, .vss = supply.vss);
ARBITER arbiter(.a = in1.r, .b = in2.r, .c = in2.a, .d = in1.a, .y1 = _y1_arb, .y2 = _y2_arb, .vdd = supply.vdd, .vss = supply.vss);
}
//The buffer_t_valid doesn't work
// export
// defproc buffer_t_valid(a1of1 in; a1of1 out; bool? reset_B; power supply)
// {
// //control
// bool _en, _reset_BX;
// A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.r,.c3=out.r,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
// A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.r,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
// //function
// bool _out_a_B;
// INV_X1 inv_outa(.a = out.a,.y=_out_a_B,.vdd = supply.vdd,.vss=supply.vss);
// A_2C1N_RB_X4 buf_func(.c1 = _en,.c2 = _out_a_B, .n1 = in.r,.y = out.r, .pr_B = _reset_BX, .sr_B = _reset_BX,.vdd = supply.vdd,.vss=supply.vss);
// //reset buffers
// BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
// }
export template<pint N>
defproc merge (avMx1of2<N> in1; avMx1of2<N> in2; avMx1of2<N> out ; bool? reset_B; power supply) {
//out acknowledge sigbuffer and inverter
bool _out_a_B,_out_a_BX[2*N];
INV_X1 out_a_inverter(.a = out.a, .y = _out_a_B);
sigbuf<2*N> out_a_buffer(.in = _out_a_B,.out = _out_a_BX,.supply=supply);
//control
bool _in1_a_B,_in2_a_B,_en,_en_X[2*N], _reset_BX,_reset_BXX[2*N];
bool _in1_arb,_in2_arb,_in1_arb_X[2*N],_in2_arb_X[2*N];
A_4C_RB_X4 in1ack_ctl(.c1=_in1_arb,.c2=_en,.c3=in1.v,.c4=out.v,.y=in1.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_4C_RB_X4 in2ack_ctl(.c1=_in2_arb,.c2=_en,.c3=in2.v,.c4=out.v,.y=in2.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_4P1N1N_X1 en_ctl(.p1 = in1.a,.p2=in2.a,.p3=out.a,.p4 = out.v, .na1 = in1.a,.nb1 = in2.a,.y = _en,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<2*N> en_buffer(.in = _en,.out = _en_X,.supply=supply);
INV_X1 in1ack_ctl_inv(.a=in1.a,.y=_in1_a_B,.vdd=supply.vdd,.vss=supply.vss);
INV_X1 in2ack_ctl_inv(.a=in2.a,.y=_in2_a_B,.vdd=supply.vdd,.vss=supply.vss);
//reset_buffers
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N*2> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
//validity
a1of1 _in1_temp,_in2_temp,_out_temp;
bool _in1_arb_temp,_in2_arb_temp;
vtree<N> vc1(.in=in1.d,.out=in1.v,.supply=supply);
vtree<N> vc2(.in=in2.d,.out=in2.v,.supply=supply);
arbiter_handshake validity_arb(.in1 = _in1_temp,.in2 = _in2_temp,.out =_out_temp, .supply = supply);
_in1_temp.r = in1.v;
_in2_temp.r = in2.v;
_in1_temp.a = _in1_arb_temp;
_in2_temp.a = _in2_arb_temp;
_out_temp.r = _out_temp.a;
AND2_X1 AND_arb1(.a = _in2_a_B,.b = _in1_arb_temp, .y = _in1_arb);
AND2_X1 AND_arb2(.a = _in1_a_B,.b = _in2_arb_temp, .y = _in2_arb);
sigbuf<2*N> arb2function1(.in = _in1_arb,.out = _in1_arb_X,.supply=supply);
sigbuf<2*N> arb2function2(.in = _in2_arb,.out = _in2_arb_X,.supply=supply);
//function
A_2C2N2N_RB_X1 merge_func_t[N];
A_2C2N2N_RB_X1 merge_func_f[N];
(i:N:
merge_func_t[i].c1 = _en_X[i];
merge_func_t[i].c2 = _out_a_BX[i];
merge_func_t[i].na1 = _in1_arb_X[i];
merge_func_t[i].na2 = in1.d.d[i].t;
merge_func_t[i].nb1 = _in2_arb_X[i];
merge_func_t[i].nb2 = in2.d.d[i].t;
merge_func_t[i].y = out.d.d[i].t;
merge_func_t[i].vdd=supply.vdd;
merge_func_t[i].vss=supply.vss;
merge_func_t[i].pr_B = _reset_BXX[i];
merge_func_t[i].sr_B = _reset_BXX[i];
merge_func_f[i].c1 = _en_X[i+N];
merge_func_f[i].c2 = _out_a_BX[i+N];
merge_func_f[i].na1 = _in1_arb_X[i+N];
merge_func_f[i].na2 = in1.d.d[i].f;
merge_func_f[i].nb1 = _in2_arb_X[i+N];
merge_func_f[i].nb2 = in2.d.d[i].f;
merge_func_f[i].y = out.d.d[i].f;
merge_func_f[i].vdd=supply.vdd;
merge_func_f[i].vss=supply.vss;
merge_func_f[i].pr_B = _reset_BXX[i+N];
merge_func_f[i].sr_B = _reset_BXX[i+N];
)
}
export
defproc buffer_t(a1of1 in; a1of1 out; bool? reset_B; power supply)
{
//control
bool _en, _reset_BX;
A_2C1N_RB_X4 inack_ctl(.c1=_en,.c2=in.r,.n1=out.r,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.r,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
//function
bool _out_a_B;
INV_X1 inv_outa(.a = out.a,.y=_out_a_B,.vdd = supply.vdd,.vss=supply.vss);
A_2C1N_RB_X4 buf_func(.c1 = _en,.c2 = _out_a_B, .n1 = in.r,.y = out.r, .pr_B = _reset_BX, .sr_B = _reset_BX,.vdd = supply.vdd,.vss=supply.vss);
//reset buffers
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
}
// A template creating a FIFO of N buffers tokens
export template<pint N>
defproc fifo_t(a1of1 in; a1of1 out; bool? reset_B; power supply)
{
buffer_t fifo_element[N];
bool _reset_BXX[N];
fifo_element[0].in.r = in.r;
fifo_element[0].in.a = in.a;
fifo_element[0].supply = supply;
fifo_element[0].reset_B = _reset_BXX[0];
(i:1..N-1:
fifo_element[i].in.r = fifo_element[i-1].out.r;
fifo_element[i].in.a = fifo_element[i-1].out.a;
fifo_element[i].supply = supply;
fifo_element[i].reset_B = _reset_BXX[i];
)
fifo_element[N-1].out.r = out.r;
fifo_element[N-1].out.a = out.a;
// reset buffers
bool _reset_BX;
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply = supply);
}
// Programmable delay line.
// N is the number of layers,
// the longest layer having 2**N DLY elements
// Circuit for creating delays, there are N delay layers.
// The block has the parameters:
// N -> the number is the number of layers with the longest being 2**N elements
// wl -> word length, length of each word
// N_dly_cfg -> the number of config bits in the ACK delay line
// The block has the pins:
// in -> input data
// out -> output data
// s -> bit word with size N that sets delay configuration. int(s) = number of delays
export template<pint N>
defproc delayprog (bool! out; bool? in, s[N]; power supply)
{
{ N >= 0 : "What?" };
{ N < 10 : "Delay prog size is given in 2**N. Given N is ridiculous." };
AND2_X1 and2[N];
MUX2_X1 mu2[N];
DLY4_X1 dly[(1<<N) -1];
bool _a[N+1]; // Holds the input to each row
_a[0] = in;
pint i_delay;
i_delay = 0; // Index of the last connected delay element
(i:0..N-1:
// For each row
and2[i].a = _a[i];
and2[i].b = s[i];
// Delays
dly[i_delay].a = and2[i].y;
i_delay = i_delay + 1;
(j:1..(1<<i)-1:
dly[i_delay].a = dly[i_delay-1].y;
i_delay = i_delay +1;
)
// Mux
mu2[i].a = _a[i];
mu2[i].s = s[i];
dly[i_delay-1].y = mu2[i].b;
_a[i+1] = mu2[i].y;
)
out = mu2[N-1].y;
// Connect everything to vdd/gnd
(i:N:and2[i].vdd = supply.vdd;)
(i:N:mu2[i].vdd = supply.vdd;)
(i:((1<<N)-1):dly[i].vdd = supply.vdd;)
(i:N:and2[i].vss = supply.vss;)
(i:N:mu2[i].vss = supply.vss;)
(i:((1<<N)-1):dly[i].vss = supply.vss;)
}
// Non programmable delays
// N is number of delays to have in series (not log!!).
// Is useful for testing purposes.
// But should probably remove before running innovus etc.
export template<pint N>
defproc delay_chain (bool out; bool in; power supply) {
{ N >= 0 : "What?" };
[N >= 1 ->
DLY4_X1 dly[N];
dly[0].vdd = supply.vdd;
dly[0].vss = supply.vss;
dly[0].a = in;
(i:1..N-1:
dly[i].vdd = supply.vdd;
dly[i].vss = supply.vss;
dly[i].a = dly[i-1].y;
)
dly[N-1].vdd = supply.vdd;
dly[N-1].vss = supply.vss;
dly[N-1].y = out;
[] N = 0 ->
in = out;
]
}
/**
* Appends a hard-coded word "VAL" to an input.
* Works by piping through all sigs, but adding
* some extra sigs when the input is valid.
* N is size of channel to pipe through.
* NVAL is size of word to be put on output.
* VAL is word to be put on output.
* Output looks like
* 0..............N........N+NVAL-1
* --input_data----LSB....MSB
*
*/
export template<pint N, NVAL, VAL>
defproc append (avMx1of2<N> in; avMx1of2<N+NVAL> out; power supply)
{
{ N >= 0 : "What?" };
{ NVAL >= 0 : "What?" };
{ VAL < 1<<NVAL : "VAL too big!" };
// valid tree
vtree<N> in_val(.supply = supply);
(i:N:
in_val.in.d[i].t = in.d.d[i].t;
in_val.in.d[i].f = in.d.d[i].f;
)
// wire through most signals
(i:N:
in.d.d[i].t = out.d.d[i].t;
in.d.d[i].f = out.d.d[i].f;
)
in.a = out.a;
in.v = out.v;
// appender
pint bitval;
sigbuf<NVAL> sb(.in = in_val.out, .supply = supply);
TIELO_X1 tielows[NVAL];
(i:NVAL:tielows[i].vss = supply.vss; tielows[i].vdd = supply.vdd;)
(i:0..NVAL-1:
bitval = (VAL & ( 1 << i )) >> i;
[ bitval = 1 ->
out.d.d[i+N].t = sb.out[i];
out.d.d[i+N].f = tielows[i].y;
[] bitval = 0 ->
out.d.d[i+N].f = sb.out[i];
out.d.d[i+N].t = tielows[i].y;
[] bitval >= 2 -> {false : "fuck"};
]
)
}
/**
* Drops bits. Slices lines. Crop in. Enhance.
* Useful if say, have an 8 bit packet coming in, but
* receiver only needs 3 of them.
* KEEPS all bits between the two bounds.
* e.g. drop_lines(8, 0, 3) would keep lines [0,1,2]
**/
export template<pint N, N0, N1>
defproc slice_data(avMx1of2<N> in; avMx1of2<std::min(N1,N)-std::max(N0,0)> out; power supply) {
// {N0 >= 0 : "N0 can be minimum 0!"};
// {N1 <= N : "N1 can be maximum N"};
pint _N1, _N0;
_N1 = std::min(N1,N);
_N0 = std::max(N0,0);
[_N0 = 0 & _N1 = N ->
in = out;
[] _N0 != 0 | _N1 != N ->
vtree<N> in_vt(.in = in.d, .out = in.v, .supply = supply);
(i:_N1-_N0:
in.d.d[i + _N0] = out.d.d[i];
)
// in.a = out.a;
A_2C_B_X1 Cel(.c1 = out.a, .c2 =in.v, .y = in.a, .vss = supply.vss, .vdd = supply.vdd);
]
}
}
// this is a wrapper for the demux, such that the condition bit is absorbed into the data
// and demux msb is just defaulting it to the msb
export template<pint N; pint CONDITION_BIT>
defproc demux_bit (avMx1of2<N+1> in; avMx1of2<N> out1; avMx1of2<N> out2; bool? reset_B; power supply)
{
demux<N> demux(.reset_B = reset_B, .out1=out1, .out2=out2);
in.d.d[CONDITION_BIT].f = demux.cond.d.d[0].f;
in.d.d[CONDITION_BIT].t = demux.cond.d.d[0].t;
A_2C_B_X1 val_Cel(.c1 = demux.in.v, .c2 = demux.cond.v, .y = in.v,
.vdd = supply.vdd, .vss = supply.vss);
// Not actually needed bc the current version of demux
// Something like below should be added once the handshakes are properly decoupled.
// wires the data and cond ack lines together anyway.
// A_2C_B_X1 ack_Cel(.c1 = demux.in.a, .c2 = demux.cond.a, .y = in.a,
// .vdd = supply.vdd, .vss = supply.vss);
// in.v = demux.in.v;
in.a = demux.in.a;
(i:0..CONDITION_BIT-1:
in.d.d[i].f = demux.in.d.d[i].f;
in.d.d[i].t = demux.in.d.d[i].t;)
(i:CONDITION_BIT+1..N:
in.d.d[i].f = demux.in.d.d[i-1].f;
in.d.d[i].t = demux.in.d.d[i-1].t;)
}
export template<pint N>
defproc demux_bit_msb (avMx1of2<N+1> in; avMx1of2<N> out1; avMx1of2<N> out2; bool? reset_B; power supply)
{
demux_bit<N,N> demux(.in = in, .out1 = out1, .out2 = out2, .reset_B = reset_B, .out1=out1, .out2=out2);
}
/**
* Create M sigbufs to buffer an M bool array to N strength.
* Done lazily.
**/
export template<pint M, N>
defproc sigbuf_boolarray(bool? in[M]; bool! out[M]; power supply) {
sigbuf<N> sb[M];
(i:M:
sb[i].in = in[i];
sb[i].out[0] = out[i];
sb[i].supply = supply;
)
}
}}

352
dataflow_neuro/registers.act
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@@ -1,352 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import "../../dataflow_neuro/treegates.act";
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/coders.act";
// import tmpl::dataflow_neuro;
// import tmpl::dataflow_neuro;
import std::channel;
open std::channel;
namespace tmpl {
namespace dataflow_neuro {
/**
* A single register made out of A cells.
* MSB is whether to read or write.
* Currently only handles writing.
* NOTE: this does not handle in.v properly, and instead has in.v = in.a
*/
//@TODO Get rid of scarying warning
export template<pint N>
defproc register_acells_improved(avMx1of2<N+1> in; Mx1of2<N> out;
bool? reset_B; power supply) {
bool _resetX[N], _reset_BX[N];
bool _en, _enBX;
bool _flush, _flushBX;
bool _out_v, _out_vB;
bool _w = in.d.d[N].t;
INV_X2 out_val_inv(.a = _out_v, .y = _out_vB,
.vdd = supply.vdd, .vss= supply.vss);
// Reset sigs
INV_X1 reset_inv(.a = reset_B, .vdd = supply.vdd, .vss = supply.vss);
sigbuf<N> reset_sb(.in = reset_inv.y, .out = _resetX, .supply = supply);
sigbuf<N> resetB_sb(.in=reset_B, .out=_reset_BX, .supply = supply);
A_2C1N_RB_X1 A_flush(.c1 = _en, .c2 = _out_v, .n1 = _w, .y = _flush,
.vdd = supply.vdd, .vss = supply.vss, .pr_B = _reset_BX[0], .sr_B = _reset_BX[0]);
A_2C_X1 A_en(.c1 = _w, .c2 = _out_vB, .y = _en,
.vdd = supply.vdd, .vss = supply.vss);
INV_X1 flush_inv(.a = _flush, .vdd = supply.vdd, .vss = supply.vss);
sigbuf<N*2> sb_flushB(.in = flush_inv.y, .supply = supply);
sb_flushB.out[0] = _flushBX;
INV_X1 en_inv(.a = _en, .vdd = supply.vdd, .vss = supply.vss);
sigbuf<N*2> sb_enB(.in = en_inv.y, .supply = supply);
sb_enB.out[0] = _enBX;
vtree<N> vc(.in = out, .out = _out_v, .supply = supply);
// WARNING WARNING
in.v = in.a;
A_1C1P_X1 A_ack(.c1 = _en, .p1 = _out_vB, .y = in.a,
.vdd = supply.vdd, .vss = supply.vss);
//function
A_2C1N_SB_X4 f_buf_func[N];
A_2C1N_RB_X4 t_buf_func[N];
(i:N:
f_buf_func[i].y=out.d[i].f;
t_buf_func[i].y=out.d[i].t;
f_buf_func[i].c1=_flushBX;
t_buf_func[i].c1=_flushBX;
f_buf_func[i].c2=_enBX;
t_buf_func[i].c2=_enBX;
f_buf_func[i].n1=in.d.d[i].f;
t_buf_func[i].n1=in.d.d[i].t;
f_buf_func[i].vdd=supply.vdd;
t_buf_func[i].vdd=supply.vdd;
f_buf_func[i].vss=supply.vss;
t_buf_func[i].vss=supply.vss;
f_buf_func[i].pr = _resetX[i];
f_buf_func[i].sr = _resetX[i];
t_buf_func[i].pr_B = _reset_BX[i];
t_buf_func[i].sr_B = _reset_BX[i];
)
}
/**
* Array of registers made out of A-cells
* params:
* NcW: number of bits in Words to be stored in buffers
* NcA: number of bits in Address
* M: number of registers. M = 2^Nc_addr would be a natural choice.
* Input packets should be
* [-addr-][-word-][r/w]
*/
export template<pint NcA, NcW, M>
defproc register_wr_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M]; avMx1of2<NcA+NcW> out;
bool? reset_B; power supply) {
// Input valid tree
vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
.supply = supply);
// Address decoder
decoder_dualrail<NcA, M> decoder(.supply = supply);
(i:NcA:
decoder.in.d[i] = in.d.d[i];
)
// OrTree over acks from all registers
ortree<M> ack_ortree(.supply = supply);
bool _write_ack;
// C element handling in ack
A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = _write_ack,
.vss = supply.vss, .vdd = supply.vdd);
// Bit to join the acks either from read or write
bool _read_ack;
_read_ack = out.a;
OR2_X1 ack_rw_or(.a = _read_ack, .b = _write_ack,
.vdd = supply.vdd, .vss = supply.vss);
A_2C_B_X1 ack_safety(.c1 = ack_rw_or.y, .c2 = in.v, .y = in.a);
// Write bit selector
bool _w = in.d.d[NcA+NcW].t;
bool _wX[M];
sigbuf<M> _w_sb(.in = _w, .out = _wX, .supply = supply);
A_2C_B_X1 write_selectors[M];
(i:M:
write_selectors[i].c1 = _wX[i];
write_selectors[i].c2 = decoder.out[i];
write_selectors[i].vdd = supply.vdd;
write_selectors[i].vss = supply.vss;
)
// Registers
register_acells_improved<NcW> registers[M];
TIELO_X1 tielow_writebit_f[M];
(i:M:
// Connect each register to word inputs.
(j:NcW:
registers[i].in.d.d[j] = in.d.d[j + NcA];
)
// Connect the (selected) write bit
registers[i].in.d.d[NcW].t = write_selectors[i].y;
tielow_writebit_f[i].vdd = supply.vdd;
tielow_writebit_f[i].vss = supply.vss;
registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y;
// Connect to ack ortree
registers[i].in.a = ack_ortree.in[i];
// Connect outputs
data[i] = registers[i].out;
registers[i].supply = supply;
registers[i].reset_B = reset_B;
)
// Read bit selector
bool _r = in.d.d[NcA+NcW].f;
bool _rX[M+NcA];
sigbuf<M+NcA> _r_sb(.in = _r, .out = _rX, .supply = supply);
A_2C_B_X1 read_selectors[M];
sigbuf_boolarray<M, NcW*2> read_selectorsX(.supply = supply);
(i:M:
read_selectors[i].c1 = _rX[i];
read_selectors[i].c2 = decoder.out[i];
read_selectors[i].vdd = supply.vdd;
read_selectors[i].vss = supply.vss;
read_selectorsX.in[i] = read_selectors[i].y;
)
// OrTrees for each output word bit on read
ortree<M> out_ortrees_t[NcW];
ortree<M> out_ortrees_f[NcW];
(i:NcW:
out_ortrees_t[i].out = out.d.d[i+NcA].t;
out_ortrees_f[i].out = out.d.d[i+NcA].f;
out_ortrees_t[i].supply = supply;
out_ortrees_f[i].supply = supply;
)
// ANDs over each reg's data
// and whether it is selected for read.
AND2_X1 and_reads_t[NcW * M];
AND2_X1 and_reads_f[NcW * M];
pint index;
(i:NcW:
(j:M:
index = i + j*NcW;
and_reads_t[index].a = data[j].d[i].t;
and_reads_t[index].b = read_selectorsX.out[j];
and_reads_f[index].a = data[j].d[i].f;
and_reads_f[index].b = read_selectorsX.out[j];
and_reads_t[index].y = out_ortrees_t[i].in[j];
and_reads_f[index].y = out_ortrees_f[i].in[j];
and_reads_t[index].vss = supply.vss;
and_reads_t[index].vdd = supply.vdd;
and_reads_f[index].vss = supply.vss;
and_reads_f[index].vdd = supply.vdd;
)
)
// C elements passing address to out on read.
A_2C_B_X1 addr_read_t[NcA];
A_2C_B_X1 addr_read_f[NcA];
(i:NcA:
addr_read_t[i].c1 = in.d.d[i].t;
addr_read_f[i].c1 = in.d.d[i].f;
addr_read_t[i].c2 = _rX[M+i];
addr_read_f[i].c2 = _rX[M+i];
addr_read_t[i].y = out.d.d[i].t;
addr_read_f[i].y = out.d.d[i].f;
addr_read_t[i].vdd = supply.vdd;
addr_read_t[i].vss = supply.vss;
addr_read_f[i].vdd = supply.vdd;
addr_read_f[i].vss = supply.vss;
)
}
/**
* Array of registers made out of A-cells.
* !!!Registers ONLY have write functionality!!!
* params:
* NcW: number of bits in Words to be stored in buffers
* NcA: number of bits in Address
* M: number of registers. M = 2^Nc_addr would be a natural choice.
* Input packets should be
* LSB [-addr-][-word-] MSB
*/
//@TODO check if it is used
export template<pint NcA, NcW, M>
defproc register_w_array(avMx1of2<NcA + NcW> in; Mx1of2<NcW> data[M]; avMx1of2<NcA+NcW> out;
bool? reset_B; power supply) {
// Input valid tree
vtree<NcA + NcW> input_valid(.in = in.d, .out = in.v,
.supply = supply);
// Address decoder
decoder_dualrail<NcA, M> decoder(.supply = supply);
(i:NcA:
decoder.in.d[i] = in.d.d[i];
)
// OrTree over acks from all registers
ortree<M> ack_ortree(.supply = supply);
bool _write_ack;
// C element handling in ack
A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = _write_ack,
.vss = supply.vss, .vdd = supply.vdd);
A_2C_B_X1 ack_safety(.c1 = _write_ack, .c2 = in.v, .y = in.a);
// Registers
register_acells_improved<NcW> registers[M];
TIELO_X1 tielow_writebit_f[M];
(i:M:
// Connect each register to word inputs.
(j:NcW:
registers[i].in.d.d[j] = in.d.d[j + NcA];
)
// Connect the (selected) write bit
registers[i].in.d.d[NcW].t = decoder.out[i];
tielow_writebit_f[i].vdd = supply.vdd;
tielow_writebit_f[i].vss = supply.vss;
registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y;
// Connect to ack ortree
registers[i].in.a = ack_ortree.in[i];
// Connect outputs
data[i] = registers[i].out;
registers[i].supply = supply;
registers[i].reset_B = reset_B;
)
}
}}

454
dataflow_neuro/treegates.act
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@@ -1,454 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Madison Cotteret
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2021 Rajit Manohar
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************/
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import std::channel;
open std::channel;
namespace tmpl {
namespace dataflow_neuro {
/*
* Build an OR-gate tree (NOR/NAND/optional INV)
*/
export deftype power (bool?! vdd, vss) { }
export template<pint N>
defproc ortree (bool? in[N]; bool! out; power supply)
{
bool tout;
{ N > 0 : "What?" };
[N = 1 -> BUF_X1 b(.vss=supply.vss, .vdd = supply.vdd, .a = in[0], .y = out);
[] N > 1 ->
pint i, end, j;
i = 0;
end = N-1;
pint lenTree2Count, lenTree3Count;
lenTree2Count = 0;
lenTree3Count = 0;
/* Pre"calculate" the number of C cells required, look below if confused */
*[ i != end ->
j = 0;
*[ i < end ->
j = j + 1;
[ i+1 >= end ->
i = end;
lenTree2Count = lenTree2Count +1;
[] i+2 >= end ->
i = end;
lenTree3Count = lenTree3Count +1;
[] else ->
i = i + 2;
lenTree2Count = lenTree2Count +1;
]
]
/*-- update range that has to be combined --*/
i = end+1;
end = end+j;
j = 0;
]
/* array that holds ALL the nodes in the completion tree */
bool tmp[end+1];
(k:N:tmp[k] = in[k];)
/* array to hold the actual C-elments, either A2C or A3C */
[lenTree2Count > 0 ->
OR2_X1 or2s[lenTree2Count];
]
[lenTree3Count > 0 ->
OR3_X1 or3s[lenTree3Count];
]
(h:lenTree2Count:or2s[h].vdd = supply.vdd;)
(h:lenTree3Count:or3s[h].vdd = supply.vdd;)
(h:lenTree2Count:or2s[h].vss = supply.vss;)
(h:lenTree3Count:or3s[h].vss = supply.vss;)
/* Reset the variables we just stole lol */
i = 0;
end = N-1;
j = 0;
pint tree2Index = 0;
pint tree3Index = 0;
/* Invariant: i <= end */
*[ i != end ->
/*
* Invariant: tmp[i..end] has the current signals that need to be
* combined together, and "isinv" specifies if they are the inverted
* sense or not
*/
j = 0;
*[ i < end ->
/*-- there are still signals that need to be combined --*/
j = j + 1;
[ i+1 >= end ->
/*-- last piece: use either a 2 input C-element --*/
or2s[tree2Index].a = tmp[i];
or2s[tree2Index].b = tmp[i+1];
or2s[tree2Index].y = tmp[end+j];
tree2Index = tree2Index +1;
i = end;
[] i+2 >= end ->
/*-- last piece: use either a 3 input C-element --*/
or3s[tree3Index].a = tmp[i];
or3s[tree3Index].b = tmp[i+1];
or3s[tree3Index].c = tmp[i+2];
or3s[tree3Index].y = tmp[end+j];
tree3Index = tree3Index +1;
i = end;
[] else ->
/*-- more to come; so use a two input C-element --*/
or2s[tree2Index].a = tmp[i];
or2s[tree2Index].b = tmp[i+1];
or2s[tree2Index].y = tmp[end+j];
tree2Index = tree2Index +1;
i = i + 2;
]
]
/*-- update range that has to be combined --*/
i = end+1;
end = end+j;
j = 0;
]
out = tmp[end];
]
}
export template<pint N>
defproc andtree (bool? in[N]; bool! out; power supply)
{
bool tout;
{ N > 0 : "What?" };
[N = 1 -> BUF_X1 b(.vss=supply.vss, .vdd = supply.vdd, .a = in[0], .y = out);
[] N > 1 ->
pint i, end, j;
i = 0;
end = N-1;
pint lenTree2Count, lenTree3Count;
lenTree2Count = 0;
lenTree3Count = 0;
/* Pre"calculate" the number of C cells required, look below if confused */
*[ i != end ->
j = 0;
*[ i < end ->
j = j + 1;
[ i+1 >= end ->
i = end;
lenTree2Count = lenTree2Count +1;
[] i+2 >= end ->
i = end;
lenTree3Count = lenTree3Count +1;
[] else ->
i = i + 2;
lenTree2Count = lenTree2Count +1;
]
]
/*-- update range that has to be combined --*/
i = end+1;
end = end+j;
j = 0;
]
/* array that holds ALL the nodes in the completion tree */
bool tmp[end+1];
(k:N:tmp[k] = in[k];)
/* array to hold the actual C-elments, either A2C or A3C */
[lenTree2Count > 0 ->
AND2_X1 and2s[lenTree2Count];
]
[lenTree3Count > 0 ->
AND3_X1 and3s[lenTree3Count];
]
(h:lenTree2Count:and2s[h].vdd = supply.vdd;)
(h:lenTree3Count:and3s[h].vdd = supply.vdd;)
(h:lenTree2Count:and2s[h].vss = supply.vss;)
(h:lenTree3Count:and3s[h].vss = supply.vss;)
/* Reset the variables we just stole lol */
i = 0;
end = N-1;
j = 0;
pint tree2Index = 0;
pint tree3Index = 0;
/* Invariant: i <= end */
*[ i != end ->
/*
* Invariant: tmp[i..end] has the current signals that need to be
* combined together, and "isinv" specifies if they are the inverted
* sense or not
*/
j = 0;
*[ i < end ->
/*-- there are still signals that need to be combined --*/
j = j + 1;
[ i+1 >= end ->
/*-- last piece: use either a 2 input C-element --*/
and2s[tree2Index].a = tmp[i];
and2s[tree2Index].b = tmp[i+1];
and2s[tree2Index].y = tmp[end+j];
tree2Index = tree2Index +1;
i = end;
[] i+2 >= end ->
/*-- last piece: use either a 3 input C-element --*/
and3s[tree3Index].a = tmp[i];
and3s[tree3Index].b = tmp[i+1];
and3s[tree3Index].c = tmp[i+2];
and3s[tree3Index].y = tmp[end+j];
tree3Index = tree3Index +1;
i = end;
[] else ->
/*-- more to come; so use a two input C-element --*/
and2s[tree2Index].a = tmp[i];
and2s[tree2Index].b = tmp[i+1];
and2s[tree2Index].y = tmp[end+j];
tree2Index = tree2Index +1;
i = i + 2;
]
]
/*-- update range that has to be combined --*/
i = end+1;
end = end+j;
j = 0;
]
out = tmp[end];
]
}
/*
* Build a completion tree using a combination of 2-input and 3-input
* C-elements
*/
export template<pint N>
defproc ctree (bool? in[N]; bool! out; power supply)
{
bool tout;
{ N > 0 : "What?" };
bool meaningless_var;
[N = 1 -> BUF_X1 b(.vss=supply.vss, .vdd = supply.vdd, .a = in[0], .y = out);
[] N > 1 ->
pint i, end, j;
i = 0;
end = N-1;
pint lenTree2Count, lenTree3Count;
lenTree2Count = 0;
lenTree3Count = 0;
/* Pre"calculate" the number of C cells required, look below if confused */
*[ i != end ->
j = 0;
*[ i < end ->
j = j + 1;
[ i+1 >= end ->
i = end;
lenTree2Count = lenTree2Count +1;
[] i+2 >= end ->
i = end;
lenTree3Count = lenTree3Count +1;
[] else ->
i = i + 2;
lenTree2Count = lenTree2Count +1;
]
]
/*-- update range that has to be combined --*/
i = end+1;
end = end+j;
]
/* array that holds ALL the nodes in the completion tree */
bool tmp[end+1];
// Connecting the first nodes to the input
(l:N:
tmp[l] = in[l];
)
/* array to hold the actual C-elments, either A2C or A3C */
[lenTree2Count > 0 ->
A_2C_B_X1 C2Els[lenTree2Count];
]
[lenTree3Count > 0 ->
A_3C_B_X1 C3Els[lenTree3Count];
]
(h:lenTree2Count:C2Els[h].vdd = supply.vdd;)
(h:lenTree3Count:C3Els[h].vdd = supply.vdd;)
(h:lenTree2Count:C2Els[h].vss = supply.vss;)
(h:lenTree3Count:C3Els[h].vss = supply.vss;)
/* Reset the variables we just stole lol */
i = 0;
end = N-1;
j = 0;
pint tree2Index = 0;
pint tree3Index = 0;
/* Invariant: i <= end */
*[ i != end ->
/*
* Invariant: tmp[i..end] has the current signals that need to be
* combined together, and "isinv" specifies if they are the inverted
* sense or not
*/
j = 0;
*[ i < end ->
/*-- there are still signals that need to be combined --*/
j = j + 1;
[ i+1 >= end ->
/*-- last piece: use either a 2 input C-element --*/
C2Els[tree2Index].c1 = tmp[i];
C2Els[tree2Index].c2 = tmp[i+1];
C2Els[tree2Index].y = tmp[end+j];
tree2Index = tree2Index +1;
i = end;
[] i+2 >= end ->
/*-- last piece: use either a 3 input C-element --*/
C3Els[tree3Index].c1 = tmp[i];
C3Els[tree3Index].c2 = tmp[i+1];
C3Els[tree3Index].c3 = tmp[i+2];
C3Els[tree3Index].y = tmp[end+j];
tree3Index = tree3Index +1;
i = end;
[] else ->
/*-- more to come; so use a two input C-element --*/
C2Els[tree2Index].c1 = tmp[i];
C2Els[tree2Index].c2 = tmp[i+1];
C2Els[tree2Index].y = tmp[end+j];
tree2Index = tree2Index +1;
i = i + 2;
]
]
/*-- update range that has to be combined --*/
i = end+1;
end = end+j;
j = 0;
]
out = tmp[end];
]
}
export template<pint N>
defproc vtree (std::data::Mx1of2?<N> in; bool! out; power supply)
{
// OR layer for making OR between true and false of in (they are then sent to Ctree)
OR2_X1 OR2_tf[N];
ctree<N> ct;
(l:N:
OR2_tf[l].a = in.d[l].t;
OR2_tf[l].b = in.d[l].f;
OR2_tf[l].y = ct.in[l];
OR2_tf[l].vdd = supply.vdd;
OR2_tf[l].vss = supply.vss;
)
ct.supply = supply;
out = ct.out;
}
export template<pint N>
defproc sigbuf (bool? in; bool! out[N]; power supply)
{
{ N >= 0 : "sigbuf: parameter error" };
// { N <= 43 : "sigbuf: parameter error, N too big" };
/* -- just use in sized driver here -- */
[ N <= 4 ->
BUF_X1 buf1 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
[] N >= 5 & N <= 7 ->
BUF_X2 buf2 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
[] N >= 8 & N <= 10 ->
BUF_X3 buf3 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
[] N >= 11 & N <= 14 ->
BUF_X4 buf4 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
[] N >= 15 & N <= 18 ->
BUF_X6 buf6 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
[] N >= 19 & N <= 29 ->
BUF_X8 buf8 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
[] N >= 30 & N<= 48->
BUF_X12 buf12 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
[] N >= 49 & N <= 64 ->
BUF_X16 buf16 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
[] N >= 65 & N <= 96 ->
BUF_X24 buf24 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
[] N >= 97 ->
BUF_X32 buf32 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
// [] N >= 129 & N <=192 ->
// BUF_X48 buf48 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
// [] N >= 193 & N <= 256->
// BUF_X64 buf64 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
]
(i:1..N-1:out[i]=out[0];)
}
}}

280
test/prsim_plot.py
View File

@@ -1,280 +0,0 @@
#!/usr/bin/env python3
import sys
import glob
import re
import matplotlib.pyplot as plt
import numpy as np
def main(argv):
# Load file
assert len(argv) >= 2, "No arguments given. -h for help"
if argv[1] == "-h":
print("""Specify the path to prsim.out either by giving the full path,
or the folder name like 'buf_15'.
Use -include='regex' to specify signals to include (or -in).
Use -exclude='regex' to specify signals to exclude (or -ex).""")
return
file_path = argv[1]
if not ".out" in file_path:
file_path = f"./unit_tests/{file_path}/run/prsim.out"
assert len(glob.glob(file_path)) >= 1, "prsim.out file not found!"
print(f"Loading {file_path}")
f = open(file_path,'r').read()
# Start regexxing
entries = re.findall(r"\t *(\d+) ([^:]+) : (\d)( \[by.+\])?[\n\r]", f)
assert len(entries) >= 1, "Could not find signal info in prsim.out!"
# Check if user gave a colour specification
# default is Michele's atm
colour_undefined = (100,100,100)
colour_high = (98, 187, 93)
colour_low = (233, 115, 115)
for arg in argv:
r = re.findall(r'-c=[\"\']?(.+)[\"\']?', arg)
if len(r) >= 1:
if r[0] == "ole":
colour_undefined = (233, 115, 115)
colour_high = (98, 187, 93)
colour_low = (90, 111, 199)
elif r[0] == "og":
colour_undefined = (255,0,0)
colour_high = (252, 186, 3)
colour_low = (20, 184, 186)
elif r[0] == "michele":
colour_undefined = (100,100,100)
colour_high = (98, 187, 93)
colour_low = (233, 115, 115)
else:
raise Exception("Unknown colour given. I cba to code up general colours atm.")
# Check if start time given
t0 = None
for arg in argv:
r = re.findall(r'-t0=(\d+)', arg)
if len(r) >= 1:
print(f"Filtering by start time t0 = {r[0]}")
t0 = int[r[0]]
entries = [e for e in entries if int(e[0]) >= int(r[0])]
# Check if end time given
t1 = None
for arg in argv:
r = re.findall(r'-t1=(\d+)', arg)
if len(r) >= 1:
print(f"Filtering by end time t1 = {r[0]}")
t1 = int[r[0]]
entries = [e for e in entries if int(e[0]) <= int(r[0])]
# Check if user gave an include filter
include_given = False
include_re = None
for arg in argv:
r = re.findall(r'(-include|-in)=(.+)', arg)
if len(r) >= 1:
include_given = True
include_re = r[0][1]
# Check if user gave an exclude filter
exclude_given = False
exclude_re = None
for arg in argv:
r = re.findall(r'(-exclude|-ex)=(.+)', arg)
if len(r) >= 1:
exclude_given = True
exclude_re = r[0][1]
# Check if user gave "keep all times" flag
# This is so you can look at certain signals only
# without them all bunching up.
include_all_times = False
for arg in argv:
r = re.findall(r'(-alltimes?)', arg)
if len(r) >= 1:
include_all_times = True
# Check if user gave "nowarn" flag
plot_warn = True
for arg in argv:
r = re.findall(r'(-nowarn?)', arg)
if len(r) >= 1:
plot_warn = False
# Get list of all times (before filtering)
unique_times = np.unique([int(e[0]) for e in entries])
# assert not (exclude_given and include_given), "Can't give include and exclude re simultaneously."
if include_given: print(f"Including signals that match regex {include_re}")
if exclude_given: print(f"Excluding signals that match regex {exclude_re}")
if include_given:
entries = [e for e in entries if not re.search(include_re, e[1]) == None]
if exclude_given:
entries = [e for e in entries if re.search(exclude_re, e[1]) == None]
assert len(entries) >= 1, "No valid entries in prsim.out!"
num_times = unique_times.shape[0]
# Get list of all times (after filtering)
times = np.array([int(e[0]) for e in entries])
if not include_all_times: unique_times = np.unique(times)
num_times = unique_times.shape[0]
# Get list of all sigs
sigs = np.array([e[1] for e in entries])
unique_sigs = np.unique(sigs)
num_sigs = unique_sigs.shape[0]
print(f"Plotting signals:")
print(unique_sigs)
# Some functions to order everything nicely
# Should probably put these outside but whatever.
def time_to_index(time):
'''
Since times are random, need to convert them to an index.
'''
if not (int(time) in unique_times): return None
out = np.argwhere(unique_times == int(time))
return out[0][0]
def sig_to_index(sig):
'''
Handles signal name ordering.
Assume ordered like unique_sigs for now
'''
if not (sig in unique_sigs): return None
out = np.argwhere(unique_sigs == sig)
return out[0][0]
# Create matrix of signals over time and populate
signals_matrix = np.zeros((num_sigs, num_times), dtype = int)
for sig in unique_sigs:
entries_filtered = [e for e in entries if e[1] == sig]
# make sure sorted
entries_filtered = sorted(entries_filtered, key = lambda e: int(e[0]))
for e in entries_filtered:
val = int(e[2])
val = 2*val -1
signals_matrix[sig_to_index(sig),time_to_index(e[0]):] = val
# Plot
# Generate figure
# weird sizing is to try to keep "pixel" sizes approx const
fig = plt.figure(figsize = (num_times/3+0.2,num_sigs/3+0.2), dpi = 100)
image = np.zeros((num_sigs, num_times, 3), dtype = int)
image[signals_matrix == 0] = colour_undefined
image[signals_matrix == 1] = colour_high
image[signals_matrix == -1] = colour_low
plt.imshow(image)
ax = fig.gca()
ax.set_xlabel("Time")
# ax.set_ylabel("Signal")
ax.set_yticks([])
# Plot signal names
sig_repeat_period = 20
for sig in unique_sigs:
ax.text(-1, sig_to_index(sig), sig, ha = "right", va = "center", size = 10)
ax.text(num_times, sig_to_index(sig), sig, ha = "left", va = "center", size = 10)
for i in range(num_sigs-1):
ax.axhline(i+0.5, c = "white", lw = 2)
for i in range(num_times-1):
ax.axvline(i+0.5, c = "white", lw = 2)
ax.axis("off")
# Draw arrows
for e in entries:
# check if has a causal signal
by = re.findall(r"\[by (.+):=(\d)",e[3])
if len(by) == 0: continue
sig = e[1]
time = e[0]
t_index = time_to_index(time)
by_sig = by[0][0]
by_val = int(by[0][1])
t0,t1 = (t_index, t_index)
# The sig that caused the change might have been excluded from plotting
s0 = sig_to_index(sig)
if by_sig in unique_sigs:
s1 = sig_to_index(by_sig)
else:
s1 = s0
if by_val == 1:
plt.arrow(t0, s1, 0, s0-s1 + 0.2*np.sign(s0-s1), head_width = 0.5, width = 0.2,
ec = "none", lw = 0, fc = "black", length_includes_head = True)
else:
plt.arrow(t0, s1, 0, s0-s1 + 0.2*np.sign(s0-s1), head_width = 0, width = 0.2,
ec = "none", lw = 0, fc = "black", length_includes_head = True)
plt.scatter((t0),(s0), c = "black", s = 40)
# Write times on x axis
for time in unique_times:
ax.text(time_to_index(time), num_sigs, time, ha = "center", va = "top", size = 10, rotation = 90)
# Find and plot wrong Assert statements
asserts = re.findall(r"\t *(\d+) .*\n(WRONG ASSERT|WARNING):\t?(.+)", f)
if len(asserts): print("Warnings found!")
for a in asserts:
print(a)
time = int(a[0])
if not time in unique_times:
try:
time = unique_times[np.argwhere((unique_times-time) < 0)[-1]]
except:
print(f"Couldn't find an appropriate time for warning {a}")
continue
index = time_to_index(time)
if plot_warn:
ax.axvline(index+0.5, c = "red", lw = 2)
ax.text(index+0.5, -1, a[2], rotation = 90, ha = "center", va = "bottom", c = "red")
# Find echoed statements of the form "[digits] text"
echoes = re.findall(r"\t *(\d+) [^\t]*\n(\[\d*\].+)", f)
for a in echoes:
time = int(a[0])
if not time in unique_times:
try:
time = unique_times[np.argwhere((unique_times-time) < 0)[-1]]
except:
print(f"Couldn't find an appropriate time for echo {a}")
continue
index = time_to_index(time)
c = "xkcd:bright purple"
ax.axvline(index+0.5, c = c, lw = 2)
ax.text(index+0.5, -1, a[1], rotation = 90, ha = "center", va = "bottom", c = c)
output_type = ".pdf"
for arg in argv:
if arg == "-png": output_type = ".png"
file_out_path = file_path.replace(".out",output_type)
plt.savefig(file_out_path, bbox_inches = "tight")
if __name__ == "__main__":
# print(sys.argv[0:])
main(sys.argv)
# main(sys.argv[1:])

155
test/repeat_unit.sh
View File

@@ -1,94 +1,85 @@
#!/bin/sh
# repeatedly run prsim on one unit_test's PRs
fail=0
faildirs=""
proc=""
bold=$(tput bold)
normal=$(tput sgr0)
und=$(tput smul)
i=${unit}
proc="$i<>"
faildirs=""
failed=0
iteration=0
numberofruns=100
#
# run_test name [option]
#
run_test () {
echo "Testing ${bold}$1 ${normal} for $2 random delay runs"
# clear run directory
if [ -d $1/run ]; then
rm -rf $1/run
fi
mkdir $1/run
cp init.prs $1/run/test.prs
if aflat -ref=1 $1/test.act >> $1/run/test.prs; then
echo "random_seed $2" > $1/run/prsim.in
cat init_qdi.prsim $1/test.prsim >> $1/run/prsim.in
cat $1/run/prsim.in | prsim -r $1/run/test.prs > $1/run/prsim.out
if egrep '(WRONG|WARNING|Node)' $1/run/prsim.out >/dev/null; then
echo "${bold}*** simulation failed seed: $2 ***${normal}"
faildirs="${faildirs} ${1}-sim($2)"
failed=1
echo
fi
else
echo "${bold}*** circuit construction failed ***${normal}"
faildirs="${faildirs} ${1}-ckt"
failed=1
echo
fi
}
if [ ! $(command -v aflat) ]; then #&& ! command -v prsim ]; then
echo "${bold}Error:${bold} aflat & prsim necessary for tests."
exit 1
fi
if [ ! -d "unit_tests" ];
then
echo "${bold}Error:${bold} no unit_tests directory."
exit 1
fi
echo ""
echo "${bold}******************************************"
echo "* ${i} repetitions , show warnings=${warning}*"
echo "******************************************${normal}"
cd "unit_tests"
echo "${bold}... checking aflat${normal}"
# run all test except single one is specified
if [ ! -z $3 ]; then
iteration=$3
fi
if [ ! -z $2 ]; then
numberofruns=$2
fi
# check aflat
if ($ACT_HOME/bin/aflat "$i/test_final.act" > "$i/test.prs");
then
echo "${bold}... aflat complete, checking in prsim${normal}"
if [ -z $1 ]; then
for i in *
do
if [ -d $i -a -f $i/test.act ]; then
while [ $iteration -lt $numberofruns ]
do
run_test $iteration
iteration=$iteration+1
done
# run prsim on prs
(($ACT_HOME/bin/prsim "$i/test.prs" < "$i/test.prsim") > "$i/prsim.out");
if (cat "$i/prsim.out" | grep -e "WRONG ASSERT" -e "FATAL" -e "not found")
then
echo "FAILED in first prsim"
else
# show warnings setting
if [ "${warning}" = "1" ];
then
echo "${bold}Exit on prsim warnings turned ON${normal}"
else
echo "${bold}Exit on prsim warnings turned OFF${normal}"
fi
done
echo ""
# begin prsim test loop
has_failed=0
iter=0
echo "${bold}using random_seed${normal}"
echo "\nusing random_seed" >> "$i/prsim.out"
while [ has_failed=0 ]
do
# write prsim test file with random seed appended to top of file
(echo "random_seed $iter \nrandom" > "$i/test_rand.prsim");
(cat "$i/test.prsim" >> "$i/test_rand.prsim");
(echo "\nTEST $iter\n" >> "$i/prsim.out");
# validate prsim output
if (($ACT_HOME/bin/prsim "$i/test.prs" < "$i/test_rand.prsim") >> "$i/prsim.out");
then
if [ "${warning}" = "1" ];
then
if (cat "$i/prsim.out" | grep -e "WRONG ASSERT" -e "FATAL" -e "not found" -e "WARNING:");
then
echo "${bold}==> test #${iter} ${und}FAILED in prsim${normal}"
has_failed=1
exit 0
else
echo "==> passed test #${iter}"
iter=$(($iter + 1))
fi
else
if (cat "$i/prsim.out" | grep -e "WRONG ASSERT" -e "FATAL" -e "not found");
then
echo "${bold}==> test #${iter} ${und}FAILED in prsim${normal}"
has_failed=1
exit 0
else
echo "==> passed test #${iter}"
iter=$(($iter + 1))
fi
fi
else
has_failed=1
exit 0
fi
done
(cd ".."; pwd);
exit 1
fi
else
while [ $iteration -lt $numberofruns ]
do
run_test $1 $iteration
iteration=$((iteration+1))
done
echo "FAILED in aflat conversion"
fi
if [ $failed -eq 1 ]; then
echo ""
echo "${bold}*********************************"
echo "* FAILED DIRECTORIES:${normal}$faildirs ${bold}*"
echo "*********************************${normal}"
fi
exit $failed

6
test/run.sh
View File

@@ -22,8 +22,7 @@ run_test () {
mkdir $1/run
cp init.prs $1/run/test.prs
if aflat -ref=1 $1/test.act >> $1/run/test.prs; then
cat init_qdi.prsim $1/test.prsim > $1/run/prsim.in
cat $1/run/prsim.in | prsim -r $1/run/test.prs > $1/run/prsim.out
cat init_qdi.prsim $1/test.prsim | prsim -r $1/run/test.prs > $1/run/prsim.out
if egrep '(WRONG|WARNING|Node)' $1/run/prsim.out >/dev/null; then
echo "${bold}*** simulation failed ***${normal}"
faildirs="${faildirs} ${1}-sim"
@@ -38,7 +37,8 @@ run_test () {
fi
}
if [ ! $(command -v aflat) ]; then #&& ! command -v prsim ]; then
if [ ! ( command -v aflat && command -v prsim ) ];
then
echo "${bold}Error:${bold} aflat & prsim necessary for tests."
exit 1
fi

BIN
test/unit_tests/.DS_Store vendored
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41
test/unit_tests/andtree_15/test.act
View File

@@ -1,41 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/treegates.act";
import globals;
open tmpl::dataflow_neuro;
defproc andtree_15 (bool? in[15]; bool! out){
andtree<15> at(.in=in, .out=out);
at.supply.vss = GND;
at.supply.vdd = Vdd;
}
andtree_15 t;

110
test/unit_tests/andtree_15/test.prsim
View File

@@ -1,110 +0,0 @@
watchall
system "echo '0'"
set t.in[0] 0
set t.in[1] 0
set t.in[2] 0
set t.in[3] 0
set t.in[4] 0
set t.in[5] 0
set t.in[6] 0
set t.in[7] 0
set t.in[8] 0
set t.in[9] 0
set t.in[10] 0
set t.in[11] 0
set t.in[12] 0
set t.in[13] 0
set t.in[14] 0
system "echo '1'"
cycle
mode run
assert t.out 0
system "echo '[] setting some bits high'"
set t.in[0] 1
set t.in[1] 1
set t.in[2] 1
set t.in[3] 1
set t.in[4] 1
set t.in[5] 1
set t.in[6] 1
set t.in[7] 1
set t.in[8] 1
set t.in[9] 1
set t.in[10] 1
set t.in[11] 1
set t.in[12] 0
set t.in[13] 0
set t.in[14] 0
cycle
assert t.out 0
system "echo '[] setting all bits high'"
set t.in[0] 1
set t.in[1] 1
set t.in[2] 1
set t.in[3] 1
set t.in[4] 1
set t.in[5] 1
set t.in[6] 1
set t.in[7] 1
set t.in[8] 1
set t.in[9] 1
set t.in[10] 1
set t.in[11] 1
set t.in[12] 1
set t.in[13] 1
set t.in[14] 1
cycle
assert t.out 1
system "echo '[] setting some low'"
set t.in[0] 1
set t.in[1] 1
set t.in[2] 1
set t.in[3] 1
set t.in[4] 1
set t.in[5] 1
set t.in[6] 1
set t.in[7] 1
set t.in[8] 1
set t.in[9] 1
set t.in[10] 0
set t.in[11] 1
set t.in[12] 1
set t.in[13] 1
set t.in[14] 1
cycle
assert t.out 0
system "echo '[] setting all low'"
set t.in[0] 0
set t.in[1] 0
set t.in[2] 0
set t.in[3] 0
set t.in[4] 0
set t.in[5] 0
set t.in[6] 0
set t.in[7] 0
set t.in[8] 0
set t.in[9] 0
set t.in[10] 0
set t.in[11] 0
set t.in[12] 0
set t.in[13] 0
set t.in[14] 0
cycle
assert t.out 0

41
test/unit_tests/andtree_5/test.act
View File

@@ -1,41 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/treegates.act";
import globals;
open tmpl::dataflow_neuro;
defproc andtree_5 (bool? in[5]; bool! out){
andtree<5> at(.in=in, .out=out);
at.supply.vss = GND;
at.supply.vdd = Vdd;
}
andtree_5 t;

50
test/unit_tests/andtree_5/test.prsim
View File

@@ -1,50 +0,0 @@
watchall
system "echo '0'"
set t.in[0] 0
set t.in[1] 0
set t.in[2] 0
set t.in[3] 0
set t.in[4] 0
system "echo '1'"
cycle
mode run
assert t.out 0
system "echo '[] setting some bits high'"
set t.in[0] 1
set t.in[1] 1
set t.in[2] 1
cycle
assert t.out 0
system "echo '[] setting all bits high'"
set t.in[3] 1
set t.in[4] 1
cycle
assert t.out 1
system "echo '[] setting some low'"
set t.in[0] 0
set t.in[1] 0
cycle
assert t.out 0
system "echo '[] setting all low'"
set t.in[2] 0
set t.in[3] 0
set t.in[4] 0
cycle
assert t.out 0

53
test/unit_tests/append_5_3_2/test.act
View File

@@ -1,53 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc append_5_3_2(avMx1of2<5> in; avMx1of2<8> out)
{
bool _reset_B;
prs {
Reset => _reset_B-
}
fifo<5,4> fifo_pre(.in = in, .reset_B = _reset_B);
append<5,3,3> app(.in = fifo_pre.out);
fifo<5+3,4> fifo_post(.in = app.out, .out = out, .reset_B = _reset_B);
app.supply.vdd = Vdd;
app.supply.vss = GND;
fifo_pre.supply.vdd = Vdd;
fifo_pre.supply.vss = GND;
fifo_post.supply.vdd = Vdd;
fifo_post.supply.vss = GND;
}
append_5_3_2 b;

78
test/unit_tests/append_5_3_2/test.prsim
View File

@@ -1,78 +0,0 @@
watchall
set b.out.a 0
set b.out.v 0
set Reset 0
set-qdi-channel-neutral "b.in" 5
cycle
system "echo '[] set Reset 1'"
set Reset 1
cycle
system "echo '[] set Reset 0'"
set Reset 0
mode run
cycle
status X
assert-qdi-channel-neutral "b.out" 8
assert b.in.a 0
assert b.in.v 0
system "echo '[] sending in a 31'"
set-qdi-channel-valid "b.in" 5 31
cycle
assert-qdi-channel-valid "b.out" 8 127
assert b.in.a 1
assert b.in.v 1
system "echo '[] removing input'"
set-qdi-channel-neutral "b.in" 5
cycle
assert b.in.a 0
assert b.in.v 0
system "echo '[] sending in a 0'"
set-qdi-channel-valid "b.in" 5 0
cycle
# assert-qdi-channel-valid "b.out" 8 96
assert b.in.a 1
assert b.in.v 1
system "echo '[] removing input'"
set-qdi-channel-neutral "b.in" 5
cycle
assert b.in.a 0
assert b.in.v 0
system "echo '[] receiving out ack/val'"
set b.out.a 1
set b.out.v 1
cycle
assert-qdi-channel-neutral "b.out" 8
system "echo '[] removing out ack/val'"
set b.out.a 0
set b.out.v 0
cycle
assert-qdi-channel-valid "b.out" 8 96
system "echo '[] receiving out ack/val'"
set b.out.a 1
set b.out.v 1
cycle
assert-qdi-channel-neutral "b.out" 8
system "echo '[] removing out ack/val'"
set b.out.a 0
set b.out.v 0
cycle
assert-qdi-channel-neutral "b.out" 8

18
test/unit_tests/arbiter/test.act
View File

@@ -1,18 +0,0 @@
defproc arbiter (bool a, b, u, v)
{
bool _u, _v;
prs {
[keeper=0] a & _v -> _u-
[keeper=0] ~a | ~_v -> _u+
[keeper=0] b & _u -> _v-
[keeper=0] ~b | ~_u -> _v+
[keeper=0] _u => u-
[keeper=0] _v => v-
}
spec {
mk_excllo(_u, _v)
}
}
arbiter a;

39
test/unit_tests/arbiter/test.prsim
View File

@@ -1,39 +0,0 @@
watchall
cycle
system "echo 'reset done'"
set a.a 0
set a.b 0
advance 1000000
status X
mode run
system "echo 'step 1.1 finished'"
set a.a 1
set a.b 1
advance 1000000
status X
mode run
system "echo 'step 1.2 finished'"
set a.a 0
set a.b 0
advance 1000000
status X
mode run
system "echo 'step 2.1 finished'"
set a.a 1
set a.b 1
advance 1000000
status X
mode run
system "echo 'step 2.2 finished'"
set a.a 0
set a.b 0
advance 1000000
status X
mode run
system "echo 'step 3.1 finished'"
set a.a 0
set a.b 1
advance 1000000
status X
mode run
system "echo 'step 3.2 finished'"

18
test/unit_tests/arbiter_2/test.act
View File

@@ -1,18 +0,0 @@
defproc arbiter (bool a, b, u, v)
{
bool _u, _v;
prs {
[keeper=0] a & _v -> _u-
[keeper=0] ~a | ~_v -> _u+
[keeper=0] b & _u -> _v-
[keeper=0] ~b | ~_u -> _v+
[keeper=0] _u => u-
[keeper=0] _v => v-
}
spec {
mk_excllo(_u, _v)
}
}
arbiter a;

39
test/unit_tests/arbiter_2/test.prsim
View File

@@ -1,39 +0,0 @@
watchall
cycle
system "echo 'reset done'"
set a.a 0
set a.b 0
advance 1000000
status X
mode run
system "echo 'step 1.1 finished'"
set a.a 1
set a.b 1
advance 1000000
status X
mode run
system "echo 'step 1.2 finished'"
set a.a 0
set a.b 0
advance 1000000
status X
mode run
system "echo 'step 2.1 finished'"
set a.a 1
set a.b 1
advance 1000000
status X
mode run
system "echo 'step 2.2 finished'"
set a.a 0
set a.b 0
advance 1000000
status X
mode run
system "echo 'step 3.1 finished'"
set a.a 0
set a.b 1
advance 1000000
status X
mode run
system "echo 'step 3.2 finished'"

52
test/unit_tests/arbiter_handshake_adv/test.act
View File

@@ -1,52 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc arbiter_test(a1of1 in1; a1of1 in2; a1of1 out)
{
a1of1 _out1,_out2;
fifo_t<4> fifo_in1(.in = in1,.out = _out1);
fifo_t<4> fifo_in2(.in = in2,.out = _out2);
fifo_in1.supply.vdd = Vdd;
fifo_in1.supply.vss = GND;
fifo_in1.reset_B = Reset;
fifo_in2.supply.vdd = Vdd;
fifo_in2.supply.vss = GND;
fifo_in2.reset_B = Reset;
arbiter_handshake arb(.in1 = _out1, .in2 = _out2, .out = out);
arb.supply.vdd = Vdd;
arb.supply.vss = GND;
}
arbiter_test t;

45
test/unit_tests/arbiter_handshake_adv/test.prsim
View File

@@ -1,45 +0,0 @@
watchall
system "echo '[0] code starts'"
set t.in1.r 0
set t.in2.r 0
set t.out.a 0
set Reset 0
cycle
status X
mode run
set Reset 1
cycle
system "echo '[1] reset done'"
system "echo '----------------------------------------------------------------------------------------------------'"
set t.in1.r 1
set t.in2.r 1
cycle
assert t.out.r 1
set t.out.a 1
system "echo '----------------------------------------------------------------------------------------------------'"
system "echo '[2] 1 bit processed by the arbiter'"
cycle
set t.out.a 0
cycle
assert t.out.r 1
set t.out.a 1
set t.in1.r 0
set t.in2.r 0
system "echo '----------------------------------------------------------------------------------------------------'"
system "echo '[3] 2 bit processed by the arbiter'"
cycle
set t.out.a 0
set t.in1.r 1
set t.in2.r 1
cycle
assert t.out.r 1
set t.out.a 1
system "echo '----------------------------------------------------------------------------------------------------'"
system "echo '[4] 3 bit processed by the arbiter'"
cycle
set t.out.a 0
cycle
assert t.out.r 1
set t.out.a 1
system "echo '----------------------------------------------------------------------------------------------------'"
system "echo '[5] 4 bit processed by the arbiter'"

58
test/unit_tests/arbiter_handshake_simple/run/prsim.out
View File

@@ -1,58 +0,0 @@
t.in1.r t.in2.r t.out.r t.a.arbiter._y1 t.a.arbiter._y2 t.out.a t.in1.a t.a._y1_arb t.a._y2_arb t.in2.a t.a.or_cell._y t.a.ack_cell1._y t.a.ack_cell2._y
[0] code starts
0 t.in1.r : 0
0 t.out.a : 0
0 t.in2.r : 0
1 t.a.arbiter._y1 : 1 [by t.in1.r:=0]
7092 t.a.arbiter._y2 : 1 [by t.in2.r:=0]
7094 t.a._y2_arb : 0 [by t.a.arbiter._y2:=1]
10468 t.a._y1_arb : 0 [by t.a.arbiter._y1:=1]
10582 t.a.or_cell._y : 1 [by t.a._y1_arb:=0]
11605 t.a.ack_cell1._y : 1 [by t.a._y1_arb:=0]
11847 t.a.ack_cell2._y : 1 [by t.a._y2_arb:=0]
11886 t.in2.a : 0 [by t.a.ack_cell2._y:=1]
13331 t.in1.a : 0 [by t.a.ack_cell1._y:=1]
75948 t.out.r : 0 [by t.a.or_cell._y:=1]
[1] reset done
----------------------------------------------------------------------------------------------------
75948 t.in1.r : 1
75963 t.a.arbiter._y1 : 0 [by t.in1.r:=1]
76454 t.a._y1_arb : 1 [by t.a.arbiter._y1:=0]
76467 t.a.or_cell._y : 0 [by t.a._y1_arb:=1]
76507 t.out.r : 1 [by t.a.or_cell._y:=0]
76507 t.out.a : 1
76922 t.a.ack_cell1._y : 0 [by t.out.a:=1]
76942 t.in1.a : 1 [by t.a.ack_cell1._y:=0]
[2] test in1 done
----------------------------------------------------------------------------------------------------
76942 t.in1.r : 0
83003 t.a.arbiter._y1 : 1 [by t.in1.r:=0]
83050 t.a._y1_arb : 0 [by t.a.arbiter._y1:=1]
83066 t.a.or_cell._y : 1 [by t.a._y1_arb:=0]
127164 t.out.r : 0 [by t.a.or_cell._y:=1]
127164 t.out.a : 0
140888 t.a.ack_cell1._y : 1 [by t.out.a:=0]
140892 t.in1.a : 0 [by t.a.ack_cell1._y:=1]
[3] reset done
----------------------------------------------------------------------------------------------------
140892 t.in2.r : 1
150021 t.a.arbiter._y2 : 0 [by t.in2.r:=1]
150036 t.a._y2_arb : 1 [by t.a.arbiter._y2:=0]
193284 t.a.or_cell._y : 0 [by t.a._y2_arb:=1]
230215 t.out.r : 1 [by t.a.or_cell._y:=0]
230215 t.out.a : 1
230270 t.a.ack_cell2._y : 0 [by t.out.a:=1]
281923 t.in2.a : 1 [by t.a.ack_cell2._y:=0]
[4] test in2 done
----------------------------------------------------------------------------------------------------
281923 t.in2.r : 0
311703 t.a.arbiter._y2 : 1 [by t.in2.r:=0]
325552 t.a._y2_arb : 0 [by t.a.arbiter._y2:=1]
350364 t.a.or_cell._y : 1 [by t.a._y2_arb:=0]
364707 t.out.r : 0 [by t.a.or_cell._y:=1]
364707 t.out.a : 0
365129 t.a.ack_cell2._y : 1 [by t.out.a:=0]
413843 t.in2.a : 0 [by t.a.ack_cell2._y:=1]
[5] reset done
----------------------------------------------------------------------------------------------------

70
test/unit_tests/arbiter_handshake_simple/run/test.prs
View File

@@ -1,70 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
= "t.a.in1.d.d[0]" "t.a.in1.r"
= "t.a.in1.a" "t.a.arbiter.d"
= "t.a.in1.a" "t.a.ack_cell1.y"
= "t.a.in1.d.d[0]" "t.a.arbiter.a"
= "t.a.in1.d.d[0]" "t.a.in1.r"
~"t.a.ack_cell1.c1"&~"t.a.ack_cell1.c2"->"t.a.ack_cell1._y"+
"t.a.ack_cell1.c1"&"t.a.ack_cell1.c2"->"t.a.ack_cell1._y"-
"t.a.ack_cell1._y"->"t.a.ack_cell1.y"-
~("t.a.ack_cell1._y")->"t.a.ack_cell1.y"+
= "t.a.in2.d.d[0]" "t.a.in2.r"
= "t.a.in2.a" "t.a.arbiter.c"
= "t.a.in2.a" "t.a.ack_cell2.y"
= "t.a.in2.d.d[0]" "t.a.arbiter.b"
= "t.a.in2.d.d[0]" "t.a.in2.r"
= "t.a.supply.vdd" "t.a.arbiter.vdd"
= "t.a.supply.vdd" "t.a.or_cell.vdd"
= "t.a.supply.vdd" "t.a.ack_cell2.vdd"
= "t.a.supply.vdd" "t.a.ack_cell1.vdd"
= "t.a.supply.vss" "t.a.arbiter.vss"
= "t.a.supply.vss" "t.a.or_cell.vss"
= "t.a.supply.vss" "t.a.ack_cell2.vss"
= "t.a.supply.vss" "t.a.ack_cell1.vss"
"t.a.arbiter.a"&"t.a.arbiter._y2"->"t.a.arbiter._y1"-
~"t.a.arbiter.a"|~"t.a.arbiter._y2"->"t.a.arbiter._y1"+
"t.a.arbiter.b"&"t.a.arbiter._y1"->"t.a.arbiter._y2"-
~"t.a.arbiter.b"|~"t.a.arbiter._y1"->"t.a.arbiter._y2"+
"t.a.arbiter._y1"|"t.a.arbiter.c"->"t.a.arbiter.y1"-
~("t.a.arbiter._y1"|"t.a.arbiter.c")->"t.a.arbiter.y1"+
"t.a.arbiter._y2"|"t.a.arbiter.d"->"t.a.arbiter.y2"-
~("t.a.arbiter._y2"|"t.a.arbiter.d")->"t.a.arbiter.y2"+
mk_excllo("t.a.arbiter._y1","t.a.arbiter._y2")
= "t.a._y1_arb" "t.a.arbiter.y1"
= "t.a._y1_arb" "t.a.or_cell.a"
= "t.a._y1_arb" "t.a.ack_cell1.c2"
~"t.a.ack_cell2.c1"&~"t.a.ack_cell2.c2"->"t.a.ack_cell2._y"+
"t.a.ack_cell2.c1"&"t.a.ack_cell2.c2"->"t.a.ack_cell2._y"-
"t.a.ack_cell2._y"->"t.a.ack_cell2.y"-
~("t.a.ack_cell2._y")->"t.a.ack_cell2.y"+
"t.a.or_cell.a"|"t.a.or_cell.b"->"t.a.or_cell._y"-
~("t.a.or_cell.a"|"t.a.or_cell.b")->"t.a.or_cell._y"+
"t.a.or_cell._y"->"t.a.or_cell.y"-
~("t.a.or_cell._y")->"t.a.or_cell.y"+
= "t.a.out.d.d[0]" "t.a.out.r"
= "t.a.out.a" "t.a.ack_cell2.c1"
= "t.a.out.a" "t.a.ack_cell1.c1"
= "t.a.out.d.d[0]" "t.a.or_cell.y"
= "t.a.out.d.d[0]" "t.a.out.r"
= "t.a._y2_arb" "t.a.arbiter.y2"
= "t.a._y2_arb" "t.a.or_cell.b"
= "t.a._y2_arb" "t.a.ack_cell2.c2"
= "Vdd" "t.a.supply.vdd"
= "GND" "t.a.supply.vss"
= "t.in1.d.d[0]" "t.in1.r"
= "t.in1.r" "t.a.in1.r"
= "t.in1.a" "t.a.in1.a"
= "t.in1.d.d[0]" "t.a.in1.d.d[0]"
= "t.in1.d.d[0]" "t.in1.r"
= "t.out.d.d[0]" "t.out.r"
= "t.out.r" "t.a.out.r"
= "t.out.a" "t.a.out.a"
= "t.out.d.d[0]" "t.a.out.d.d[0]"
= "t.out.d.d[0]" "t.out.r"
= "t.in2.d.d[0]" "t.in2.r"
= "t.in2.r" "t.a.in2.r"
= "t.in2.a" "t.a.in2.a"
= "t.in2.d.d[0]" "t.a.in2.d.d[0]"
= "t.in2.d.d[0]" "t.in2.r"

41
test/unit_tests/arbiter_handshake_simple/test.act
View File

@@ -1,41 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc arbiter_test(a1of1 in1; a1of1 in2; a1of1 out)
{
arbiter_handshake a(.in1 = in1, .in2 = in2, .out = out);
a.supply.vdd = Vdd;
a.supply.vss = GND;
}
arbiter_test t;

42
test/unit_tests/arbiter_handshake_simple/test.prsim
View File

@@ -1,42 +0,0 @@
watchall
system "echo '[0] code starts'"
set t.in1.r 0
set t.in2.r 0
set t.out.a 0
cycle
status X
mode run
system "echo '[1] reset done'"
system "echo '----------------------------------------------------------------------------------------------------'"
set t.in1.r 1
cycle
assert t.out.r 1
set t.out.a 1
cycle
assert t.in1.a 1
system "echo '[2] test in1 done'"
system "echo '----------------------------------------------------------------------------------------------------'"
set t.in1.r 0
cycle
assert t.out.r 0
set t.out.a 0
cycle
assert t.in1.a 0
system "echo '[3] reset done'"
system "echo '----------------------------------------------------------------------------------------------------'"
set t.in2.r 1
cycle
assert t.out.r 1
set t.out.a 1
cycle
assert t.in2.a 1
system "echo '[4] test in2 done'"
system "echo '----------------------------------------------------------------------------------------------------'"
set t.in2.r 0
cycle
assert t.out.r 0
set t.out.a 0
cycle
assert t.in2.a 0
system "echo '[5] reset done'"
system "echo '----------------------------------------------------------------------------------------------------'"

98
test/unit_tests/arbiter_tree_simple_nosim/run/prsim.out
View File

@@ -1,98 +0,0 @@
my_tree.in[4].r my_tree.at_cell.tmp[6].r my_tree.at_cell.arbs[0].arbiter._y1 my_tree.in[2].a my_tree.at_cell.tmp[8].a my_tree.at_cell.arbs[0]._y1_arb my_tree.out.r my_tree.at_cell.tmp[5].a my_tree.at_cell.arbs[2]._y2_arb my_tree.at_cell.arbs[3].ack_cell1._y my_tree.in[0].a my_tree.at_cell.tmp[6].a my_tree.in[4].a my_tree.at_cell.arbs[2].arbiter._y2 my_tree.in[1].a my_tree.out.a my_tree.at_cell.arbs[0].ack_cell1._y my_tree.in[0].r my_tree.at_cell.arbs[3].ack_cell2._y my_tree.in[3].r my_tree.at_cell.tmp[5].r my_tree.in[1].r my_tree.at_cell.arbs[0]._y2_arb my_tree.at_cell.arbs[2].ack_cell2._y my_tree.at_cell.arbs[1]._y1_arb my_tree.at_cell.arbs[1].ack_cell2._y my_tree.in[2].r my_tree.in[3].a my_tree.at_cell.tmp[8].r my_tree.at_cell.arbs[1]._y2_arb my_tree.at_cell.arbs[3]._y1_arb my_tree.at_cell.arbs[3].or_cell._y my_tree.at_cell.arbs[1].arbiter._y2 my_tree.at_cell.arbs[3].arbiter._y2 my_tree.at_cell.arbs[1].ack_cell1._y my_tree.at_cell.arbs[3].arbiter._y1 my_tree.at_cell.arbs[0].ack_cell2._y my_tree.at_cell.arbs[3]._y2_arb my_tree.at_cell.arbs[2].ack_cell1._y my_tree.at_cell.arbs[1].or_cell._y my_tree.at_cell.arbs[2]._y1_arb my_tree.at_cell.arbs[1].arbiter._y1 my_tree.at_cell.arbs[0].or_cell._y my_tree.at_cell.arbs[0].arbiter._y2 my_tree.at_cell.arbs[2].or_cell._y my_tree.at_cell.arbs[2].arbiter._y1
1 my_tree.in[0].r : 0
1 my_tree.out.a : 0
1 my_tree.in[2].r : 0
1 my_tree.in[4].r : 0
1 my_tree.in[1].r : 0
1 my_tree.in[3].r : 0
3 my_tree.at_cell.arbs[3].arbiter._y2 : 1 [by my_tree.in[4].r:=0]
117 my_tree.at_cell.arbs[3]._y2_arb : 0 [by my_tree.at_cell.arbs[3].arbiter._y2:=1]
1138 my_tree.at_cell.arbs[1].arbiter._y2 : 1 [by my_tree.in[3].r:=0]
2864 my_tree.at_cell.arbs[1]._y2_arb : 0 [by my_tree.at_cell.arbs[1].arbiter._y2:=1]
4754 my_tree.at_cell.arbs[0].arbiter._y2 : 1 [by my_tree.in[1].r:=0]
4793 my_tree.at_cell.arbs[0]._y2_arb : 0 [by my_tree.at_cell.arbs[0].arbiter._y2:=1]
7093 my_tree.at_cell.arbs[0].arbiter._y1 : 1 [by my_tree.in[0].r:=0]
7108 my_tree.at_cell.arbs[0]._y1_arb : 0 [by my_tree.at_cell.arbs[0].arbiter._y1:=1]
7599 my_tree.at_cell.arbs[0].or_cell._y : 1 [by my_tree.at_cell.arbs[0]._y1_arb:=0]
7612 my_tree.at_cell.tmp[5].r : 0 [by my_tree.at_cell.arbs[0].or_cell._y:=1]
7652 my_tree.at_cell.arbs[2].arbiter._y1 : 1 [by my_tree.at_cell.tmp[5].r:=0]
8067 my_tree.at_cell.arbs[2]._y1_arb : 0 [by my_tree.at_cell.arbs[2].arbiter._y1:=1]
10468 my_tree.at_cell.arbs[1].arbiter._y1 : 1 [by my_tree.in[2].r:=0]
10488 my_tree.at_cell.arbs[1]._y1_arb : 0 [by my_tree.at_cell.arbs[1].arbiter._y1:=1]
16549 my_tree.at_cell.arbs[1].or_cell._y : 1 [by my_tree.at_cell.arbs[1]._y1_arb:=0]
16596 my_tree.at_cell.tmp[6].r : 0 [by my_tree.at_cell.arbs[1].or_cell._y:=1]
16612 my_tree.at_cell.arbs[2].arbiter._y2 : 1 [by my_tree.at_cell.tmp[6].r:=0]
60710 my_tree.at_cell.arbs[2]._y2_arb : 0 [by my_tree.at_cell.arbs[2].arbiter._y2:=1]
65483 my_tree.at_cell.arbs[3].ack_cell2._y : 1 [by my_tree.at_cell.arbs[3]._y2_arb:=0]
65487 my_tree.in[4].a : 0 [by my_tree.at_cell.arbs[3].ack_cell2._y:=1]
74434 my_tree.at_cell.arbs[2].or_cell._y : 1 [by my_tree.at_cell.arbs[2]._y2_arb:=0]
83563 my_tree.at_cell.tmp[8].r : 0 [by my_tree.at_cell.arbs[2].or_cell._y:=1]
83578 my_tree.at_cell.arbs[3].arbiter._y1 : 1 [by my_tree.at_cell.tmp[8].r:=0]
126826 my_tree.at_cell.arbs[3]._y1_arb : 0 [by my_tree.at_cell.arbs[3].arbiter._y1:=1]
126881 my_tree.at_cell.arbs[3].or_cell._y : 1 [by my_tree.at_cell.arbs[3]._y1_arb:=0]
163757 my_tree.at_cell.arbs[3].ack_cell1._y : 1 [by my_tree.at_cell.arbs[3]._y1_arb:=0]
178534 my_tree.out.r : 0 [by my_tree.at_cell.arbs[3].or_cell._y:=1]
193537 my_tree.at_cell.tmp[8].a : 0 [by my_tree.at_cell.arbs[3].ack_cell1._y:=1]
207386 my_tree.at_cell.arbs[2].ack_cell2._y : 1 [by my_tree.at_cell.tmp[8].a:=0]
218349 my_tree.at_cell.arbs[2].ack_cell1._y : 1 [by my_tree.at_cell.tmp[8].a:=0]
218771 my_tree.at_cell.tmp[5].a : 0 [by my_tree.at_cell.arbs[2].ack_cell1._y:=1]
218772 my_tree.at_cell.arbs[0].ack_cell1._y : 1 [by my_tree.at_cell.tmp[5].a:=0]
218773 my_tree.in[0].a : 0 [by my_tree.at_cell.arbs[0].ack_cell1._y:=1]
221729 my_tree.at_cell.tmp[6].a : 0 [by my_tree.at_cell.arbs[2].ack_cell2._y:=1]
222011 my_tree.at_cell.arbs[1].ack_cell1._y : 1 [by my_tree.at_cell.tmp[6].a:=0]
222779 my_tree.in[2].a : 0 [by my_tree.at_cell.arbs[1].ack_cell1._y:=1]
241934 my_tree.at_cell.arbs[1].ack_cell2._y : 1 [by my_tree.at_cell.tmp[6].a:=0]
241937 my_tree.in[3].a : 0 [by my_tree.at_cell.arbs[1].ack_cell2._y:=1]
267485 my_tree.at_cell.arbs[0].ack_cell2._y : 1 [by my_tree.at_cell.tmp[5].a:=0]
289926 my_tree.in[1].a : 0 [by my_tree.at_cell.arbs[0].ack_cell2._y:=1]
-------------------------------------------------
[0] System initialized
289926 Reset : 0
290477 my_tree._reset_B : 1 [by Reset:=0]
-------------------------------------------------
[1] System reset completed
290477 my_tree.in[0].r : 1
290477 my_tree.in[4].r : 1
290477 my_tree.in[2].r : 1
291431 my_tree.at_cell.arbs[3].arbiter._y2 : 0 [by my_tree.in[4].r:=1]
291548 my_tree.at_cell.arbs[0].arbiter._y1 : 0 [by my_tree.in[0].r:=1]
291558 my_tree.at_cell.arbs[1].arbiter._y1 : 0 [by my_tree.in[2].r:=1]
291576 my_tree.at_cell.arbs[1]._y1_arb : 1 [by my_tree.at_cell.arbs[1].arbiter._y1:=0]
292530 my_tree.at_cell.arbs[0]._y1_arb : 1 [by my_tree.at_cell.arbs[0].arbiter._y1:=0]
295589 my_tree.at_cell.arbs[1].or_cell._y : 0 [by my_tree.at_cell.arbs[1]._y1_arb:=1]
296533 my_tree.at_cell.arbs[0].or_cell._y : 0 [by my_tree.at_cell.arbs[0]._y1_arb:=1]
318117 my_tree.at_cell.tmp[5].r : 1 [by my_tree.at_cell.arbs[0].or_cell._y:=0]
322877 my_tree.at_cell.arbs[2].arbiter._y1 : 0 [by my_tree.at_cell.tmp[5].r:=1]
323379 my_tree.at_cell.arbs[2]._y1_arb : 1 [by my_tree.at_cell.arbs[2].arbiter._y1:=0]
323582 my_tree.at_cell.arbs[2].or_cell._y : 0 [by my_tree.at_cell.arbs[2]._y1_arb:=1]
325436 my_tree.at_cell.tmp[8].r : 1 [by my_tree.at_cell.arbs[2].or_cell._y:=0]
340490 my_tree.at_cell.tmp[6].r : 1 [by my_tree.at_cell.arbs[1].or_cell._y:=0]
345901 my_tree.at_cell.arbs[3]._y2_arb : 1 [by my_tree.at_cell.arbs[3].arbiter._y2:=0]
346040 my_tree.at_cell.arbs[3].or_cell._y : 0 [by my_tree.at_cell.arbs[3]._y2_arb:=1]
382386 my_tree.out.r : 1 [by my_tree.at_cell.arbs[3].or_cell._y:=0]
382386 my_tree.out.a : 1
382455 my_tree.at_cell.arbs[3].ack_cell2._y : 0 [by my_tree.out.a:=1]
382466 my_tree.in[4].a : 1 [by my_tree.at_cell.arbs[3].ack_cell2._y:=0]
-------------------------------------------------
[2] Number 4 was chosen, move to the next one
382466 my_tree.in[4].r : 0
434252 my_tree.at_cell.arbs[3].arbiter._y2 : 1 [by my_tree.in[4].r:=0]
434267 my_tree.at_cell.arbs[3]._y2_arb : 0 [by my_tree.at_cell.arbs[3].arbiter._y2:=1]
434268 my_tree.at_cell.arbs[3].or_cell._y : 1 [by my_tree.at_cell.arbs[3]._y2_arb:=0]
434305 my_tree.out.r : 0 [by my_tree.at_cell.arbs[3].or_cell._y:=1]
434456 my_tree.at_cell.arbs[3].arbiter._y1 : 0 [by my_tree.at_cell.arbs[3].arbiter._y2:=1]
434456 my_tree.out.a : 0
435195 my_tree.at_cell.arbs[3].ack_cell2._y : 1 [by my_tree.out.a:=0]
435307 my_tree.in[4].a : 0 [by my_tree.at_cell.arbs[3].ack_cell2._y:=1]
482819 my_tree.at_cell.arbs[3]._y1_arb : 1 [by my_tree.in[4].a:=0]
482859 my_tree.at_cell.arbs[3].or_cell._y : 0 [by my_tree.at_cell.arbs[3]._y1_arb:=1]
483116 my_tree.out.r : 1 [by my_tree.at_cell.arbs[3].or_cell._y:=0]
483116 my_tree.out.a : 1
483203 my_tree.at_cell.arbs[3].ack_cell1._y : 0 [by my_tree.out.a:=1]
483497 my_tree.at_cell.tmp[8].a : 1 [by my_tree.at_cell.arbs[3].ack_cell1._y:=0]
483498 my_tree.at_cell.arbs[2].ack_cell1._y : 0 [by my_tree.at_cell.tmp[8].a:=1]
485304 my_tree.at_cell.tmp[5].a : 1 [by my_tree.at_cell.arbs[2].ack_cell1._y:=0]
487311 my_tree.at_cell.arbs[0].ack_cell1._y : 0 [by my_tree.at_cell.tmp[5].a:=1]
488520 my_tree.in[0].a : 1 [by my_tree.at_cell.arbs[0].ack_cell1._y:=0]
-------------------------------------------------
[2] Number 0 was chosen, finish test

325
test/unit_tests/arbiter_tree_simple_nosim/run/test.prs
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@@ -1,325 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"Reset"->"my_tree._reset_B"-
~("Reset")->"my_tree._reset_B"+
= "my_tree.at_cell.arbs[0].in1.d.d[0]" "my_tree.at_cell.arbs[0].in1.r"
= "my_tree.at_cell.arbs[0].in1.a" "my_tree.at_cell.arbs[0].arbiter.d"
= "my_tree.at_cell.arbs[0].in1.a" "my_tree.at_cell.arbs[0].ack_cell1.y"
= "my_tree.at_cell.arbs[0].in1.d.d[0]" "my_tree.at_cell.arbs[0].arbiter.a"
= "my_tree.at_cell.arbs[0].in1.d.d[0]" "my_tree.at_cell.arbs[0].in1.r"
~"my_tree.at_cell.arbs[0].ack_cell1.c1"&~"my_tree.at_cell.arbs[0].ack_cell1.c2"->"my_tree.at_cell.arbs[0].ack_cell1._y"+
"my_tree.at_cell.arbs[0].ack_cell1.c1"&"my_tree.at_cell.arbs[0].ack_cell1.c2"->"my_tree.at_cell.arbs[0].ack_cell1._y"-
"my_tree.at_cell.arbs[0].ack_cell1._y"->"my_tree.at_cell.arbs[0].ack_cell1.y"-
~("my_tree.at_cell.arbs[0].ack_cell1._y")->"my_tree.at_cell.arbs[0].ack_cell1.y"+
= "my_tree.at_cell.arbs[0].in2.d.d[0]" "my_tree.at_cell.arbs[0].in2.r"
= "my_tree.at_cell.arbs[0].in2.a" "my_tree.at_cell.arbs[0].arbiter.c"
= "my_tree.at_cell.arbs[0].in2.a" "my_tree.at_cell.arbs[0].ack_cell2.y"
= "my_tree.at_cell.arbs[0].in2.d.d[0]" "my_tree.at_cell.arbs[0].arbiter.b"
= "my_tree.at_cell.arbs[0].in2.d.d[0]" "my_tree.at_cell.arbs[0].in2.r"
= "my_tree.at_cell.arbs[0].supply.vdd" "my_tree.at_cell.arbs[0].arbiter.vdd"
= "my_tree.at_cell.arbs[0].supply.vdd" "my_tree.at_cell.arbs[0].or_cell.vdd"
= "my_tree.at_cell.arbs[0].supply.vdd" "my_tree.at_cell.arbs[0].ack_cell2.vdd"
= "my_tree.at_cell.arbs[0].supply.vdd" "my_tree.at_cell.arbs[0].ack_cell1.vdd"
= "my_tree.at_cell.arbs[0].supply.vss" "my_tree.at_cell.arbs[0].arbiter.vss"
= "my_tree.at_cell.arbs[0].supply.vss" "my_tree.at_cell.arbs[0].or_cell.vss"
= "my_tree.at_cell.arbs[0].supply.vss" "my_tree.at_cell.arbs[0].ack_cell2.vss"
= "my_tree.at_cell.arbs[0].supply.vss" "my_tree.at_cell.arbs[0].ack_cell1.vss"
"my_tree.at_cell.arbs[0].arbiter.a"&"my_tree.at_cell.arbs[0].arbiter._y2"->"my_tree.at_cell.arbs[0].arbiter._y1"-
~"my_tree.at_cell.arbs[0].arbiter.a"|~"my_tree.at_cell.arbs[0].arbiter._y2"->"my_tree.at_cell.arbs[0].arbiter._y1"+
"my_tree.at_cell.arbs[0].arbiter.b"&"my_tree.at_cell.arbs[0].arbiter._y1"->"my_tree.at_cell.arbs[0].arbiter._y2"-
~"my_tree.at_cell.arbs[0].arbiter.b"|~"my_tree.at_cell.arbs[0].arbiter._y1"->"my_tree.at_cell.arbs[0].arbiter._y2"+
"my_tree.at_cell.arbs[0].arbiter._y1"|"my_tree.at_cell.arbs[0].arbiter.c"->"my_tree.at_cell.arbs[0].arbiter.y1"-
~("my_tree.at_cell.arbs[0].arbiter._y1"|"my_tree.at_cell.arbs[0].arbiter.c")->"my_tree.at_cell.arbs[0].arbiter.y1"+
"my_tree.at_cell.arbs[0].arbiter._y2"|"my_tree.at_cell.arbs[0].arbiter.d"->"my_tree.at_cell.arbs[0].arbiter.y2"-
~("my_tree.at_cell.arbs[0].arbiter._y2"|"my_tree.at_cell.arbs[0].arbiter.d")->"my_tree.at_cell.arbs[0].arbiter.y2"+
mk_excllo("my_tree.at_cell.arbs[0].arbiter._y1","my_tree.at_cell.arbs[0].arbiter._y2")
= "my_tree.at_cell.arbs[0]._y1_arb" "my_tree.at_cell.arbs[0].arbiter.y1"
= "my_tree.at_cell.arbs[0]._y1_arb" "my_tree.at_cell.arbs[0].or_cell.a"
= "my_tree.at_cell.arbs[0]._y1_arb" "my_tree.at_cell.arbs[0].ack_cell1.c2"
~"my_tree.at_cell.arbs[0].ack_cell2.c1"&~"my_tree.at_cell.arbs[0].ack_cell2.c2"->"my_tree.at_cell.arbs[0].ack_cell2._y"+
"my_tree.at_cell.arbs[0].ack_cell2.c1"&"my_tree.at_cell.arbs[0].ack_cell2.c2"->"my_tree.at_cell.arbs[0].ack_cell2._y"-
"my_tree.at_cell.arbs[0].ack_cell2._y"->"my_tree.at_cell.arbs[0].ack_cell2.y"-
~("my_tree.at_cell.arbs[0].ack_cell2._y")->"my_tree.at_cell.arbs[0].ack_cell2.y"+
"my_tree.at_cell.arbs[0].or_cell.a"|"my_tree.at_cell.arbs[0].or_cell.b"->"my_tree.at_cell.arbs[0].or_cell._y"-
~("my_tree.at_cell.arbs[0].or_cell.a"|"my_tree.at_cell.arbs[0].or_cell.b")->"my_tree.at_cell.arbs[0].or_cell._y"+
"my_tree.at_cell.arbs[0].or_cell._y"->"my_tree.at_cell.arbs[0].or_cell.y"-
~("my_tree.at_cell.arbs[0].or_cell._y")->"my_tree.at_cell.arbs[0].or_cell.y"+
= "my_tree.at_cell.arbs[0].out.d.d[0]" "my_tree.at_cell.arbs[0].out.r"
= "my_tree.at_cell.arbs[0].out.a" "my_tree.at_cell.arbs[0].ack_cell2.c1"
= "my_tree.at_cell.arbs[0].out.a" "my_tree.at_cell.arbs[0].ack_cell1.c1"
= "my_tree.at_cell.arbs[0].out.d.d[0]" "my_tree.at_cell.arbs[0].or_cell.y"
= "my_tree.at_cell.arbs[0].out.d.d[0]" "my_tree.at_cell.arbs[0].out.r"
= "my_tree.at_cell.arbs[0]._y2_arb" "my_tree.at_cell.arbs[0].arbiter.y2"
= "my_tree.at_cell.arbs[0]._y2_arb" "my_tree.at_cell.arbs[0].or_cell.b"
= "my_tree.at_cell.arbs[0]._y2_arb" "my_tree.at_cell.arbs[0].ack_cell2.c2"
= "my_tree.at_cell.arbs[1].in1.d.d[0]" "my_tree.at_cell.arbs[1].in1.r"
= "my_tree.at_cell.arbs[1].in1.a" "my_tree.at_cell.arbs[1].arbiter.d"
= "my_tree.at_cell.arbs[1].in1.a" "my_tree.at_cell.arbs[1].ack_cell1.y"
= "my_tree.at_cell.arbs[1].in1.d.d[0]" "my_tree.at_cell.arbs[1].arbiter.a"
= "my_tree.at_cell.arbs[1].in1.d.d[0]" "my_tree.at_cell.arbs[1].in1.r"
~"my_tree.at_cell.arbs[1].ack_cell1.c1"&~"my_tree.at_cell.arbs[1].ack_cell1.c2"->"my_tree.at_cell.arbs[1].ack_cell1._y"+
"my_tree.at_cell.arbs[1].ack_cell1.c1"&"my_tree.at_cell.arbs[1].ack_cell1.c2"->"my_tree.at_cell.arbs[1].ack_cell1._y"-
"my_tree.at_cell.arbs[1].ack_cell1._y"->"my_tree.at_cell.arbs[1].ack_cell1.y"-
~("my_tree.at_cell.arbs[1].ack_cell1._y")->"my_tree.at_cell.arbs[1].ack_cell1.y"+
= "my_tree.at_cell.arbs[1].in2.d.d[0]" "my_tree.at_cell.arbs[1].in2.r"
= "my_tree.at_cell.arbs[1].in2.a" "my_tree.at_cell.arbs[1].arbiter.c"
= "my_tree.at_cell.arbs[1].in2.a" "my_tree.at_cell.arbs[1].ack_cell2.y"
= "my_tree.at_cell.arbs[1].in2.d.d[0]" "my_tree.at_cell.arbs[1].arbiter.b"
= "my_tree.at_cell.arbs[1].in2.d.d[0]" "my_tree.at_cell.arbs[1].in2.r"
= "my_tree.at_cell.arbs[1].supply.vdd" "my_tree.at_cell.arbs[1].arbiter.vdd"
= "my_tree.at_cell.arbs[1].supply.vdd" "my_tree.at_cell.arbs[1].or_cell.vdd"
= "my_tree.at_cell.arbs[1].supply.vdd" "my_tree.at_cell.arbs[1].ack_cell2.vdd"
= "my_tree.at_cell.arbs[1].supply.vdd" "my_tree.at_cell.arbs[1].ack_cell1.vdd"
= "my_tree.at_cell.arbs[1].supply.vss" "my_tree.at_cell.arbs[1].arbiter.vss"
= "my_tree.at_cell.arbs[1].supply.vss" "my_tree.at_cell.arbs[1].or_cell.vss"
= "my_tree.at_cell.arbs[1].supply.vss" "my_tree.at_cell.arbs[1].ack_cell2.vss"
= "my_tree.at_cell.arbs[1].supply.vss" "my_tree.at_cell.arbs[1].ack_cell1.vss"
"my_tree.at_cell.arbs[1].arbiter.a"&"my_tree.at_cell.arbs[1].arbiter._y2"->"my_tree.at_cell.arbs[1].arbiter._y1"-
~"my_tree.at_cell.arbs[1].arbiter.a"|~"my_tree.at_cell.arbs[1].arbiter._y2"->"my_tree.at_cell.arbs[1].arbiter._y1"+
"my_tree.at_cell.arbs[1].arbiter.b"&"my_tree.at_cell.arbs[1].arbiter._y1"->"my_tree.at_cell.arbs[1].arbiter._y2"-
~"my_tree.at_cell.arbs[1].arbiter.b"|~"my_tree.at_cell.arbs[1].arbiter._y1"->"my_tree.at_cell.arbs[1].arbiter._y2"+
"my_tree.at_cell.arbs[1].arbiter._y1"|"my_tree.at_cell.arbs[1].arbiter.c"->"my_tree.at_cell.arbs[1].arbiter.y1"-
~("my_tree.at_cell.arbs[1].arbiter._y1"|"my_tree.at_cell.arbs[1].arbiter.c")->"my_tree.at_cell.arbs[1].arbiter.y1"+
"my_tree.at_cell.arbs[1].arbiter._y2"|"my_tree.at_cell.arbs[1].arbiter.d"->"my_tree.at_cell.arbs[1].arbiter.y2"-
~("my_tree.at_cell.arbs[1].arbiter._y2"|"my_tree.at_cell.arbs[1].arbiter.d")->"my_tree.at_cell.arbs[1].arbiter.y2"+
mk_excllo("my_tree.at_cell.arbs[1].arbiter._y1","my_tree.at_cell.arbs[1].arbiter._y2")
= "my_tree.at_cell.arbs[1]._y1_arb" "my_tree.at_cell.arbs[1].arbiter.y1"
= "my_tree.at_cell.arbs[1]._y1_arb" "my_tree.at_cell.arbs[1].or_cell.a"
= "my_tree.at_cell.arbs[1]._y1_arb" "my_tree.at_cell.arbs[1].ack_cell1.c2"
~"my_tree.at_cell.arbs[1].ack_cell2.c1"&~"my_tree.at_cell.arbs[1].ack_cell2.c2"->"my_tree.at_cell.arbs[1].ack_cell2._y"+
"my_tree.at_cell.arbs[1].ack_cell2.c1"&"my_tree.at_cell.arbs[1].ack_cell2.c2"->"my_tree.at_cell.arbs[1].ack_cell2._y"-
"my_tree.at_cell.arbs[1].ack_cell2._y"->"my_tree.at_cell.arbs[1].ack_cell2.y"-
~("my_tree.at_cell.arbs[1].ack_cell2._y")->"my_tree.at_cell.arbs[1].ack_cell2.y"+
"my_tree.at_cell.arbs[1].or_cell.a"|"my_tree.at_cell.arbs[1].or_cell.b"->"my_tree.at_cell.arbs[1].or_cell._y"-
~("my_tree.at_cell.arbs[1].or_cell.a"|"my_tree.at_cell.arbs[1].or_cell.b")->"my_tree.at_cell.arbs[1].or_cell._y"+
"my_tree.at_cell.arbs[1].or_cell._y"->"my_tree.at_cell.arbs[1].or_cell.y"-
~("my_tree.at_cell.arbs[1].or_cell._y")->"my_tree.at_cell.arbs[1].or_cell.y"+
= "my_tree.at_cell.arbs[1].out.d.d[0]" "my_tree.at_cell.arbs[1].out.r"
= "my_tree.at_cell.arbs[1].out.a" "my_tree.at_cell.arbs[1].ack_cell2.c1"
= "my_tree.at_cell.arbs[1].out.a" "my_tree.at_cell.arbs[1].ack_cell1.c1"
= "my_tree.at_cell.arbs[1].out.d.d[0]" "my_tree.at_cell.arbs[1].or_cell.y"
= "my_tree.at_cell.arbs[1].out.d.d[0]" "my_tree.at_cell.arbs[1].out.r"
= "my_tree.at_cell.arbs[1]._y2_arb" "my_tree.at_cell.arbs[1].arbiter.y2"
= "my_tree.at_cell.arbs[1]._y2_arb" "my_tree.at_cell.arbs[1].or_cell.b"
= "my_tree.at_cell.arbs[1]._y2_arb" "my_tree.at_cell.arbs[1].ack_cell2.c2"
= "my_tree.at_cell.arbs[2].in1.d.d[0]" "my_tree.at_cell.arbs[2].in1.r"
= "my_tree.at_cell.arbs[2].in1.a" "my_tree.at_cell.arbs[2].arbiter.d"
= "my_tree.at_cell.arbs[2].in1.a" "my_tree.at_cell.arbs[2].ack_cell1.y"
= "my_tree.at_cell.arbs[2].in1.d.d[0]" "my_tree.at_cell.arbs[2].arbiter.a"
= "my_tree.at_cell.arbs[2].in1.d.d[0]" "my_tree.at_cell.arbs[2].in1.r"
~"my_tree.at_cell.arbs[2].ack_cell1.c1"&~"my_tree.at_cell.arbs[2].ack_cell1.c2"->"my_tree.at_cell.arbs[2].ack_cell1._y"+
"my_tree.at_cell.arbs[2].ack_cell1.c1"&"my_tree.at_cell.arbs[2].ack_cell1.c2"->"my_tree.at_cell.arbs[2].ack_cell1._y"-
"my_tree.at_cell.arbs[2].ack_cell1._y"->"my_tree.at_cell.arbs[2].ack_cell1.y"-
~("my_tree.at_cell.arbs[2].ack_cell1._y")->"my_tree.at_cell.arbs[2].ack_cell1.y"+
= "my_tree.at_cell.arbs[2].in2.d.d[0]" "my_tree.at_cell.arbs[2].in2.r"
= "my_tree.at_cell.arbs[2].in2.a" "my_tree.at_cell.arbs[2].arbiter.c"
= "my_tree.at_cell.arbs[2].in2.a" "my_tree.at_cell.arbs[2].ack_cell2.y"
= "my_tree.at_cell.arbs[2].in2.d.d[0]" "my_tree.at_cell.arbs[2].arbiter.b"
= "my_tree.at_cell.arbs[2].in2.d.d[0]" "my_tree.at_cell.arbs[2].in2.r"
= "my_tree.at_cell.arbs[2].supply.vdd" "my_tree.at_cell.arbs[2].arbiter.vdd"
= "my_tree.at_cell.arbs[2].supply.vdd" "my_tree.at_cell.arbs[2].or_cell.vdd"
= "my_tree.at_cell.arbs[2].supply.vdd" "my_tree.at_cell.arbs[2].ack_cell2.vdd"
= "my_tree.at_cell.arbs[2].supply.vdd" "my_tree.at_cell.arbs[2].ack_cell1.vdd"
= "my_tree.at_cell.arbs[2].supply.vss" "my_tree.at_cell.arbs[2].arbiter.vss"
= "my_tree.at_cell.arbs[2].supply.vss" "my_tree.at_cell.arbs[2].or_cell.vss"
= "my_tree.at_cell.arbs[2].supply.vss" "my_tree.at_cell.arbs[2].ack_cell2.vss"
= "my_tree.at_cell.arbs[2].supply.vss" "my_tree.at_cell.arbs[2].ack_cell1.vss"
"my_tree.at_cell.arbs[2].arbiter.a"&"my_tree.at_cell.arbs[2].arbiter._y2"->"my_tree.at_cell.arbs[2].arbiter._y1"-
~"my_tree.at_cell.arbs[2].arbiter.a"|~"my_tree.at_cell.arbs[2].arbiter._y2"->"my_tree.at_cell.arbs[2].arbiter._y1"+
"my_tree.at_cell.arbs[2].arbiter.b"&"my_tree.at_cell.arbs[2].arbiter._y1"->"my_tree.at_cell.arbs[2].arbiter._y2"-
~"my_tree.at_cell.arbs[2].arbiter.b"|~"my_tree.at_cell.arbs[2].arbiter._y1"->"my_tree.at_cell.arbs[2].arbiter._y2"+
"my_tree.at_cell.arbs[2].arbiter._y1"|"my_tree.at_cell.arbs[2].arbiter.c"->"my_tree.at_cell.arbs[2].arbiter.y1"-
~("my_tree.at_cell.arbs[2].arbiter._y1"|"my_tree.at_cell.arbs[2].arbiter.c")->"my_tree.at_cell.arbs[2].arbiter.y1"+
"my_tree.at_cell.arbs[2].arbiter._y2"|"my_tree.at_cell.arbs[2].arbiter.d"->"my_tree.at_cell.arbs[2].arbiter.y2"-
~("my_tree.at_cell.arbs[2].arbiter._y2"|"my_tree.at_cell.arbs[2].arbiter.d")->"my_tree.at_cell.arbs[2].arbiter.y2"+
mk_excllo("my_tree.at_cell.arbs[2].arbiter._y1","my_tree.at_cell.arbs[2].arbiter._y2")
= "my_tree.at_cell.arbs[2]._y1_arb" "my_tree.at_cell.arbs[2].arbiter.y1"
= "my_tree.at_cell.arbs[2]._y1_arb" "my_tree.at_cell.arbs[2].or_cell.a"
= "my_tree.at_cell.arbs[2]._y1_arb" "my_tree.at_cell.arbs[2].ack_cell1.c2"
~"my_tree.at_cell.arbs[2].ack_cell2.c1"&~"my_tree.at_cell.arbs[2].ack_cell2.c2"->"my_tree.at_cell.arbs[2].ack_cell2._y"+
"my_tree.at_cell.arbs[2].ack_cell2.c1"&"my_tree.at_cell.arbs[2].ack_cell2.c2"->"my_tree.at_cell.arbs[2].ack_cell2._y"-
"my_tree.at_cell.arbs[2].ack_cell2._y"->"my_tree.at_cell.arbs[2].ack_cell2.y"-
~("my_tree.at_cell.arbs[2].ack_cell2._y")->"my_tree.at_cell.arbs[2].ack_cell2.y"+
"my_tree.at_cell.arbs[2].or_cell.a"|"my_tree.at_cell.arbs[2].or_cell.b"->"my_tree.at_cell.arbs[2].or_cell._y"-
~("my_tree.at_cell.arbs[2].or_cell.a"|"my_tree.at_cell.arbs[2].or_cell.b")->"my_tree.at_cell.arbs[2].or_cell._y"+
"my_tree.at_cell.arbs[2].or_cell._y"->"my_tree.at_cell.arbs[2].or_cell.y"-
~("my_tree.at_cell.arbs[2].or_cell._y")->"my_tree.at_cell.arbs[2].or_cell.y"+
= "my_tree.at_cell.arbs[2].out.d.d[0]" "my_tree.at_cell.arbs[2].out.r"
= "my_tree.at_cell.arbs[2].out.a" "my_tree.at_cell.arbs[2].ack_cell2.c1"
= "my_tree.at_cell.arbs[2].out.a" "my_tree.at_cell.arbs[2].ack_cell1.c1"
= "my_tree.at_cell.arbs[2].out.d.d[0]" "my_tree.at_cell.arbs[2].or_cell.y"
= "my_tree.at_cell.arbs[2].out.d.d[0]" "my_tree.at_cell.arbs[2].out.r"
= "my_tree.at_cell.arbs[2]._y2_arb" "my_tree.at_cell.arbs[2].arbiter.y2"
= "my_tree.at_cell.arbs[2]._y2_arb" "my_tree.at_cell.arbs[2].or_cell.b"
= "my_tree.at_cell.arbs[2]._y2_arb" "my_tree.at_cell.arbs[2].ack_cell2.c2"
= "my_tree.at_cell.arbs[3].in1.d.d[0]" "my_tree.at_cell.arbs[3].in1.r"
= "my_tree.at_cell.arbs[3].in1.a" "my_tree.at_cell.arbs[3].arbiter.d"
= "my_tree.at_cell.arbs[3].in1.a" "my_tree.at_cell.arbs[3].ack_cell1.y"
= "my_tree.at_cell.arbs[3].in1.d.d[0]" "my_tree.at_cell.arbs[3].arbiter.a"
= "my_tree.at_cell.arbs[3].in1.d.d[0]" "my_tree.at_cell.arbs[3].in1.r"
~"my_tree.at_cell.arbs[3].ack_cell1.c1"&~"my_tree.at_cell.arbs[3].ack_cell1.c2"->"my_tree.at_cell.arbs[3].ack_cell1._y"+
"my_tree.at_cell.arbs[3].ack_cell1.c1"&"my_tree.at_cell.arbs[3].ack_cell1.c2"->"my_tree.at_cell.arbs[3].ack_cell1._y"-
"my_tree.at_cell.arbs[3].ack_cell1._y"->"my_tree.at_cell.arbs[3].ack_cell1.y"-
~("my_tree.at_cell.arbs[3].ack_cell1._y")->"my_tree.at_cell.arbs[3].ack_cell1.y"+
= "my_tree.at_cell.arbs[3].in2.d.d[0]" "my_tree.at_cell.arbs[3].in2.r"
= "my_tree.at_cell.arbs[3].in2.a" "my_tree.at_cell.arbs[3].arbiter.c"
= "my_tree.at_cell.arbs[3].in2.a" "my_tree.at_cell.arbs[3].ack_cell2.y"
= "my_tree.at_cell.arbs[3].in2.d.d[0]" "my_tree.at_cell.arbs[3].arbiter.b"
= "my_tree.at_cell.arbs[3].in2.d.d[0]" "my_tree.at_cell.arbs[3].in2.r"
= "my_tree.at_cell.arbs[3].supply.vdd" "my_tree.at_cell.arbs[3].arbiter.vdd"
= "my_tree.at_cell.arbs[3].supply.vdd" "my_tree.at_cell.arbs[3].or_cell.vdd"
= "my_tree.at_cell.arbs[3].supply.vdd" "my_tree.at_cell.arbs[3].ack_cell2.vdd"
= "my_tree.at_cell.arbs[3].supply.vdd" "my_tree.at_cell.arbs[3].ack_cell1.vdd"
= "my_tree.at_cell.arbs[3].supply.vss" "my_tree.at_cell.arbs[3].arbiter.vss"
= "my_tree.at_cell.arbs[3].supply.vss" "my_tree.at_cell.arbs[3].or_cell.vss"
= "my_tree.at_cell.arbs[3].supply.vss" "my_tree.at_cell.arbs[3].ack_cell2.vss"
= "my_tree.at_cell.arbs[3].supply.vss" "my_tree.at_cell.arbs[3].ack_cell1.vss"
"my_tree.at_cell.arbs[3].arbiter.a"&"my_tree.at_cell.arbs[3].arbiter._y2"->"my_tree.at_cell.arbs[3].arbiter._y1"-
~"my_tree.at_cell.arbs[3].arbiter.a"|~"my_tree.at_cell.arbs[3].arbiter._y2"->"my_tree.at_cell.arbs[3].arbiter._y1"+
"my_tree.at_cell.arbs[3].arbiter.b"&"my_tree.at_cell.arbs[3].arbiter._y1"->"my_tree.at_cell.arbs[3].arbiter._y2"-
~"my_tree.at_cell.arbs[3].arbiter.b"|~"my_tree.at_cell.arbs[3].arbiter._y1"->"my_tree.at_cell.arbs[3].arbiter._y2"+
"my_tree.at_cell.arbs[3].arbiter._y1"|"my_tree.at_cell.arbs[3].arbiter.c"->"my_tree.at_cell.arbs[3].arbiter.y1"-
~("my_tree.at_cell.arbs[3].arbiter._y1"|"my_tree.at_cell.arbs[3].arbiter.c")->"my_tree.at_cell.arbs[3].arbiter.y1"+
"my_tree.at_cell.arbs[3].arbiter._y2"|"my_tree.at_cell.arbs[3].arbiter.d"->"my_tree.at_cell.arbs[3].arbiter.y2"-
~("my_tree.at_cell.arbs[3].arbiter._y2"|"my_tree.at_cell.arbs[3].arbiter.d")->"my_tree.at_cell.arbs[3].arbiter.y2"+
mk_excllo("my_tree.at_cell.arbs[3].arbiter._y1","my_tree.at_cell.arbs[3].arbiter._y2")
= "my_tree.at_cell.arbs[3]._y1_arb" "my_tree.at_cell.arbs[3].arbiter.y1"
= "my_tree.at_cell.arbs[3]._y1_arb" "my_tree.at_cell.arbs[3].or_cell.a"
= "my_tree.at_cell.arbs[3]._y1_arb" "my_tree.at_cell.arbs[3].ack_cell1.c2"
~"my_tree.at_cell.arbs[3].ack_cell2.c1"&~"my_tree.at_cell.arbs[3].ack_cell2.c2"->"my_tree.at_cell.arbs[3].ack_cell2._y"+
"my_tree.at_cell.arbs[3].ack_cell2.c1"&"my_tree.at_cell.arbs[3].ack_cell2.c2"->"my_tree.at_cell.arbs[3].ack_cell2._y"-
"my_tree.at_cell.arbs[3].ack_cell2._y"->"my_tree.at_cell.arbs[3].ack_cell2.y"-
~("my_tree.at_cell.arbs[3].ack_cell2._y")->"my_tree.at_cell.arbs[3].ack_cell2.y"+
"my_tree.at_cell.arbs[3].or_cell.a"|"my_tree.at_cell.arbs[3].or_cell.b"->"my_tree.at_cell.arbs[3].or_cell._y"-
~("my_tree.at_cell.arbs[3].or_cell.a"|"my_tree.at_cell.arbs[3].or_cell.b")->"my_tree.at_cell.arbs[3].or_cell._y"+
"my_tree.at_cell.arbs[3].or_cell._y"->"my_tree.at_cell.arbs[3].or_cell.y"-
~("my_tree.at_cell.arbs[3].or_cell._y")->"my_tree.at_cell.arbs[3].or_cell.y"+
= "my_tree.at_cell.arbs[3].out.d.d[0]" "my_tree.at_cell.arbs[3].out.r"
= "my_tree.at_cell.arbs[3].out.a" "my_tree.at_cell.arbs[3].ack_cell2.c1"
= "my_tree.at_cell.arbs[3].out.a" "my_tree.at_cell.arbs[3].ack_cell1.c1"
= "my_tree.at_cell.arbs[3].out.d.d[0]" "my_tree.at_cell.arbs[3].or_cell.y"
= "my_tree.at_cell.arbs[3].out.d.d[0]" "my_tree.at_cell.arbs[3].out.r"
= "my_tree.at_cell.arbs[3]._y2_arb" "my_tree.at_cell.arbs[3].arbiter.y2"
= "my_tree.at_cell.arbs[3]._y2_arb" "my_tree.at_cell.arbs[3].or_cell.b"
= "my_tree.at_cell.arbs[3]._y2_arb" "my_tree.at_cell.arbs[3].ack_cell2.c2"
= "my_tree.at_cell.tmp[5].d.d[0]" "my_tree.at_cell.tmp[5].r"
= "my_tree.at_cell.tmp[6].d.d[0]" "my_tree.at_cell.tmp[6].r"
= "my_tree.at_cell.tmp[8].d.d[0]" "my_tree.at_cell.tmp[8].r"
= "my_tree.at_cell.tmp[5].r" "my_tree.at_cell.arbs[2].in1.r"
= "my_tree.at_cell.tmp[5].a" "my_tree.at_cell.arbs[2].in1.a"
= "my_tree.at_cell.tmp[5].d.d[0]" "my_tree.at_cell.arbs[2].in1.d.d[0]"
= "my_tree.at_cell.tmp[5].r" "my_tree.at_cell.arbs[0].out.r"
= "my_tree.at_cell.tmp[5].a" "my_tree.at_cell.arbs[0].out.a"
= "my_tree.at_cell.tmp[5].d.d[0]" "my_tree.at_cell.arbs[0].out.d.d[0]"
= "my_tree.at_cell.tmp[6].r" "my_tree.at_cell.arbs[2].in2.r"
= "my_tree.at_cell.tmp[6].a" "my_tree.at_cell.arbs[2].in2.a"
= "my_tree.at_cell.tmp[6].d.d[0]" "my_tree.at_cell.arbs[2].in2.d.d[0]"
= "my_tree.at_cell.tmp[6].r" "my_tree.at_cell.arbs[1].out.r"
= "my_tree.at_cell.tmp[6].a" "my_tree.at_cell.arbs[1].out.a"
= "my_tree.at_cell.tmp[6].d.d[0]" "my_tree.at_cell.arbs[1].out.d.d[0]"
= "my_tree.at_cell.tmp[8].r" "my_tree.at_cell.arbs[3].in1.r"
= "my_tree.at_cell.tmp[8].a" "my_tree.at_cell.arbs[3].in1.a"
= "my_tree.at_cell.tmp[8].d.d[0]" "my_tree.at_cell.arbs[3].in1.d.d[0]"
= "my_tree.at_cell.tmp[8].r" "my_tree.at_cell.arbs[2].out.r"
= "my_tree.at_cell.tmp[8].a" "my_tree.at_cell.arbs[2].out.a"
= "my_tree.at_cell.tmp[8].d.d[0]" "my_tree.at_cell.arbs[2].out.d.d[0]"
= "my_tree.at_cell.tmp[8].d.d[0]" "my_tree.at_cell.tmp[8].r"
= "my_tree.at_cell.tmp[6].d.d[0]" "my_tree.at_cell.tmp[6].r"
= "my_tree.at_cell.tmp[5].d.d[0]" "my_tree.at_cell.tmp[5].r"
= "my_tree.at_cell.supply.vss" "my_tree.at_cell.arbs[3].supply.vss"
= "my_tree.at_cell.supply.vdd" "my_tree.at_cell.arbs[3].supply.vdd"
= "my_tree.at_cell.supply.vss" "my_tree.at_cell.arbs[2].supply.vss"
= "my_tree.at_cell.supply.vdd" "my_tree.at_cell.arbs[2].supply.vdd"
= "my_tree.at_cell.supply.vss" "my_tree.at_cell.arbs[1].supply.vss"
= "my_tree.at_cell.supply.vdd" "my_tree.at_cell.arbs[1].supply.vdd"
= "my_tree.at_cell.supply.vss" "my_tree.at_cell.arbs[0].supply.vss"
= "my_tree.at_cell.supply.vdd" "my_tree.at_cell.arbs[0].supply.vdd"
= "my_tree.at_cell.in[0].d.d[0]" "my_tree.at_cell.in[0].r"
= "my_tree.at_cell.in[1].d.d[0]" "my_tree.at_cell.in[1].r"
= "my_tree.at_cell.in[2].d.d[0]" "my_tree.at_cell.in[2].r"
= "my_tree.at_cell.in[3].d.d[0]" "my_tree.at_cell.in[3].r"
= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.in[4].r"
= "my_tree.at_cell.in[0].r" "my_tree.at_cell.arbs[0].in1.r"
= "my_tree.at_cell.in[0].a" "my_tree.at_cell.arbs[0].in1.a"
= "my_tree.at_cell.in[0].d.d[0]" "my_tree.at_cell.arbs[0].in1.d.d[0]"
= "my_tree.at_cell.in[0].r" "my_tree.at_cell.tmp[0].r"
= "my_tree.at_cell.in[0].a" "my_tree.at_cell.tmp[0].a"
= "my_tree.at_cell.in[0].d.d[0]" "my_tree.at_cell.tmp[0].d.d[0]"
= "my_tree.at_cell.in[1].r" "my_tree.at_cell.arbs[0].in2.r"
= "my_tree.at_cell.in[1].a" "my_tree.at_cell.arbs[0].in2.a"
= "my_tree.at_cell.in[1].d.d[0]" "my_tree.at_cell.arbs[0].in2.d.d[0]"
= "my_tree.at_cell.in[1].r" "my_tree.at_cell.tmp[1].r"
= "my_tree.at_cell.in[1].a" "my_tree.at_cell.tmp[1].a"
= "my_tree.at_cell.in[1].d.d[0]" "my_tree.at_cell.tmp[1].d.d[0]"
= "my_tree.at_cell.in[2].r" "my_tree.at_cell.arbs[1].in1.r"
= "my_tree.at_cell.in[2].a" "my_tree.at_cell.arbs[1].in1.a"
= "my_tree.at_cell.in[2].d.d[0]" "my_tree.at_cell.arbs[1].in1.d.d[0]"
= "my_tree.at_cell.in[2].r" "my_tree.at_cell.tmp[2].r"
= "my_tree.at_cell.in[2].a" "my_tree.at_cell.tmp[2].a"
= "my_tree.at_cell.in[2].d.d[0]" "my_tree.at_cell.tmp[2].d.d[0]"
= "my_tree.at_cell.in[3].r" "my_tree.at_cell.arbs[1].in2.r"
= "my_tree.at_cell.in[3].a" "my_tree.at_cell.arbs[1].in2.a"
= "my_tree.at_cell.in[3].d.d[0]" "my_tree.at_cell.arbs[1].in2.d.d[0]"
= "my_tree.at_cell.in[3].r" "my_tree.at_cell.tmp[3].r"
= "my_tree.at_cell.in[3].a" "my_tree.at_cell.tmp[3].a"
= "my_tree.at_cell.in[3].d.d[0]" "my_tree.at_cell.tmp[3].d.d[0]"
= "my_tree.at_cell.in[4].r" "my_tree.at_cell.arbs[3].in2.r"
= "my_tree.at_cell.in[4].a" "my_tree.at_cell.arbs[3].in2.a"
= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.arbs[3].in2.d.d[0]"
= "my_tree.at_cell.in[4].r" "my_tree.at_cell.tmp[9].r"
= "my_tree.at_cell.in[4].a" "my_tree.at_cell.tmp[9].a"
= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.tmp[9].d.d[0]"
= "my_tree.at_cell.in[4].r" "my_tree.at_cell.tmp[7].r"
= "my_tree.at_cell.in[4].a" "my_tree.at_cell.tmp[7].a"
= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.tmp[7].d.d[0]"
= "my_tree.at_cell.in[4].r" "my_tree.at_cell.tmp[4].r"
= "my_tree.at_cell.in[4].a" "my_tree.at_cell.tmp[4].a"
= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.tmp[4].d.d[0]"
= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.in[4].r"
= "my_tree.at_cell.in[3].d.d[0]" "my_tree.at_cell.in[3].r"
= "my_tree.at_cell.in[2].d.d[0]" "my_tree.at_cell.in[2].r"
= "my_tree.at_cell.in[1].d.d[0]" "my_tree.at_cell.in[1].r"
= "my_tree.at_cell.in[0].d.d[0]" "my_tree.at_cell.in[0].r"
= "my_tree.at_cell.out.d.d[0]" "my_tree.at_cell.out.r"
= "my_tree.at_cell.out.r" "my_tree.at_cell.arbs[3].out.r"
= "my_tree.at_cell.out.a" "my_tree.at_cell.arbs[3].out.a"
= "my_tree.at_cell.out.d.d[0]" "my_tree.at_cell.arbs[3].out.d.d[0]"
= "my_tree.at_cell.out.r" "my_tree.at_cell.tmp[10].r"
= "my_tree.at_cell.out.a" "my_tree.at_cell.tmp[10].a"
= "my_tree.at_cell.out.d.d[0]" "my_tree.at_cell.tmp[10].d.d[0]"
= "my_tree.at_cell.out.d.d[0]" "my_tree.at_cell.out.r"
= "my_tree._supply.vss" "my_tree.at_cell.supply.vss"
= "my_tree._supply.vdd" "my_tree.at_cell.supply.vdd"
= "Vdd" "my_tree._supply.vdd"
= "GND" "my_tree._supply.vss"
= "my_tree.out.d.d[0]" "my_tree.out.r"
= "my_tree.out.r" "my_tree.at_cell.out.r"
= "my_tree.out.a" "my_tree.at_cell.out.a"
= "my_tree.out.d.d[0]" "my_tree.at_cell.out.d.d[0]"
= "my_tree.out.d.d[0]" "my_tree.out.r"
= "my_tree.in[0].d.d[0]" "my_tree.in[0].r"
= "my_tree.in[1].d.d[0]" "my_tree.in[1].r"
= "my_tree.in[2].d.d[0]" "my_tree.in[2].r"
= "my_tree.in[3].d.d[0]" "my_tree.in[3].r"
= "my_tree.in[4].d.d[0]" "my_tree.in[4].r"
= "my_tree.in[0].r" "my_tree.at_cell.in[0].r"
= "my_tree.in[1].r" "my_tree.at_cell.in[1].r"
= "my_tree.in[2].r" "my_tree.at_cell.in[2].r"
= "my_tree.in[3].r" "my_tree.at_cell.in[3].r"
= "my_tree.in[4].r" "my_tree.at_cell.in[4].r"
= "my_tree.in[0].a" "my_tree.at_cell.in[0].a"
= "my_tree.in[1].a" "my_tree.at_cell.in[1].a"
= "my_tree.in[2].a" "my_tree.at_cell.in[2].a"
= "my_tree.in[3].a" "my_tree.at_cell.in[3].a"
= "my_tree.in[4].a" "my_tree.at_cell.in[4].a"
= "my_tree.in[0].d.d[0]" "my_tree.at_cell.in[0].d.d[0]"
= "my_tree.in[1].d.d[0]" "my_tree.at_cell.in[1].d.d[0]"
= "my_tree.in[2].d.d[0]" "my_tree.at_cell.in[2].d.d[0]"
= "my_tree.in[3].d.d[0]" "my_tree.at_cell.in[3].d.d[0]"
= "my_tree.in[4].d.d[0]" "my_tree.at_cell.in[4].d.d[0]"
= "my_tree.in[4].d.d[0]" "my_tree.in[4].r"
= "my_tree.in[3].d.d[0]" "my_tree.in[3].r"
= "my_tree.in[2].d.d[0]" "my_tree.in[2].r"
= "my_tree.in[1].d.d[0]" "my_tree.in[1].r"
= "my_tree.in[0].d.d[0]" "my_tree.in[0].r"

55
test/unit_tests/arbiter_tree_simple_nosim/test.act
View File

@@ -1,55 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/coders.act";
import globals;
open tmpl::dataflow_neuro;
defproc arbiter_treee (a1of1 in[5]; a1of1 out)
{
//Low active Reset
bool _reset_B;
prs {
Reset => _reset_B-
}
power _supply;
_supply.vdd = Vdd;
_supply.vss = GND;
arbtree<5> at_cell(.in=in, .out = out);
at_cell.supply = _supply;
}
arbiter_treee my_tree;

52
test/unit_tests/arbiter_tree_simple_nosim/test.prsim
View File

@@ -1,52 +0,0 @@
watchall
set my_tree.in[0].r 0
set my_tree.in[1].r 0
set my_tree.in[2].r 0
set my_tree.in[3].r 0
set my_tree.in[4].r 0
set my_tree.out.a 0
cycle
assert my_tree.in[0].a 0
assert my_tree.in[1].a 0
assert my_tree.in[2].a 0
assert my_tree.in[3].a 0
assert my_tree.in[4].a 0
assert my_tree.out.r 0
system "echo '-------------------------------------------------'"
system "echo '[0] System initialized'"
set Reset 0
cycle
system "echo '-------------------------------------------------'"
system "echo '[1] System reset completed'"
set my_tree.in[0].r 1
set my_tree.in[2].r 1
set my_tree.in[4].r 1
cycle
assert my_tree.out.r 1
set my_tree.out.a 1
cycle
assert my_tree.in[4].a 1
set my_tree.in[4].r 0
system "echo '-------------------------------------------------'"
system "echo '[2] Number 4 was chosen, move to the next one'"
cycle
assert my_tree.out.r 0
set my_tree.out.a 0
cycle
assert my_tree.in[4].a 0
assert my_tree.out.r 1
set my_tree.out.a 1
cycle
assert my_tree.in[0].a 1
system "echo '-------------------------------------------------'"
system "echo '[2] Number 0 was chosen, finish test'"

232
test/unit_tests/arbiter_tree_test/run/prsim.out
View File

@@ -1,232 +0,0 @@
my_tree.in[1].r my_tree.at_cell.tmp[8].a my_tree.in[3].r my_tree.at_cell.tmp[5].a my_tree.at_cell.arbs[3].ack_cell1._y my_tree.fifo_to_tree[2].fifo_element[1]._out_a_B my_tree._in[1].a my_tree.fifo_to_tree[3].fifo_element[1]._out_a_B my_tree._in[3].a my_tree.fifo_to_tree[0].fifo_element[1]._out_a_B my_tree._in[2].a my_tree.at_cell.arbs[2].ack_cell2._y my_tree.at_cell.arbs[1].ack_cell2._y my_tree._in[4].a my_tree.out.a my_tree._in[0].a my_tree.at_cell.arbs[1].ack_cell1._y my_tree.at_cell.tmp[6].a my_tree.in[2].r my_tree.in[4].r my_tree.at_cell.arbs[2].ack_cell1._y my_tree.in[0].r my_tree.fifo_to_tree[1].fifo_element[1]._out_a_B my_tree.fifo_to_tree[4].fifo_element[1]._out_a_B my_tree.at_cell.arbs[0].ack_cell1._y my_tree.at_cell.arbs[3].ack_cell2._y my_tree.at_cell.arbs[0].ack_cell2._y
217204 my_tree.in[0].r : 0
217204 my_tree.out.a : 0
217204 my_tree.in[4].r : 0
217204 my_tree.in[2].r : 0
217204 my_tree.in[1].r : 0
217204 my_tree.in[3].r : 0
217205 my_tree.at_cell.arbs[3].ack_cell2._y : 1 [by my_tree.out.a:=0]
217216 my_tree._in[4].a : 0 [by my_tree.at_cell.arbs[3].ack_cell2._y:=1]
217586 my_tree.fifo_to_tree[4].fifo_element[1]._out_a_B : 1 [by my_tree._in[4].a:=0]
217752 my_tree.at_cell.arbs[3].ack_cell1._y : 1 [by my_tree.out.a:=0]
217819 my_tree.at_cell.tmp[8].a : 0 [by my_tree.at_cell.arbs[3].ack_cell1._y:=1]
217835 my_tree.at_cell.arbs[2].ack_cell1._y : 1 [by my_tree.at_cell.tmp[8].a:=0]
220460 my_tree.at_cell.arbs[2].ack_cell2._y : 1 [by my_tree.at_cell.tmp[8].a:=0]
220988 my_tree.at_cell.tmp[6].a : 0 [by my_tree.at_cell.arbs[2].ack_cell2._y:=1]
222397 my_tree.at_cell.tmp[5].a : 0 [by my_tree.at_cell.arbs[2].ack_cell1._y:=1]
223423 my_tree.at_cell.arbs[1].ack_cell2._y : 1 [by my_tree.at_cell.tmp[6].a:=0]
223425 my_tree._in[3].a : 0 [by my_tree.at_cell.arbs[1].ack_cell2._y:=1]
235438 my_tree.at_cell.arbs[0].ack_cell1._y : 1 [by my_tree.at_cell.tmp[5].a:=0]
235441 my_tree._in[0].a : 0 [by my_tree.at_cell.arbs[0].ack_cell1._y:=1]
235470 my_tree.fifo_to_tree[0].fifo_element[1]._out_a_B : 1 [by my_tree._in[0].a:=0]
246322 my_tree.at_cell.arbs[0].ack_cell2._y : 1 [by my_tree.at_cell.tmp[5].a:=0]
246639 my_tree._in[1].a : 0 [by my_tree.at_cell.arbs[0].ack_cell2._y:=1]
247868 my_tree.at_cell.arbs[1].ack_cell1._y : 1 [by my_tree.at_cell.tmp[6].a:=0]
248021 my_tree._in[2].a : 0 [by my_tree.at_cell.arbs[1].ack_cell1._y:=1]
248065 my_tree.fifo_to_tree[2].fifo_element[1]._out_a_B : 1 [by my_tree._in[2].a:=0]
248240 my_tree.fifo_to_tree[1].fifo_element[1]._out_a_B : 1 [by my_tree._in[1].a:=0]
284383 my_tree.fifo_to_tree[3].fifo_element[1]._out_a_B : 1 [by my_tree._in[3].a:=0]
-------------------------------------------------
[0] System initialized
284383 Reset : 0
287144 my_tree._reset_B : 1 [by Reset:=0]
287145 my_tree.fifo_to_tree[3].reset_buf._y : 0 [by my_tree._reset_B:=1]
287145 my_tree.fifo_to_tree[0].reset_buf._y : 0 [by my_tree._reset_B:=1]
287166 my_tree.fifo_to_tree[1].reset_buf._y : 0 [by my_tree._reset_B:=1]
287325 my_tree.fifo_to_tree[1]._reset_BX : 1 [by my_tree.fifo_to_tree[1].reset_buf._y:=0]
287361 my_tree.fifo_to_tree[2].reset_buf._y : 0 [by my_tree._reset_B:=1]
288648 my_tree.fifo_to_tree[2]._reset_BX : 1 [by my_tree.fifo_to_tree[2].reset_buf._y:=0]
288726 my_tree.fifo_to_tree[3]._reset_BX : 1 [by my_tree.fifo_to_tree[3].reset_buf._y:=0]
288871 my_tree.fifo_to_tree[3].reset_bufarray.buf1._y : 0 [by my_tree.fifo_to_tree[3]._reset_BX:=1]
290880 my_tree.fifo_to_tree[2].reset_bufarray.buf1._y : 0 [by my_tree.fifo_to_tree[2]._reset_BX:=1]
291703 my_tree.fifo_to_tree[3]._reset_BXX[0] : 1 [by my_tree.fifo_to_tree[3].reset_bufarray.buf1._y:=0]
291704 my_tree.fifo_to_tree[3].fifo_element[0].reset_buf._y : 0 [by my_tree.fifo_to_tree[3]._reset_BXX[0]:=1]
291866 my_tree.fifo_to_tree[3].fifo_element[0]._reset_BX : 1 [by my_tree.fifo_to_tree[3].fifo_element[0].reset_buf._y:=0]
296490 my_tree.fifo_to_tree[0]._reset_BX : 1 [by my_tree.fifo_to_tree[0].reset_buf._y:=0]
297234 my_tree.fifo_to_tree[2]._reset_BXX[0] : 1 [by my_tree.fifo_to_tree[2].reset_bufarray.buf1._y:=0]
297241 my_tree.fifo_to_tree[2].fifo_element[1].reset_buf._y : 0 [by my_tree.fifo_to_tree[2]._reset_BXX[0]:=1]
297248 my_tree.fifo_to_tree[2].fifo_element[0].reset_buf._y : 0 [by my_tree.fifo_to_tree[2]._reset_BXX[0]:=1]
297401 my_tree.fifo_to_tree[2].fifo_element[1]._reset_BX : 1 [by my_tree.fifo_to_tree[2].fifo_element[1].reset_buf._y:=0]
300827 my_tree.fifo_to_tree[4].reset_buf._y : 0 [by my_tree._reset_B:=1]
300828 my_tree.fifo_to_tree[4]._reset_BX : 1 [by my_tree.fifo_to_tree[4].reset_buf._y:=0]
300829 my_tree.fifo_to_tree[4].reset_bufarray.buf1._y : 0 [by my_tree.fifo_to_tree[4]._reset_BX:=1]
300830 my_tree.fifo_to_tree[4]._reset_BXX[0] : 1 [by my_tree.fifo_to_tree[4].reset_bufarray.buf1._y:=0]
301017 my_tree.fifo_to_tree[4].fifo_element[1].reset_buf._y : 0 [by my_tree.fifo_to_tree[4]._reset_BXX[0]:=1]
301018 my_tree.fifo_to_tree[4].fifo_element[1]._reset_BX : 1 [by my_tree.fifo_to_tree[4].fifo_element[1].reset_buf._y:=0]
303073 my_tree.fifo_to_tree[4].fifo_element[0].reset_buf._y : 0 [by my_tree.fifo_to_tree[4]._reset_BXX[0]:=1]
303859 my_tree.fifo_to_tree[0].reset_bufarray.buf1._y : 0 [by my_tree.fifo_to_tree[0]._reset_BX:=1]
307001 my_tree.fifo_to_tree[1].reset_bufarray.buf1._y : 0 [by my_tree.fifo_to_tree[1]._reset_BX:=1]
307002 my_tree.fifo_to_tree[1]._reset_BXX[0] : 1 [by my_tree.fifo_to_tree[1].reset_bufarray.buf1._y:=0]
307007 my_tree.fifo_to_tree[1].fifo_element[1].reset_buf._y : 0 [by my_tree.fifo_to_tree[1]._reset_BXX[0]:=1]
307255 my_tree.fifo_to_tree[4].fifo_element[0]._reset_BX : 1 [by my_tree.fifo_to_tree[4].fifo_element[0].reset_buf._y:=0]
307855 my_tree.fifo_to_tree[1].fifo_element[0].reset_buf._y : 0 [by my_tree.fifo_to_tree[1]._reset_BXX[0]:=1]
307856 my_tree.fifo_to_tree[1].fifo_element[0]._reset_BX : 1 [by my_tree.fifo_to_tree[1].fifo_element[0].reset_buf._y:=0]
307898 my_tree.fifo_to_tree[1].fifo_element[1]._reset_BX : 1 [by my_tree.fifo_to_tree[1].fifo_element[1].reset_buf._y:=0]
318805 my_tree.fifo_to_tree[2].fifo_element[0]._reset_BX : 1 [by my_tree.fifo_to_tree[2].fifo_element[0].reset_buf._y:=0]
330987 my_tree.fifo_to_tree[3].fifo_element[1].reset_buf._y : 0 [by my_tree.fifo_to_tree[3]._reset_BXX[0]:=1]
331004 my_tree.fifo_to_tree[3].fifo_element[1]._reset_BX : 1 [by my_tree.fifo_to_tree[3].fifo_element[1].reset_buf._y:=0]
338641 my_tree.fifo_to_tree[0]._reset_BXX[0] : 1 [by my_tree.fifo_to_tree[0].reset_bufarray.buf1._y:=0]
341214 my_tree.fifo_to_tree[0].fifo_element[0].reset_buf._y : 0 [by my_tree.fifo_to_tree[0]._reset_BXX[0]:=1]
341217 my_tree.fifo_to_tree[0].fifo_element[0]._reset_BX : 1 [by my_tree.fifo_to_tree[0].fifo_element[0].reset_buf._y:=0]
347002 my_tree.fifo_to_tree[0].fifo_element[1].reset_buf._y : 0 [by my_tree.fifo_to_tree[0]._reset_BXX[0]:=1]
347943 my_tree.fifo_to_tree[0].fifo_element[1]._reset_BX : 1 [by my_tree.fifo_to_tree[0].fifo_element[1].reset_buf._y:=0]
-------------------------------------------------
[1] System reset completed
347943 my_tree.in[0].r : 1
347943 my_tree.in[4].r : 1
347943 my_tree.in[2].r : 1
347944 my_tree.fifo_to_tree[4].fifo_element[0].buf_func._y : 0 [by my_tree.in[4].r:=1]
347985 my_tree.fifo_to_tree[2].fifo_element[0].buf_func._y : 0 [by my_tree.in[2].r:=1]
350761 my_tree.fifo_to_tree[4].fifo_element[1].in.r : 1 [by my_tree.fifo_to_tree[4].fifo_element[0].buf_func._y:=0]
350856 my_tree.fifo_to_tree[4].fifo_element[1].buf_func._y : 0 [by my_tree.fifo_to_tree[4].fifo_element[1].in.r:=1]
350864 my_tree._in[4].r : 1 [by my_tree.fifo_to_tree[4].fifo_element[1].buf_func._y:=0]
350898 my_tree.at_cell.arbs[3].arbiter._y2 : 0 [by my_tree._in[4].r:=1]
351096 my_tree.fifo_to_tree[4].fifo_element[0].inack_ctl._y : 0 [by my_tree.fifo_to_tree[4].fifo_element[1].in.r:=1]
351100 my_tree.in[4].a : 1 [by my_tree.fifo_to_tree[4].fifo_element[0].inack_ctl._y:=0]
351816 my_tree.at_cell.arbs[3]._y2_arb : 1 [by my_tree.at_cell.arbs[3].arbiter._y2:=0]
354214 my_tree.at_cell.arbs[3].or_cell._y : 0 [by my_tree.at_cell.arbs[3]._y2_arb:=1]
357429 my_tree.out.r : 1 [by my_tree.at_cell.arbs[3].or_cell._y:=0]
361718 my_tree.fifo_to_tree[2].fifo_element[1].in.r : 1 [by my_tree.fifo_to_tree[2].fifo_element[0].buf_func._y:=0]
361766 my_tree.fifo_to_tree[2].fifo_element[0].inack_ctl._y : 0 [by my_tree.fifo_to_tree[2].fifo_element[1].in.r:=1]
361769 my_tree.in[2].a : 1 [by my_tree.fifo_to_tree[2].fifo_element[0].inack_ctl._y:=0]
361947 my_tree.fifo_to_tree[2].fifo_element[0]._en : 0 [by my_tree.in[2].a:=1]
364751 my_tree.fifo_to_tree[4].fifo_element[1].inack_ctl._y : 0 [by my_tree._in[4].r:=1]
385728 my_tree.fifo_to_tree[4].fifo_element[1].in.a : 1 [by my_tree.fifo_to_tree[4].fifo_element[1].inack_ctl._y:=0]
391679 my_tree.fifo_to_tree[4].fifo_element[0]._out_a_B : 0 [by my_tree.fifo_to_tree[4].fifo_element[1].in.a:=1]
397478 my_tree.fifo_to_tree[4].fifo_element[0]._en : 0 [by my_tree.in[4].a:=1]
397627 my_tree.fifo_to_tree[4].fifo_element[1]._en : 0 [by my_tree.fifo_to_tree[4].fifo_element[1].in.a:=1]
406905 my_tree.fifo_to_tree[0].fifo_element[0].buf_func._y : 0 [by my_tree.in[0].r:=1]
407732 my_tree.fifo_to_tree[0].fifo_element[1].in.r : 1 [by my_tree.fifo_to_tree[0].fifo_element[0].buf_func._y:=0]
407905 my_tree.fifo_to_tree[0].fifo_element[1].buf_func._y : 0 [by my_tree.fifo_to_tree[0].fifo_element[1].in.r:=1]
407906 my_tree._in[0].r : 1 [by my_tree.fifo_to_tree[0].fifo_element[1].buf_func._y:=0]
407910 my_tree.fifo_to_tree[0].fifo_element[1].inack_ctl._y : 0 [by my_tree._in[0].r:=1]
407916 my_tree.fifo_to_tree[0].fifo_element[0].inack_ctl._y : 0 [by my_tree.fifo_to_tree[0].fifo_element[1].in.r:=1]
407979 my_tree.at_cell.arbs[0].arbiter._y1 : 0 [by my_tree._in[0].r:=1]
408012 my_tree.in[0].a : 1 [by my_tree.fifo_to_tree[0].fifo_element[0].inack_ctl._y:=0]
408013 my_tree.fifo_to_tree[0].fifo_element[0]._en : 0 [by my_tree.in[0].a:=1]
408115 my_tree.at_cell.arbs[0]._y1_arb : 1 [by my_tree.at_cell.arbs[0].arbiter._y1:=0]
408837 my_tree.fifo_to_tree[2].fifo_element[1].buf_func._y : 0 [by my_tree.fifo_to_tree[2].fifo_element[1].in.r:=1]
409078 my_tree._in[2].r : 1 [by my_tree.fifo_to_tree[2].fifo_element[1].buf_func._y:=0]
409090 my_tree.fifo_to_tree[2].fifo_element[1].inack_ctl._y : 0 [by my_tree._in[2].r:=1]
412990 my_tree.fifo_to_tree[2].fifo_element[1].in.a : 1 [by my_tree.fifo_to_tree[2].fifo_element[1].inack_ctl._y:=0]
412991 my_tree.fifo_to_tree[2].fifo_element[0]._out_a_B : 0 [by my_tree.fifo_to_tree[2].fifo_element[1].in.a:=1]
413037 my_tree.at_cell.arbs[1].arbiter._y1 : 0 [by my_tree._in[2].r:=1]
413047 my_tree.fifo_to_tree[2].fifo_element[0].buf_func._y : 1 [by my_tree.fifo_to_tree[2].fifo_element[0]._out_a_B:=0]
413048 my_tree.fifo_to_tree[2].fifo_element[1].in.r : 0 [by my_tree.fifo_to_tree[2].fifo_element[0].buf_func._y:=1]
414019 my_tree.fifo_to_tree[2].fifo_element[1]._en : 0 [by my_tree.fifo_to_tree[2].fifo_element[1].in.a:=1]
414056 my_tree.fifo_to_tree[2].fifo_element[1].inack_ctl._y : 1 [by my_tree.fifo_to_tree[2].fifo_element[1]._en:=0]
427161 my_tree.at_cell.arbs[0].or_cell._y : 0 [by my_tree.at_cell.arbs[0]._y1_arb:=1]
427162 my_tree.at_cell.tmp[5].r : 1 [by my_tree.at_cell.arbs[0].or_cell._y:=0]
430726 my_tree.at_cell.arbs[2].arbiter._y1 : 0 [by my_tree.at_cell.tmp[5].r:=1]
432418 my_tree.at_cell.arbs[2]._y1_arb : 1 [by my_tree.at_cell.arbs[2].arbiter._y1:=0]
432431 my_tree.at_cell.arbs[2].or_cell._y : 0 [by my_tree.at_cell.arbs[2]._y1_arb:=1]
436963 my_tree.fifo_to_tree[4].fifo_element[0].buf_func._y : 1 [by my_tree.fifo_to_tree[4].fifo_element[0]._en:=0]
437320 my_tree.fifo_to_tree[4].fifo_element[1].in.r : 0 [by my_tree.fifo_to_tree[4].fifo_element[0].buf_func._y:=1]
437345 my_tree.fifo_to_tree[4].fifo_element[1].inack_ctl._y : 1 [by my_tree.fifo_to_tree[4].fifo_element[1].in.r:=0]
437366 my_tree.fifo_to_tree[4].fifo_element[1].in.a : 0 [by my_tree.fifo_to_tree[4].fifo_element[1].inack_ctl._y:=1]
437367 my_tree.fifo_to_tree[4].fifo_element[0]._out_a_B : 1 [by my_tree.fifo_to_tree[4].fifo_element[1].in.a:=0]
437431 my_tree.fifo_to_tree[2].fifo_element[1].in.a : 0 [by my_tree.fifo_to_tree[2].fifo_element[1].inack_ctl._y:=1]
445198 my_tree.fifo_to_tree[0].fifo_element[1].in.a : 1 [by my_tree.fifo_to_tree[0].fifo_element[1].inack_ctl._y:=0]
445199 my_tree.fifo_to_tree[0].fifo_element[1]._en : 0 [by my_tree.fifo_to_tree[0].fifo_element[1].in.a:=1]
445199 my_tree.fifo_to_tree[0].fifo_element[0]._out_a_B : 0 [by my_tree.fifo_to_tree[0].fifo_element[1].in.a:=1]
445360 my_tree.fifo_to_tree[0].fifo_element[0].buf_func._y : 1 [by my_tree.fifo_to_tree[0].fifo_element[0]._out_a_B:=0]
446397 my_tree.fifo_to_tree[0].fifo_element[1].in.r : 0 [by my_tree.fifo_to_tree[0].fifo_element[0].buf_func._y:=1]
446402 my_tree.fifo_to_tree[0].fifo_element[1].inack_ctl._y : 1 [by my_tree.fifo_to_tree[0].fifo_element[1].in.r:=0]
446983 my_tree.fifo_to_tree[0].fifo_element[1].in.a : 0 [by my_tree.fifo_to_tree[0].fifo_element[1].inack_ctl._y:=1]
447079 my_tree.fifo_to_tree[2].fifo_element[0]._out_a_B : 1 [by my_tree.fifo_to_tree[2].fifo_element[1].in.a:=0]
447391 my_tree.fifo_to_tree[0].fifo_element[0]._out_a_B : 1 [by my_tree.fifo_to_tree[0].fifo_element[1].in.a:=0]
449415 my_tree.at_cell.tmp[8].r : 1 [by my_tree.at_cell.arbs[2].or_cell._y:=0]
458043 my_tree.at_cell.arbs[1]._y1_arb : 1 [by my_tree.at_cell.arbs[1].arbiter._y1:=0]
458054 my_tree.at_cell.arbs[1].or_cell._y : 0 [by my_tree.at_cell.arbs[1]._y1_arb:=1]
459101 my_tree.at_cell.tmp[6].r : 1 [by my_tree.at_cell.arbs[1].or_cell._y:=0]
459101 my_tree.out.a : 1
459115 my_tree.at_cell.arbs[3].ack_cell2._y : 0 [by my_tree.out.a:=1]
459133 my_tree._in[4].a : 1 [by my_tree.at_cell.arbs[3].ack_cell2._y:=0]
459137 my_tree.fifo_to_tree[4].fifo_element[1]._out_a_B : 0 [by my_tree._in[4].a:=1]
459241 my_tree.fifo_to_tree[4].fifo_element[1].buf_func._y : 1 [by my_tree.fifo_to_tree[4].fifo_element[1]._out_a_B:=0]
490685 my_tree._in[4].r : 0 [by my_tree.fifo_to_tree[4].fifo_element[1].buf_func._y:=1]
491889 my_tree.at_cell.arbs[3].arbiter._y2 : 1 [by my_tree._in[4].r:=0]
492117 my_tree.at_cell.arbs[3].arbiter._y1 : 0 [by my_tree.at_cell.arbs[3].arbiter._y2:=1]
492732 my_tree.at_cell.arbs[3]._y2_arb : 0 [by my_tree.at_cell.arbs[3].arbiter._y2:=1]
494191 my_tree.at_cell.arbs[3].or_cell._y : 1 [by my_tree.at_cell.arbs[3]._y2_arb:=0]
494261 my_tree.out.r : 0 [by my_tree.at_cell.arbs[3].or_cell._y:=1]
499140 my_tree.fifo_to_tree[4].fifo_element[1]._en : 1 [by my_tree._in[4].r:=0]
499140 my_tree.out.a : 0
549562 my_tree.at_cell.arbs[3].ack_cell2._y : 1 [by my_tree.out.a:=0]
549573 my_tree._in[4].a : 0 [by my_tree.at_cell.arbs[3].ack_cell2._y:=1]
549576 my_tree.at_cell.arbs[3]._y1_arb : 1 [by my_tree._in[4].a:=0]
549627 my_tree.fifo_to_tree[4].fifo_element[1]._out_a_B : 1 [by my_tree._in[4].a:=0]
550724 my_tree.at_cell.arbs[3].or_cell._y : 0 [by my_tree.at_cell.arbs[3]._y1_arb:=1]
551885 my_tree.out.r : 1 [by my_tree.at_cell.arbs[3].or_cell._y:=0]
551885 my_tree.out.a : 1
560537 my_tree.at_cell.arbs[3].ack_cell1._y : 0 [by my_tree.out.a:=1]
560618 my_tree.at_cell.tmp[8].a : 1 [by my_tree.at_cell.arbs[3].ack_cell1._y:=0]
571695 my_tree.at_cell.arbs[2].ack_cell1._y : 0 [by my_tree.at_cell.tmp[8].a:=1]
589678 my_tree.at_cell.tmp[5].a : 1 [by my_tree.at_cell.arbs[2].ack_cell1._y:=0]
589770 my_tree.at_cell.arbs[0].ack_cell1._y : 0 [by my_tree.at_cell.tmp[5].a:=1]
598081 my_tree._in[0].a : 1 [by my_tree.at_cell.arbs[0].ack_cell1._y:=0]
599825 my_tree.fifo_to_tree[0].fifo_element[1]._out_a_B : 0 [by my_tree._in[0].a:=1]
600438 my_tree.fifo_to_tree[0].fifo_element[1].buf_func._y : 1 [by my_tree.fifo_to_tree[0].fifo_element[1]._out_a_B:=0]
614460 my_tree._in[0].r : 0 [by my_tree.fifo_to_tree[0].fifo_element[1].buf_func._y:=1]
614505 my_tree.at_cell.arbs[0].arbiter._y1 : 1 [by my_tree._in[0].r:=0]
615457 my_tree.fifo_to_tree[0].fifo_element[1]._en : 1 [by my_tree._in[0].r:=0]
616154 my_tree.at_cell.arbs[0]._y1_arb : 0 [by my_tree.at_cell.arbs[0].arbiter._y1:=1]
616679 my_tree.at_cell.arbs[0].or_cell._y : 1 [by my_tree.at_cell.arbs[0]._y1_arb:=0]
617579 my_tree.at_cell.tmp[5].r : 0 [by my_tree.at_cell.arbs[0].or_cell._y:=1]
617631 my_tree.at_cell.arbs[2].arbiter._y1 : 1 [by my_tree.at_cell.tmp[5].r:=0]
617638 my_tree.at_cell.arbs[2].arbiter._y2 : 0 [by my_tree.at_cell.arbs[2].arbiter._y1:=1]
633243 my_tree.at_cell.arbs[2]._y1_arb : 0 [by my_tree.at_cell.arbs[2].arbiter._y1:=1]
639710 my_tree.at_cell.arbs[2].or_cell._y : 1 [by my_tree.at_cell.arbs[2]._y1_arb:=0]
639712 my_tree.at_cell.tmp[8].r : 0 [by my_tree.at_cell.arbs[2].or_cell._y:=1]
640066 my_tree.at_cell.arbs[3].arbiter._y1 : 1 [by my_tree.at_cell.tmp[8].r:=0]
640199 my_tree.at_cell.arbs[3]._y1_arb : 0 [by my_tree.at_cell.arbs[3].arbiter._y1:=1]
640200 my_tree.at_cell.arbs[3].or_cell._y : 1 [by my_tree.at_cell.arbs[3]._y1_arb:=0]
640204 my_tree.out.r : 0 [by my_tree.at_cell.arbs[3].or_cell._y:=1]
640204 my_tree.out.a : 0
640750 my_tree.at_cell.arbs[3].ack_cell1._y : 1 [by my_tree.out.a:=0]
686313 my_tree.at_cell.tmp[8].a : 0 [by my_tree.at_cell.arbs[3].ack_cell1._y:=1]
686314 my_tree.at_cell.arbs[2].ack_cell1._y : 1 [by my_tree.at_cell.tmp[8].a:=0]
698692 my_tree.at_cell.tmp[5].a : 0 [by my_tree.at_cell.arbs[2].ack_cell1._y:=1]
698771 my_tree.at_cell.arbs[2]._y2_arb : 1 [by my_tree.at_cell.tmp[5].a:=0]
698859 my_tree.at_cell.arbs[2].or_cell._y : 0 [by my_tree.at_cell.arbs[2]._y2_arb:=1]
701125 my_tree.at_cell.arbs[0].ack_cell1._y : 1 [by my_tree.at_cell.tmp[5].a:=0]
706641 my_tree.at_cell.tmp[8].r : 1 [by my_tree.at_cell.arbs[2].or_cell._y:=0]
706700 my_tree.at_cell.arbs[3].arbiter._y1 : 0 [by my_tree.at_cell.tmp[8].r:=1]
706730 my_tree.at_cell.arbs[3]._y1_arb : 1 [by my_tree.at_cell.arbs[3].arbiter._y1:=0]
708197 my_tree.at_cell.arbs[3].or_cell._y : 0 [by my_tree.at_cell.arbs[3]._y1_arb:=1]
729452 my_tree._in[0].a : 0 [by my_tree.at_cell.arbs[0].ack_cell1._y:=1]
748836 my_tree.fifo_to_tree[0].fifo_element[1]._out_a_B : 1 [by my_tree._in[0].a:=0]
767701 my_tree.out.r : 1 [by my_tree.at_cell.arbs[3].or_cell._y:=0]
767701 my_tree.out.a : 1
768386 my_tree.at_cell.arbs[3].ack_cell1._y : 0 [by my_tree.out.a:=1]
785101 my_tree.at_cell.tmp[8].a : 1 [by my_tree.at_cell.arbs[3].ack_cell1._y:=0]
785228 my_tree.at_cell.arbs[2].ack_cell2._y : 0 [by my_tree.at_cell.tmp[8].a:=1]
785397 my_tree.at_cell.tmp[6].a : 1 [by my_tree.at_cell.arbs[2].ack_cell2._y:=0]
785440 my_tree.at_cell.arbs[1].ack_cell1._y : 0 [by my_tree.at_cell.tmp[6].a:=1]
785452 my_tree._in[2].a : 1 [by my_tree.at_cell.arbs[1].ack_cell1._y:=0]
786731 my_tree.fifo_to_tree[2].fifo_element[1]._out_a_B : 0 [by my_tree._in[2].a:=1]
786964 my_tree.fifo_to_tree[2].fifo_element[1].buf_func._y : 1 [by my_tree.fifo_to_tree[2].fifo_element[1]._out_a_B:=0]
786967 my_tree._in[2].r : 0 [by my_tree.fifo_to_tree[2].fifo_element[1].buf_func._y:=1]
786968 my_tree.fifo_to_tree[2].fifo_element[1]._en : 1 [by my_tree._in[2].r:=0]
787005 my_tree.at_cell.arbs[1].arbiter._y1 : 1 [by my_tree._in[2].r:=0]
799757 my_tree.at_cell.arbs[1]._y1_arb : 0 [by my_tree.at_cell.arbs[1].arbiter._y1:=1]
799849 my_tree.at_cell.arbs[1].or_cell._y : 1 [by my_tree.at_cell.arbs[1]._y1_arb:=0]
802576 my_tree.at_cell.tmp[6].r : 0 [by my_tree.at_cell.arbs[1].or_cell._y:=1]
802578 my_tree.at_cell.arbs[2].arbiter._y2 : 1 [by my_tree.at_cell.tmp[6].r:=0]
802579 my_tree.at_cell.arbs[2]._y2_arb : 0 [by my_tree.at_cell.arbs[2].arbiter._y2:=1]
804080 my_tree.at_cell.arbs[2].or_cell._y : 1 [by my_tree.at_cell.arbs[2]._y2_arb:=0]
804082 my_tree.at_cell.tmp[8].r : 0 [by my_tree.at_cell.arbs[2].or_cell._y:=1]
804100 my_tree.at_cell.arbs[3].arbiter._y1 : 1 [by my_tree.at_cell.tmp[8].r:=0]
804219 my_tree.at_cell.arbs[3]._y1_arb : 0 [by my_tree.at_cell.arbs[3].arbiter._y1:=1]
809939 my_tree.at_cell.arbs[3].or_cell._y : 1 [by my_tree.at_cell.arbs[3]._y1_arb:=0]
809947 my_tree.out.r : 0 [by my_tree.at_cell.arbs[3].or_cell._y:=1]
809947 my_tree.out.a : 0
810001 my_tree.at_cell.arbs[3].ack_cell1._y : 1 [by my_tree.out.a:=0]
860539 my_tree.at_cell.tmp[8].a : 0 [by my_tree.at_cell.arbs[3].ack_cell1._y:=1]
860544 my_tree.at_cell.arbs[2].ack_cell2._y : 1 [by my_tree.at_cell.tmp[8].a:=0]
861611 my_tree.at_cell.tmp[6].a : 0 [by my_tree.at_cell.arbs[2].ack_cell2._y:=1]
861612 my_tree.at_cell.arbs[1].ack_cell1._y : 1 [by my_tree.at_cell.tmp[6].a:=0]
861750 my_tree._in[2].a : 0 [by my_tree.at_cell.arbs[1].ack_cell1._y:=1]
861751 my_tree.fifo_to_tree[2].fifo_element[1]._out_a_B : 1 [by my_tree._in[2].a:=0]
-------------------------------------------------
[3] Sent three inputs, received 3 outputs

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test/unit_tests/arbiter_tree_test/run/test.prs
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64
test/unit_tests/arbiter_tree_test/test.act
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@@ -1,64 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/coders.act";
import globals;
open tmpl::dataflow_neuro;
defproc arbiter_treee (a1of1 in[5]; a1of1 out)
{
//Low active Reset
bool _reset_B;
prs {
Reset => _reset_B-
}
a1of1 _in[5];
power _supply;
_supply.vdd = Vdd;
_supply.vss = GND;
fifo_t<2> fifo_to_tree[5];
(i:5:
fifo_to_tree[i].in = in[i];
fifo_to_tree[i].out = _in[i];
fifo_to_tree[i].supply = _supply;
fifo_to_tree[i].reset_B = _reset_B;
)
arbtree<5> at_cell(.in=_in, .out = out);
at_cell.supply = _supply;
}
arbiter_treee my_tree;

63
test/unit_tests/arbiter_tree_test/test.prsim
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@@ -1,63 +0,0 @@
watchall
set my_tree.in[0].r 0
set my_tree.in[1].r 0
set my_tree.in[2].r 0
set my_tree.in[3].r 0
set my_tree.in[4].r 0
set my_tree.out.a 0
cycle
assert my_tree.in[0].a 0
assert my_tree.in[1].a 0
assert my_tree.in[2].a 0
assert my_tree.in[3].a 0
assert my_tree.in[4].a 0
assert my_tree.out.r 0
system "echo '-------------------------------------------------'"
system "echo '[0] System initialized'"
set Reset 0
cycle
system "echo '-------------------------------------------------'"
system "echo '[1] System reset completed'"
set my_tree.in[0].r 1
set my_tree.in[2].r 1
set my_tree.in[4].r 1
cycle
assert my_tree.out.r 1
set my_tree.out.a 1
cycle
assert my_tree.out.r 0
set my_tree.out.a 0
cycle
assert my_tree.out.r 1
set my_tree.out.a 1
cycle
assert my_tree.out.r 0
set my_tree.out.a 0
cycle
assert my_tree.out.r 1
set my_tree.out.a 1
cycle
assert my_tree.out.r 0
set my_tree.out.a 0
cycle
system "echo '-------------------------------------------------'"
system "echo '[3] Sent three inputs, received 3 outputs'"

60
test/unit_tests/async_instantiate/test.act
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@@ -1,60 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_async.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/cell_lib_async.act";
open tmpl::dataflow_neuro;
A_1C1P2N_RB_X1 cell1;
A_1C1P2N_R_X1 cell2;
A_1C1P_1N_X1 cell3;
A_1C1P_B cell4;
A_1C1P_X1 cell5;
A_1C2P1N_X1 cell6;
A_1C2P_B_X1 cell7;
A_1C2P_X1 cell8;
A_1C3P2P2N_R_X1 cell9;
A_2C2N2N_RB_X1 cell10;
A_2C2N2N_RB_X2 cell11;
A_2C2N2N_RB_X4 cell12;
A_2C2N2N_R_X1 cell13;
A_2C2N_RB_X2 cell14;
A_2C2N_RB_X4 cell15;
A_2C2N_R_X1 cell16;
A_2C_B_X1 cell17;
A_2C_RB_X1 cell18;
A_2C_R_X1 cell19;
A_2C_X1 cell20;
A_3C_RB_X1 cell21;
A_3C_RB_X2 cell22;
A_3C_RB_X4 cell23;
A_3C_R_X1 cell24;
A_3C_X1 cell25;
A_4C_RB_X1 cell26;
A_4C_RB_X2 cell27;
A_4C_RB_X4 cell28;
A_4C_R_X1 cell29;
A_4P1N1N_B_X1 cell30;
A_4P1N1N_X1 cell31;

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test/unit_tests/async_instantiate/test.prsim
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test/unit_tests/bd-fifo-register-fifo-bd/test.act
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@@ -1,64 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/registers.act";
import "../../dataflow_neuro/interfaces.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc fifo_reg_fifo_3x5x8 (bd<3+5+1> in; Mx1of2<5> data[8]; bd<8> out; bool? dly_cfg[4]; bool? dly_cfg2[2]){
bool _reset_B;
prs {
Reset => _reset_B-
}
power supply;
supply.vdd = Vdd;
supply.vss = GND;
bd2qdi<9,4,2> _bd2qdi(.in = in, .dly_cfg = dly_cfg, .dly_cfg2 = dly_cfg2, .reset_B = _reset_B, .supply = supply);
fifo<9,5> fifo_pre(.in = _bd2qdi.out, .reset_B = _reset_B, .supply = supply);
// Make a register array with 3 bit address (-> 8 registers),
// each register holding 5 bits.
register_wr_array<3,5,8> reg(.in = fifo_pre.out, .data = data,
.reset_B = _reset_B, .supply = supply);
fifo<8,5> fifo_post(.in = reg.out, .reset_B = _reset_B, .supply = supply);
qdi2bd<8,4> _qdi2bd(.in = fifo_post.out, .out = out, .dly_cfg = dly_cfg, .reset_B = _reset_B, .supply = supply);
}
// fifo_decoder_neurons_encoder_fifo e;
fifo_reg_fifo_3x5x8 b;

78
test/unit_tests/bd-fifo-register-fifo-bd/test.prsim
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@@ -1,78 +0,0 @@
watchall
set-bd-channel-neutral "b.in" 9
# set b.in.r 0
set b.out.a 0
set b.dly_cfg[0] 1
set b.dly_cfg[1] 1
set b.dly_cfg[2] 1
set b.dly_cfg[3] 1
set b.dly_cfg2[0] 1
set b.dly_cfg2[1] 1
cycle
mode run
system "echo '[] Set reset 0'"
status X
set Reset 0
cycle
assert b.in.a 0
assert-bd-channel-neutral "b.out" 8
system "echo '[] Sending packet write 0s to reg0'"
set-bd-data-valid "b.in" 9 256
cycle
set b.in.r 1
cycle
assert b.in.a 1
# assert b.in.v 1
assert-var-int "b.data[0]" 5 0
system "echo '[] Removing input'"
set-bd-channel-neutral "b.in" 9
cycle
assert b.in.a 0
# assert b.in.v 0
assert-var-int "b.data[0]" 5 0
system "echo '[] Sending packet write 01100=12 to reg0'"
set-bd-data-valid "b.in" 9 352
cycle
set b.in.r 1
cycle
assert b.in.a 1
# assert b.in.v 1
assert-var-int "b.data[0]" 5 12
system "echo '[] Removing input'"
set-bd-channel-neutral "b.in" 9
cycle
assert b.in.a 0
# assert b.in.v 0
assert-var-int "b.data[0]" 5 12
system "echo '[] Reading register 0'"
set-bd-data-valid "b.in" 9 0
cycle
set b.in.r 1
cycle
assert-bd-channel-valid "b.out" 8 96
assert b.out.r 1
# assert b.in.v 1
assert b.in.a 1
set b.out.a 1
cycle
assert-bd-channel-neutral "b.out" 8
assert b.in.a 1
system "echo '[] Removing input'"
set-bd-channel-neutral "b.in" 9
cycle
assert b.in.a 0
set b.out.a 0
cycle

45
test/unit_tests/bd2qdi_5/test.act
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@@ -1,45 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/interfaces.act";
import globals;
open tmpl::dataflow_neuro;
defproc bd2qdi_5(bd<5> in; avMx1of2<5> out; bool? dly_cfg[4]; bool? dly_cfg2[2])
{
bool _reset_B;
prs {
Reset => _reset_B-
}
bd2qdi<5,4,2> b(.in = in, .out = out, .reset_B = _reset_B, .dly_cfg = dly_cfg, .dly_cfg2 = dly_cfg2);
b.supply.vdd = Vdd;
b.supply.vss = GND;
}
bd2qdi_5 b;

140
test/unit_tests/bd2qdi_5/test.prsim
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@@ -1,140 +0,0 @@
watchall
set b.out.a 0
set b.out.v 0
set b.in.r 0
set b.dly_cfg[0] 1
set b.dly_cfg[1] 1
set b.dly_cfg[2] 1
set b.dly_cfg[3] 1
set b.dly_cfg2[0] 1
set b.dly_cfg2[1] 1
set b.in.d[0] 1
set b.in.d[1] 0
set b.in.d[2] 0
set b.in.d[3] 1
set b.in.d[4] 0
set Reset 0
cycle
system "echo '[] set Reset 1'"
set Reset 1
cycle
system "echo '[] set Reset 0'"
set Reset 0
mode run
cycle
status X
assert-qdi-channel-neutral "b.out" 5
assert b.in.a 0
system "echo '[] Reset finished, setting data'"
set b.in.d[0] 0
set b.in.d[1] 1
set b.in.d[2] 1
set b.in.d[3] 0
set b.in.d[4] 1
cycle
system "echo '[] Reset finished, setting req 1'"
set b.in.r 1
cycle
assert-qdi-channel-valid "b.out" 5 22
system "echo '[] Receiving val out'"
set b.out.v 1
# set b.out.a 1
cycle
assert-qdi-channel-valid "b.out" 5 22
assert b.in.a 1
system "echo '[] Changing some input data'"
set b.in.d[0] 1
set b.in.d[1] 1
set b.in.d[2] 1
cycle
system "echo '[] Removing req'"
set b.in.r 0
system "echo '[] Changing more data'"
set b.in.d[3] 0
set b.in.d[4] 0
cycle
assert-qdi-channel-valid "b.out" 5 22
system "echo '[] Receiving ack out'"
set b.out.a 1
cycle
assert-qdi-channel-neutral "b.out" 5
set b.out.v 0
cycle
assert b.in.a 0
system "echo '[] Set ack out 0'"
set b.out.a 0
cycle
assert-qdi-channel-neutral "b.out" 5
assert b.in.a 0
system "echo '[] Again!!! setting data'"
set b.in.d[0] 0
set b.in.d[1] 0
set b.in.d[2] 0
set b.in.d[3] 0
set b.in.d[4] 0
cycle
system "echo '[] Again!!! setting req 1'"
set b.in.r 1
cycle
assert-qdi-channel-valid "b.out" 5 0
system "echo '[] Receiving val out'"
set b.out.v 1
# set b.out.a 1
cycle
assert-qdi-channel-valid "b.out" 5 0
assert b.in.a 1
system "echo '[] Changing some input data'"
set b.in.d[0] 1
set b.in.d[1] 1
set b.in.d[2] 1
cycle
system "echo '[] Removing req'"
set b.in.r 0
system "echo '[] Changing more data'"
set b.in.d[3] 0
set b.in.d[4] 0
cycle
assert-qdi-channel-valid "b.out" 5 0
system "echo '[] Receiving ack out'"
set b.out.a 1
cycle
assert-qdi-channel-neutral "b.out" 5
set b.out.v 0
cycle
assert b.in.a 0
system "echo '[] Set ack out 0'"
set b.out.a 0
cycle
assert-qdi-channel-neutral "b.out" 5
assert b.in.a 0

685
test/unit_tests/buf_15.v
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//
// Verilog module for: BUF_X6<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X6(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
reg _y;
// --- instances
endmodule
//
// Verilog module for: sigbuf<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4(in, \out[0] );
input in;
output \out[0] ;
// -- signals ---
wire in;
reg \out[0] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X6 \buf6 (.y(\out[0] ), .a(in));
endmodule
//
// Verilog module for: A_3C_RB_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4(y, c1, c2, c3, pr_B, sr_B);
output y;
input c1;
input c2;
input c3;
input pr_B;
input sr_B;
// -- signals ---
wire sr_B;
wire pr_B;
wire c3;
wire c1;
reg _y;
reg y;
wire c2;
// --- instances
endmodule
//
// Verilog module for: BUF_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X4(y, a);
output y;
input a;
// -- signals ---
reg _y;
wire a;
reg y;
// --- instances
endmodule
//
// Verilog module for: INV_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0INV__X1(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
// --- instances
endmodule
//
// Verilog module for: A_2C_B_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1(y, c1, c2);
output y;
input c1;
input c2;
// -- signals ---
reg y;
reg _y;
wire c2;
wire c1;
// --- instances
endmodule
//
// Verilog module for: A_3C_B_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1(y, c1, c2, c3);
output y;
input c1;
input c2;
input c3;
// -- signals ---
reg _y;
reg y;
wire c3;
wire c1;
wire c2;
// --- instances
endmodule
//
// Verilog module for: ctree<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4(\in[0] , \in[1] , \in[2] , \in[3] , \in[4] , \in[5] , \in[6] , \in[7] , \in[8] , \in[9] , \in[10] , \in[11] , \in[12] , \in[13] , \in[14] , out);
input \in[0] ;
input \in[1] ;
input \in[2] ;
input \in[3] ;
input \in[4] ;
input \in[5] ;
input \in[6] ;
input \in[7] ;
input \in[8] ;
input \in[9] ;
input \in[10] ;
input \in[11] ;
input \in[12] ;
input \in[13] ;
input \in[14] ;
output out;
// -- signals ---
wire \in[4] ;
wire \in[11] ;
wire \in[12] ;
reg \tmp[21] ;
wire \in[3] ;
reg out;
reg \tmp[23] ;
wire \in[6] ;
wire \in[0] ;
reg \tmp[18] ;
wire \in[10] ;
reg \tmp[15] ;
reg \tmp[16] ;
wire \in[13] ;
wire \in[1] ;
wire \in[9] ;
wire \in[2] ;
wire \in[5] ;
reg \tmp[24] ;
wire \in[14] ;
reg \tmp[19] ;
wire \in[7] ;
reg \tmp[22] ;
reg \tmp[20] ;
wire \in[8] ;
reg \tmp[17] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[0] (.y(\tmp[15] ), .c1(\in[0] ), .c2(\in[1] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[1] (.y(\tmp[16] ), .c1(\in[2] ), .c2(\in[3] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[2] (.y(\tmp[17] ), .c1(\in[4] ), .c2(\in[5] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[3] (.y(\tmp[18] ), .c1(\in[6] ), .c2(\in[7] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[4] (.y(\tmp[19] ), .c1(\in[8] ), .c2(\in[9] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[5] (.y(\tmp[20] ), .c1(\in[10] ), .c2(\in[11] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[6] (.y(\tmp[22] ), .c1(\tmp[15] ), .c2(\tmp[16] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[7] (.y(\tmp[23] ), .c1(\tmp[17] ), .c2(\tmp[18] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[0] (.y(\tmp[21] ), .c1(\in[12] ), .c2(\in[13] ), .c3(\in[14] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[1] (.y(\tmp[24] ), .c1(\tmp[19] ), .c2(\tmp[20] ), .c3(\tmp[21] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[2] (.y(out), .c1(\tmp[22] ), .c2(\tmp[23] ), .c3(\tmp[24] ));
endmodule
//
// Verilog module for: OR2_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0OR2__X1(y, a, b);
output y;
input a;
input b;
// -- signals ---
reg y;
wire a;
reg _y;
wire b;
// --- instances
endmodule
//
// Verilog module for: vtree<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4(\in.d[0].d[0] , \in.d[0].d[1] , \in.d[1].d[0] , \in.d[1].d[1] , \in.d[2].d[0] , \in.d[2].d[1] , \in.d[3].d[0] , \in.d[3].d[1] , \in.d[4].d[0] , \in.d[4].d[1] , \in.d[5].d[0] , \in.d[5].d[1] , \in.d[6].d[0] , \in.d[6].d[1] , \in.d[7].d[0] , \in.d[7].d[1] , \in.d[8].d[0] , \in.d[8].d[1] , \in.d[9].d[0] , \in.d[9].d[1] , \in.d[10].d[0] , \in.d[10].d[1] , \in.d[11].d[0] , \in.d[11].d[1] , \in.d[12].d[0] , \in.d[12].d[1] , \in.d[13].d[0] , \in.d[13].d[1] , \in.d[14].d[0] , \in.d[14].d[1] , out);
input \in.d[0].d[0] ;
input \in.d[0].d[1] ;
input \in.d[1].d[0] ;
input \in.d[1].d[1] ;
input \in.d[2].d[0] ;
input \in.d[2].d[1] ;
input \in.d[3].d[0] ;
input \in.d[3].d[1] ;
input \in.d[4].d[0] ;
input \in.d[4].d[1] ;
input \in.d[5].d[0] ;
input \in.d[5].d[1] ;
input \in.d[6].d[0] ;
input \in.d[6].d[1] ;
input \in.d[7].d[0] ;
input \in.d[7].d[1] ;
input \in.d[8].d[0] ;
input \in.d[8].d[1] ;
input \in.d[9].d[0] ;
input \in.d[9].d[1] ;
input \in.d[10].d[0] ;
input \in.d[10].d[1] ;
input \in.d[11].d[0] ;
input \in.d[11].d[1] ;
input \in.d[12].d[0] ;
input \in.d[12].d[1] ;
input \in.d[13].d[0] ;
input \in.d[13].d[1] ;
input \in.d[14].d[0] ;
input \in.d[14].d[1] ;
output out;
// -- signals ---
reg \ct.in[14] ;
reg \ct.in[13] ;
wire \in.d[7].d[0] ;
wire \in.d[1].d[0] ;
wire \in.d[0].d[0] ;
reg \ct.in[4] ;
reg out;
wire \in.d[10].d[0] ;
wire \in.d[4].d[1] ;
reg \ct.in[3] ;
wire \in.d[9].d[1] ;
wire \in.d[1].d[1] ;
wire \in.d[2].d[0] ;
wire \in.d[10].d[1] ;
reg \ct.in[8] ;
wire \in.d[12].d[0] ;
wire \in.d[5].d[0] ;
wire \in.d[4].d[0] ;
reg \ct.in[10] ;
reg \ct.in[0] ;
wire \in.d[11].d[0] ;
wire \in.d[7].d[1] ;
wire \in.d[3].d[1] ;
reg \ct.in[11] ;
reg \ct.in[2] ;
reg \ct.in[9] ;
wire \in.d[13].d[0] ;
wire \in.d[14].d[1] ;
wire \in.d[11].d[1] ;
wire \in.d[13].d[1] ;
wire \in.d[0].d[1] ;
reg \ct.in[1] ;
wire \in.d[14].d[0] ;
wire \in.d[12].d[1] ;
wire \in.d[9].d[0] ;
wire \in.d[2].d[1] ;
reg \ct.in[5] ;
wire \in.d[5].d[1] ;
reg \ct.in[12] ;
reg \ct.in[6] ;
wire \in.d[3].d[0] ;
wire \in.d[8].d[0] ;
wire \in.d[8].d[1] ;
reg \ct.in[7] ;
wire \in.d[6].d[0] ;
wire \in.d[6].d[1] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4 \ct (.\in[0] (\ct.in[0] ), .\in[1] (\ct.in[1] ), .\in[2] (\ct.in[2] ), .\in[3] (\ct.in[3] ), .\in[4] (\ct.in[4] ), .\in[5] (\ct.in[5] ), .\in[6] (\ct.in[6] ), .\in[7] (\ct.in[7] ), .\in[8] (\ct.in[8] ), .\in[9] (\ct.in[9] ), .\in[10] (\ct.in[10] ), .\in[11] (\ct.in[11] ), .\in[12] (\ct.in[12] ), .\in[13] (\ct.in[13] ), .\in[14] (\ct.in[14] ), .out(out));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[0] (.y(\ct.in[0] ), .a(\in.d[0].d[1] ), .b(\in.d[0].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[1] (.y(\ct.in[1] ), .a(\in.d[1].d[1] ), .b(\in.d[1].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[2] (.y(\ct.in[2] ), .a(\in.d[2].d[1] ), .b(\in.d[2].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[3] (.y(\ct.in[3] ), .a(\in.d[3].d[1] ), .b(\in.d[3].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[4] (.y(\ct.in[4] ), .a(\in.d[4].d[1] ), .b(\in.d[4].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[5] (.y(\ct.in[5] ), .a(\in.d[5].d[1] ), .b(\in.d[5].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[6] (.y(\ct.in[6] ), .a(\in.d[6].d[1] ), .b(\in.d[6].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[7] (.y(\ct.in[7] ), .a(\in.d[7].d[1] ), .b(\in.d[7].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[8] (.y(\ct.in[8] ), .a(\in.d[8].d[1] ), .b(\in.d[8].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[9] (.y(\ct.in[9] ), .a(\in.d[9].d[1] ), .b(\in.d[9].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[10] (.y(\ct.in[10] ), .a(\in.d[10].d[1] ), .b(\in.d[10].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[11] (.y(\ct.in[11] ), .a(\in.d[11].d[1] ), .b(\in.d[11].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[12] (.y(\ct.in[12] ), .a(\in.d[12].d[1] ), .b(\in.d[12].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[13] (.y(\ct.in[13] ), .a(\in.d[13].d[1] ), .b(\in.d[13].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[14] (.y(\ct.in[14] ), .a(\in.d[14].d[1] ), .b(\in.d[14].d[0] ));
endmodule
//
// Verilog module for: A_1C1P_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1(y, c1, p1);
output y;
input c1;
input p1;
// -- signals ---
reg y;
wire c1;
wire p1;
// --- instances
endmodule
//
// Verilog module for: BUF_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X1(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
reg _y;
// --- instances
endmodule
//
// Verilog module for: A_2C1N_RB_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4(y, c1, c2, n1, pr_B, sr_B);
output y;
input c1;
input c2;
input n1;
input pr_B;
input sr_B;
// -- signals ---
reg y;
wire pr_B;
wire c2;
wire n1;
wire c1;
reg _y;
wire sr_B;
// --- instances
endmodule
//
// Verilog module for: buffer<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v , reset_B);
input \in.d.d[0].d[0] ;
input \in.d.d[0].d[1] ;
input \in.d.d[1].d[0] ;
input \in.d.d[1].d[1] ;
input \in.d.d[2].d[0] ;
input \in.d.d[2].d[1] ;
input \in.d.d[3].d[0] ;
input \in.d.d[3].d[1] ;
input \in.d.d[4].d[0] ;
input \in.d.d[4].d[1] ;
input \in.d.d[5].d[0] ;
input \in.d.d[5].d[1] ;
input \in.d.d[6].d[0] ;
input \in.d.d[6].d[1] ;
input \in.d.d[7].d[0] ;
input \in.d.d[7].d[1] ;
input \in.d.d[8].d[0] ;
input \in.d.d[8].d[1] ;
input \in.d.d[9].d[0] ;
input \in.d.d[9].d[1] ;
input \in.d.d[10].d[0] ;
input \in.d.d[10].d[1] ;
input \in.d.d[11].d[0] ;
input \in.d.d[11].d[1] ;
input \in.d.d[12].d[0] ;
input \in.d.d[12].d[1] ;
input \in.d.d[13].d[0] ;
input \in.d.d[13].d[1] ;
input \in.d.d[14].d[0] ;
input \in.d.d[14].d[1] ;
output \in.a ;
output \in.v ;
output \out.d.d[0].d[0] ;
output \out.d.d[0].d[1] ;
output \out.d.d[1].d[0] ;
output \out.d.d[1].d[1] ;
output \out.d.d[2].d[0] ;
output \out.d.d[2].d[1] ;
output \out.d.d[3].d[0] ;
output \out.d.d[3].d[1] ;
output \out.d.d[4].d[0] ;
output \out.d.d[4].d[1] ;
output \out.d.d[5].d[0] ;
output \out.d.d[5].d[1] ;
output \out.d.d[6].d[0] ;
output \out.d.d[6].d[1] ;
output \out.d.d[7].d[0] ;
output \out.d.d[7].d[1] ;
output \out.d.d[8].d[0] ;
output \out.d.d[8].d[1] ;
output \out.d.d[9].d[0] ;
output \out.d.d[9].d[1] ;
output \out.d.d[10].d[0] ;
output \out.d.d[10].d[1] ;
output \out.d.d[11].d[0] ;
output \out.d.d[11].d[1] ;
output \out.d.d[12].d[0] ;
output \out.d.d[12].d[1] ;
output \out.d.d[13].d[0] ;
output \out.d.d[13].d[1] ;
output \out.d.d[14].d[0] ;
output \out.d.d[14].d[1] ;
input \out.a ;
input \out.v ;
input reset_B;
// -- signals ---
reg \out.d.d[8].d[0] ;
reg \out.d.d[6].d[1] ;
reg \out.d.d[5].d[1] ;
reg \_en_X_f[0] ;
wire \in.d.d[14].d[0] ;
wire \in.d.d[12].d[1] ;
reg \out.d.d[12].d[1] ;
wire \in.d.d[5].d[0] ;
reg \out.d.d[11].d[0] ;
reg \out.d.d[7].d[0] ;
reg _reset_BX;
reg \_reset_BXX[0] ;
wire \in.d.d[14].d[1] ;
wire \in.d.d[10].d[1] ;
wire \in.d.d[2].d[0] ;
wire \out.a ;
reg \out.d.d[0].d[0] ;
wire \in.d.d[0].d[0] ;
reg \out.d.d[10].d[1] ;
wire \in.d.d[11].d[0] ;
wire \in.d.d[7].d[1] ;
wire \in.d.d[3].d[1] ;
reg _in_v;
reg \in.v ;
reg _out_a_B;
wire \in.d.d[9].d[1] ;
wire \in.d.d[9].d[0] ;
wire \in.d.d[4].d[1] ;
reg \out.d.d[10].d[0] ;
wire \in.d.d[1].d[1] ;
wire \in.d.d[12].d[0] ;
wire \in.d.d[1].d[0] ;
reg \_out_a_BX_f[0] ;
reg \out.d.d[3].d[1] ;
reg \out.d.d[0].d[1] ;
reg \out.d.d[2].d[1] ;
reg \out.d.d[4].d[1] ;
wire reset_B;
wire \in.d.d[8].d[0] ;
reg \out.d.d[12].d[0] ;
wire \in.d.d[5].d[1] ;
reg \out.d.d[9].d[0] ;
reg \out.d.d[7].d[1] ;
reg \_out_a_BX_t[0] ;
wire \in.d.d[10].d[0] ;
reg \out.d.d[1].d[0] ;
wire \in.d.d[6].d[0] ;
wire \in.d.d[7].d[0] ;
wire \in.d.d[13].d[1] ;
wire \out.v ;
reg \out.d.d[2].d[0] ;
wire \in.d.d[13].d[0] ;
wire \in.d.d[11].d[1] ;
wire \in.d.d[6].d[1] ;
reg \out.d.d[3].d[0] ;
reg \out.d.d[11].d[1] ;
reg \out.d.d[9].d[1] ;
wire \in.d.d[3].d[0] ;
reg _en;
reg \out.d.d[13].d[0] ;
reg \out.d.d[5].d[0] ;
reg \in.a ;
reg \out.d.d[14].d[0] ;
reg \out.d.d[4].d[0] ;
wire \in.d.d[8].d[1] ;
reg \out.d.d[13].d[1] ;
reg \out.d.d[8].d[1] ;
reg \out.d.d[14].d[1] ;
wire \in.d.d[2].d[1] ;
reg \out.d.d[6].d[0] ;
wire \in.d.d[4].d[0] ;
reg \out.d.d[1].d[1] ;
reg \_en_X_t[0] ;
wire \in.d.d[0].d[1] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_t (.in(_out_a_B), .\out[0] (\_out_a_BX_f[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4 \inack_ctl (.y(\in.a ), .c1(_en), .c2(\in.v ), .c3(\out.v ), .pr_B(_reset_BX), .sr_B(_reset_BX));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \reset_bufarray (.in(_reset_BX), .\out[0] (\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X4 \in_v_buf (.y(\in.v ), .a(_in_v));
_0_0tmpl_0_0dataflow__neuro_0_0INV__X1 \out_a_inv (.y(_out_a_B), .a(\out.a ));
_0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4 \vc (.\in.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d[14].d[1] (\in.d.d[14].d[1] ), .out(_in_v));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_f (.in(_out_a_B), .\out[0] (\_out_a_BX_t[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1 \en_ctl (.y(_en), .c1(\in.a ), .p1(\out.v ));
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X1 \reset_buf (.y(_reset_BX), .a(reset_B));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_f (.in(_en), .\out[0] (\_en_X_f[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_t (.in(_en), .\out[0] (\_en_X_t[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[0] (.y(\out.d.d[0].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[0].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[1] (.y(\out.d.d[1].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[1].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[2] (.y(\out.d.d[2].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[2].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[3] (.y(\out.d.d[3].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[3].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[4] (.y(\out.d.d[4].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[4].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[5] (.y(\out.d.d[5].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[5].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[6] (.y(\out.d.d[6].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[6].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[7] (.y(\out.d.d[7].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[7].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[8] (.y(\out.d.d[8].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[8].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[9] (.y(\out.d.d[9].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[9].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[10] (.y(\out.d.d[10].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[10].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[11] (.y(\out.d.d[11].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[11].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[12] (.y(\out.d.d[12].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[12].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[13] (.y(\out.d.d[13].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[13].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[14] (.y(\out.d.d[14].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[14].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[0] (.y(\out.d.d[0].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[0].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[1] (.y(\out.d.d[1].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[1].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[2] (.y(\out.d.d[2].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[2].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[3] (.y(\out.d.d[3].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[3].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[4] (.y(\out.d.d[4].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[4].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[5] (.y(\out.d.d[5].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[5].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[6] (.y(\out.d.d[6].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[6].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[7] (.y(\out.d.d[7].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[7].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[8] (.y(\out.d.d[8].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[8].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[9] (.y(\out.d.d[9].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[9].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[10] (.y(\out.d.d[10].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[10].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[11] (.y(\out.d.d[11].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[11].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[12] (.y(\out.d.d[12].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[12].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[13] (.y(\out.d.d[13].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[13].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[14] (.y(\out.d.d[14].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[14].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
endmodule
//
// Verilog module for: buffer_15<>
//
module buffer__15(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v );
input \in.d.d[0].d[0] ;
input \in.d.d[0].d[1] ;
input \in.d.d[1].d[0] ;
input \in.d.d[1].d[1] ;
input \in.d.d[2].d[0] ;
input \in.d.d[2].d[1] ;
input \in.d.d[3].d[0] ;
input \in.d.d[3].d[1] ;
input \in.d.d[4].d[0] ;
input \in.d.d[4].d[1] ;
input \in.d.d[5].d[0] ;
input \in.d.d[5].d[1] ;
input \in.d.d[6].d[0] ;
input \in.d.d[6].d[1] ;
input \in.d.d[7].d[0] ;
input \in.d.d[7].d[1] ;
input \in.d.d[8].d[0] ;
input \in.d.d[8].d[1] ;
input \in.d.d[9].d[0] ;
input \in.d.d[9].d[1] ;
input \in.d.d[10].d[0] ;
input \in.d.d[10].d[1] ;
input \in.d.d[11].d[0] ;
input \in.d.d[11].d[1] ;
input \in.d.d[12].d[0] ;
input \in.d.d[12].d[1] ;
input \in.d.d[13].d[0] ;
input \in.d.d[13].d[1] ;
input \in.d.d[14].d[0] ;
input \in.d.d[14].d[1] ;
output \in.a ;
output \in.v ;
output \out.d.d[0].d[0] ;
output \out.d.d[0].d[1] ;
output \out.d.d[1].d[0] ;
output \out.d.d[1].d[1] ;
output \out.d.d[2].d[0] ;
output \out.d.d[2].d[1] ;
output \out.d.d[3].d[0] ;
output \out.d.d[3].d[1] ;
output \out.d.d[4].d[0] ;
output \out.d.d[4].d[1] ;
output \out.d.d[5].d[0] ;
output \out.d.d[5].d[1] ;
output \out.d.d[6].d[0] ;
output \out.d.d[6].d[1] ;
output \out.d.d[7].d[0] ;
output \out.d.d[7].d[1] ;
output \out.d.d[8].d[0] ;
output \out.d.d[8].d[1] ;
output \out.d.d[9].d[0] ;
output \out.d.d[9].d[1] ;
output \out.d.d[10].d[0] ;
output \out.d.d[10].d[1] ;
output \out.d.d[11].d[0] ;
output \out.d.d[11].d[1] ;
output \out.d.d[12].d[0] ;
output \out.d.d[12].d[1] ;
output \out.d.d[13].d[0] ;
output \out.d.d[13].d[1] ;
output \out.d.d[14].d[0] ;
output \out.d.d[14].d[1] ;
input \out.a ;
input \out.v ;
// -- signals ---
reg \out.d.d[2].d[1] ;
wire \in.d.d[10].d[0] ;
reg \out.d.d[1].d[0] ;
wire \in.d.d[10].d[1] ;
wire \in.d.d[4].d[0] ;
reg \out.d.d[10].d[1] ;
wire \in.d.d[13].d[0] ;
reg \out.d.d[13].d[0] ;
reg \out.d.d[9].d[1] ;
wire \in.d.d[2].d[1] ;
reg \out.d.d[2].d[0] ;
reg \out.d.d[0].d[0] ;
reg \out.d.d[14].d[0] ;
reg \out.d.d[5].d[0] ;
reg \in.a ;
reg _reset_B;
wire \out.v ;
wire \out.a ;
reg \out.d.d[4].d[0] ;
wire \in.d.d[9].d[1] ;
wire \in.d.d[3].d[0] ;
wire \in.d.d[11].d[0] ;
wire \in.d.d[2].d[0] ;
reg \out.d.d[6].d[0] ;
reg \out.d.d[13].d[1] ;
reg \out.d.d[10].d[0] ;
reg \out.d.d[7].d[1] ;
wire \in.d.d[12].d[1] ;
wire \in.d.d[6].d[1] ;
reg \out.d.d[7].d[0] ;
reg \out.d.d[3].d[0] ;
wire \in.d.d[1].d[0] ;
reg \out.d.d[14].d[1] ;
reg \out.d.d[8].d[0] ;
wire \in.d.d[13].d[1] ;
wire \in.d.d[7].d[0] ;
reg \out.d.d[12].d[0] ;
wire \in.d.d[8].d[1] ;
reg \out.d.d[4].d[1] ;
wire \in.d.d[14].d[0] ;
wire \in.d.d[5].d[1] ;
wire \in.d.d[1].d[1] ;
wire \in.d.d[9].d[0] ;
wire \in.d.d[14].d[1] ;
reg \out.d.d[11].d[0] ;
reg \out.d.d[6].d[1] ;
wire \in.d.d[12].d[0] ;
wire \in.d.d[7].d[1] ;
reg \out.d.d[0].d[1] ;
wire \in.d.d[11].d[1] ;
wire \in.d.d[8].d[0] ;
wire \in.d.d[5].d[0] ;
reg \out.d.d[1].d[1] ;
reg \in.v ;
wire \in.d.d[0].d[1] ;
wire \in.d.d[0].d[0] ;
reg \out.d.d[5].d[1] ;
reg \out.d.d[8].d[1] ;
reg \out.d.d[3].d[1] ;
wire \in.d.d[6].d[0] ;
reg \out.d.d[11].d[1] ;
wire \in.d.d[3].d[1] ;
reg \out.d.d[12].d[1] ;
wire \in.d.d[4].d[1] ;
reg \out.d.d[9].d[0] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4 \buffer_test (.\in.d.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d.d[14].d[1] (\in.d.d[14].d[1] ), .\in.a (\in.a ), .\in.v (\in.v ), .\out.d.d[0].d[0] (\out.d.d[0].d[0] ), .\out.d.d[0].d[1] (\out.d.d[0].d[1] ), .\out.d.d[1].d[0] (\out.d.d[1].d[0] ), .\out.d.d[1].d[1] (\out.d.d[1].d[1] ), .\out.d.d[2].d[0] (\out.d.d[2].d[0] ), .\out.d.d[2].d[1] (\out.d.d[2].d[1] ), .\out.d.d[3].d[0] (\out.d.d[3].d[0] ), .\out.d.d[3].d[1] (\out.d.d[3].d[1] ), .\out.d.d[4].d[0] (\out.d.d[4].d[0] ), .\out.d.d[4].d[1] (\out.d.d[4].d[1] ), .\out.d.d[5].d[0] (\out.d.d[5].d[0] ), .\out.d.d[5].d[1] (\out.d.d[5].d[1] ), .\out.d.d[6].d[0] (\out.d.d[6].d[0] ), .\out.d.d[6].d[1] (\out.d.d[6].d[1] ), .\out.d.d[7].d[0] (\out.d.d[7].d[0] ), .\out.d.d[7].d[1] (\out.d.d[7].d[1] ), .\out.d.d[8].d[0] (\out.d.d[8].d[0] ), .\out.d.d[8].d[1] (\out.d.d[8].d[1] ), .\out.d.d[9].d[0] (\out.d.d[9].d[0] ), .\out.d.d[9].d[1] (\out.d.d[9].d[1] ), .\out.d.d[10].d[0] (\out.d.d[10].d[0] ), .\out.d.d[10].d[1] (\out.d.d[10].d[1] ), .\out.d.d[11].d[0] (\out.d.d[11].d[0] ), .\out.d.d[11].d[1] (\out.d.d[11].d[1] ), .\out.d.d[12].d[0] (\out.d.d[12].d[0] ), .\out.d.d[12].d[1] (\out.d.d[12].d[1] ), .\out.d.d[13].d[0] (\out.d.d[13].d[0] ), .\out.d.d[13].d[1] (\out.d.d[13].d[1] ), .\out.d.d[14].d[0] (\out.d.d[14].d[0] ), .\out.d.d[14].d[1] (\out.d.d[14].d[1] ), .\out.a (\out.a ), .\out.v (\out.v ), .reset_B(_reset_B));
endmodule

48
test/unit_tests/buf_15/test.act
View File

@@ -1,48 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc buffer_15 (avMx1of2<15> in; avMx1of2<15> out){
buffer<15> buffer_test(.in=in, .out=out);
//Low active Reset
bool _reset_B;
prs {
Reset => _reset_B-
}
buffer_test.supply.vss = GND;
buffer_test.supply.vdd = Vdd;
buffer_test.reset_B = _reset_B;
}
buffer_15 t;

29
test/unit_tests/buf_15/test.prsim
View File

@@ -1,29 +0,0 @@
set-qdi-channel-neutral "t.in" 15
set t.out.a 0
set t.out.v 0
cycle
system "echo 'yo man'"
set Reset 0
cycle
system "echo 'reset completed'"
status X
mode run
assert-qdi-channel-neutral "t.out" 15
cycle
set-qdi-channel-valid "t.in" 15 5
cycle
assert t.in.v 1
assert t.in.a 0
assert-qdi-channel-valid "t.out" 15 5
set t.out.v 1
cycle
assert t.in.a 1
set-qdi-channel-neutral "t.in" 15
cycle
set t.out.a 1
system "echo 'Finished'"

571
test/unit_tests/buf_15_friendly2.v
View File

@@ -1,571 +0,0 @@
//
// Verilog module for: BUF_X6<>
//
//
// Verilog module for: sigbuf<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4(in, \out[0] , vdd, vss);
input vdd;
input vss;
input in;
output \out[0] ;
// -- signals ---
wire in;
reg \out[0] ;
// --- instances
BUF_X6 \buf6 (.y(\out[0] ), .a(in), .vdd(vdd), .vss(vss));
endmodule
//
// Verilog module for: A_3C_RB_X4<>
//
//
// Verilog module for: BUF_X4<>
//
//
// Verilog module for: INV_X1<>
//
//
// Verilog module for: A_2C_B_X1<>
//
//
// Verilog module for: A_3C_B_X1<>
//
//
// Verilog module for: ctree<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4(\in[0] , \in[1] , \in[2] , \in[3] , \in[4] , \in[5] , \in[6] , \in[7] , \in[8] , \in[9] , \in[10] , \in[11] , \in[12] , \in[13] , \in[14] , out, vdd, vss);
input vdd;
input vss;
input \in[0] ;
input \in[1] ;
input \in[2] ;
input \in[3] ;
input \in[4] ;
input \in[5] ;
input \in[6] ;
input \in[7] ;
input \in[8] ;
input \in[9] ;
input \in[10] ;
input \in[11] ;
input \in[12] ;
input \in[13] ;
input \in[14] ;
output out;
// -- signals ---
wire \in[4] ;
wire \in[11] ;
wire \in[12] ;
reg \tmp[21] ;
wire \in[3] ;
reg out;
reg \tmp[23] ;
wire \in[6] ;
wire \in[0] ;
reg \tmp[18] ;
wire \in[10] ;
reg \tmp[15] ;
reg \tmp[16] ;
wire \in[13] ;
wire \in[1] ;
wire \in[9] ;
wire \in[2] ;
wire \in[5] ;
reg \tmp[24] ;
wire \in[14] ;
reg \tmp[19] ;
wire \in[7] ;
reg \tmp[22] ;
reg \tmp[20] ;
wire \in[8] ;
reg \tmp[17] ;
// --- instances
A_2C_B_X1 \C2Els[0] (.y(\tmp[15] ), .c1(\in[0] ), .c2(\in[1] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[1] (.y(\tmp[16] ), .c1(\in[2] ), .c2(\in[3] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[2] (.y(\tmp[17] ), .c1(\in[4] ), .c2(\in[5] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[3] (.y(\tmp[18] ), .c1(\in[6] ), .c2(\in[7] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[4] (.y(\tmp[19] ), .c1(\in[8] ), .c2(\in[9] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[5] (.y(\tmp[20] ), .c1(\in[10] ), .c2(\in[11] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[6] (.y(\tmp[22] ), .c1(\tmp[15] ), .c2(\tmp[16] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[7] (.y(\tmp[23] ), .c1(\tmp[17] ), .c2(\tmp[18] ), .vdd(vdd), .vss(vss));
A_3C_B_X1 \C3Els[0] (.y(\tmp[21] ), .c1(\in[12] ), .c2(\in[13] ), .c3(\in[14] ), .vdd(vdd), .vss(vss));
A_3C_B_X1 \C3Els[1] (.y(\tmp[24] ), .c1(\tmp[19] ), .c2(\tmp[20] ), .c3(\tmp[21] ), .vdd(vdd), .vss(vss));
A_3C_B_X1 \C3Els[2] (.y(out), .c1(\tmp[22] ), .c2(\tmp[23] ), .c3(\tmp[24] ), .vdd(vdd), .vss(vss));
endmodule
//
// Verilog module for: OR2_X1<>
//
//
// Verilog module for: vtree<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4(\in.d[0].d[0] , \in.d[0].d[1] , \in.d[1].d[0] , \in.d[1].d[1] , \in.d[2].d[0] , \in.d[2].d[1] , \in.d[3].d[0] , \in.d[3].d[1] , \in.d[4].d[0] , \in.d[4].d[1] , \in.d[5].d[0] , \in.d[5].d[1] , \in.d[6].d[0] , \in.d[6].d[1] , \in.d[7].d[0] , \in.d[7].d[1] , \in.d[8].d[0] , \in.d[8].d[1] , \in.d[9].d[0] , \in.d[9].d[1] , \in.d[10].d[0] , \in.d[10].d[1] , \in.d[11].d[0] , \in.d[11].d[1] , \in.d[12].d[0] , \in.d[12].d[1] , \in.d[13].d[0] , \in.d[13].d[1] , \in.d[14].d[0] , \in.d[14].d[1] , out, vdd, vss);
input vdd;
input vss;
input \in.d[0].d[0] ;
input \in.d[0].d[1] ;
input \in.d[1].d[0] ;
input \in.d[1].d[1] ;
input \in.d[2].d[0] ;
input \in.d[2].d[1] ;
input \in.d[3].d[0] ;
input \in.d[3].d[1] ;
input \in.d[4].d[0] ;
input \in.d[4].d[1] ;
input \in.d[5].d[0] ;
input \in.d[5].d[1] ;
input \in.d[6].d[0] ;
input \in.d[6].d[1] ;
input \in.d[7].d[0] ;
input \in.d[7].d[1] ;
input \in.d[8].d[0] ;
input \in.d[8].d[1] ;
input \in.d[9].d[0] ;
input \in.d[9].d[1] ;
input \in.d[10].d[0] ;
input \in.d[10].d[1] ;
input \in.d[11].d[0] ;
input \in.d[11].d[1] ;
input \in.d[12].d[0] ;
input \in.d[12].d[1] ;
input \in.d[13].d[0] ;
input \in.d[13].d[1] ;
input \in.d[14].d[0] ;
input \in.d[14].d[1] ;
output out;
// -- signals ---
reg \ct.in[14] ;
reg \ct.in[13] ;
wire \in.d[7].d[0] ;
wire \in.d[1].d[0] ;
wire \in.d[0].d[0] ;
reg \ct.in[4] ;
reg out;
wire \in.d[10].d[0] ;
wire \in.d[4].d[1] ;
reg \ct.in[3] ;
wire \in.d[9].d[1] ;
wire \in.d[1].d[1] ;
wire \in.d[2].d[0] ;
wire \in.d[10].d[1] ;
reg \ct.in[8] ;
wire \in.d[12].d[0] ;
wire \in.d[5].d[0] ;
wire \in.d[4].d[0] ;
reg \ct.in[10] ;
reg \ct.in[0] ;
wire \in.d[11].d[0] ;
wire \in.d[7].d[1] ;
wire \in.d[3].d[1] ;
reg \ct.in[11] ;
reg \ct.in[2] ;
reg \ct.in[9] ;
wire \in.d[13].d[0] ;
wire \in.d[14].d[1] ;
wire \in.d[11].d[1] ;
wire \in.d[13].d[1] ;
wire \in.d[0].d[1] ;
reg \ct.in[1] ;
wire \in.d[14].d[0] ;
wire \in.d[12].d[1] ;
wire \in.d[9].d[0] ;
wire \in.d[2].d[1] ;
reg \ct.in[5] ;
wire \in.d[5].d[1] ;
reg \ct.in[12] ;
reg \ct.in[6] ;
wire \in.d[3].d[0] ;
wire \in.d[8].d[0] ;
wire \in.d[8].d[1] ;
reg \ct.in[7] ;
wire \in.d[6].d[0] ;
wire \in.d[6].d[1] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4 \ct (.\in[0] (\ct.in[0] ), .\in[1] (\ct.in[1] ), .\in[2] (\ct.in[2] ), .\in[3] (\ct.in[3] ), .\in[4] (\ct.in[4] ), .\in[5] (\ct.in[5] ), .\in[6] (\ct.in[6] ), .\in[7] (\ct.in[7] ), .\in[8] (\ct.in[8] ), .\in[9] (\ct.in[9] ), .\in[10] (\ct.in[10] ), .\in[11] (\ct.in[11] ), .\in[12] (\ct.in[12] ), .\in[13] (\ct.in[13] ), .\in[14] (\ct.in[14] ), .out(out), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[0] (.y(\ct.in[0] ), .a(\in.d[0].d[1] ), .b(\in.d[0].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[1] (.y(\ct.in[1] ), .a(\in.d[1].d[1] ), .b(\in.d[1].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[2] (.y(\ct.in[2] ), .a(\in.d[2].d[1] ), .b(\in.d[2].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[3] (.y(\ct.in[3] ), .a(\in.d[3].d[1] ), .b(\in.d[3].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[4] (.y(\ct.in[4] ), .a(\in.d[4].d[1] ), .b(\in.d[4].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[5] (.y(\ct.in[5] ), .a(\in.d[5].d[1] ), .b(\in.d[5].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[6] (.y(\ct.in[6] ), .a(\in.d[6].d[1] ), .b(\in.d[6].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[7] (.y(\ct.in[7] ), .a(\in.d[7].d[1] ), .b(\in.d[7].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[8] (.y(\ct.in[8] ), .a(\in.d[8].d[1] ), .b(\in.d[8].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[9] (.y(\ct.in[9] ), .a(\in.d[9].d[1] ), .b(\in.d[9].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[10] (.y(\ct.in[10] ), .a(\in.d[10].d[1] ), .b(\in.d[10].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[11] (.y(\ct.in[11] ), .a(\in.d[11].d[1] ), .b(\in.d[11].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[12] (.y(\ct.in[12] ), .a(\in.d[12].d[1] ), .b(\in.d[12].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[13] (.y(\ct.in[13] ), .a(\in.d[13].d[1] ), .b(\in.d[13].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[14] (.y(\ct.in[14] ), .a(\in.d[14].d[1] ), .b(\in.d[14].d[0] ), .vdd(vdd), .vss(vss));
endmodule
//
// Verilog module for: A_1C1P_X1<>
//
//
// Verilog module for: BUF_X1<>
//
//
// Verilog module for: A_2C1N_RB_X4<>
//
//
// Verilog module for: buffer<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v , reset_B, vdd, vss);
input vdd;
input vss;
input \in.d.d[0].d[0] ;
input \in.d.d[0].d[1] ;
input \in.d.d[1].d[0] ;
input \in.d.d[1].d[1] ;
input \in.d.d[2].d[0] ;
input \in.d.d[2].d[1] ;
input \in.d.d[3].d[0] ;
input \in.d.d[3].d[1] ;
input \in.d.d[4].d[0] ;
input \in.d.d[4].d[1] ;
input \in.d.d[5].d[0] ;
input \in.d.d[5].d[1] ;
input \in.d.d[6].d[0] ;
input \in.d.d[6].d[1] ;
input \in.d.d[7].d[0] ;
input \in.d.d[7].d[1] ;
input \in.d.d[8].d[0] ;
input \in.d.d[8].d[1] ;
input \in.d.d[9].d[0] ;
input \in.d.d[9].d[1] ;
input \in.d.d[10].d[0] ;
input \in.d.d[10].d[1] ;
input \in.d.d[11].d[0] ;
input \in.d.d[11].d[1] ;
input \in.d.d[12].d[0] ;
input \in.d.d[12].d[1] ;
input \in.d.d[13].d[0] ;
input \in.d.d[13].d[1] ;
input \in.d.d[14].d[0] ;
input \in.d.d[14].d[1] ;
output \in.a ;
output \in.v ;
output \out.d.d[0].d[0] ;
output \out.d.d[0].d[1] ;
output \out.d.d[1].d[0] ;
output \out.d.d[1].d[1] ;
output \out.d.d[2].d[0] ;
output \out.d.d[2].d[1] ;
output \out.d.d[3].d[0] ;
output \out.d.d[3].d[1] ;
output \out.d.d[4].d[0] ;
output \out.d.d[4].d[1] ;
output \out.d.d[5].d[0] ;
output \out.d.d[5].d[1] ;
output \out.d.d[6].d[0] ;
output \out.d.d[6].d[1] ;
output \out.d.d[7].d[0] ;
output \out.d.d[7].d[1] ;
output \out.d.d[8].d[0] ;
output \out.d.d[8].d[1] ;
output \out.d.d[9].d[0] ;
output \out.d.d[9].d[1] ;
output \out.d.d[10].d[0] ;
output \out.d.d[10].d[1] ;
output \out.d.d[11].d[0] ;
output \out.d.d[11].d[1] ;
output \out.d.d[12].d[0] ;
output \out.d.d[12].d[1] ;
output \out.d.d[13].d[0] ;
output \out.d.d[13].d[1] ;
output \out.d.d[14].d[0] ;
output \out.d.d[14].d[1] ;
input \out.a ;
input \out.v ;
input reset_B;
// -- signals ---
reg \out.d.d[8].d[0] ;
reg \out.d.d[6].d[1] ;
reg \out.d.d[5].d[1] ;
reg \_en_X_f[0] ;
wire \in.d.d[14].d[0] ;
wire \in.d.d[12].d[1] ;
reg \out.d.d[12].d[1] ;
wire \in.d.d[5].d[0] ;
reg \out.d.d[11].d[0] ;
reg \out.d.d[7].d[0] ;
reg _reset_BX;
reg \_reset_BXX[0] ;
wire \in.d.d[14].d[1] ;
wire \in.d.d[10].d[1] ;
wire \in.d.d[2].d[0] ;
wire \out.a ;
reg \out.d.d[0].d[0] ;
wire \in.d.d[0].d[0] ;
reg \out.d.d[10].d[1] ;
wire \in.d.d[11].d[0] ;
wire \in.d.d[7].d[1] ;
wire \in.d.d[3].d[1] ;
reg _in_v;
reg \in.v ;
reg _out_a_B;
wire \in.d.d[9].d[1] ;
wire \in.d.d[9].d[0] ;
wire \in.d.d[4].d[1] ;
reg \out.d.d[10].d[0] ;
wire \in.d.d[1].d[1] ;
wire \in.d.d[12].d[0] ;
wire \in.d.d[1].d[0] ;
reg \_out_a_BX_f[0] ;
reg \out.d.d[3].d[1] ;
reg \out.d.d[0].d[1] ;
reg \out.d.d[2].d[1] ;
reg \out.d.d[4].d[1] ;
wire reset_B;
wire \in.d.d[8].d[0] ;
reg \out.d.d[12].d[0] ;
wire \in.d.d[5].d[1] ;
reg \out.d.d[9].d[0] ;
reg \out.d.d[7].d[1] ;
reg \_out_a_BX_t[0] ;
wire \in.d.d[10].d[0] ;
reg \out.d.d[1].d[0] ;
wire \in.d.d[6].d[0] ;
wire \in.d.d[7].d[0] ;
wire \in.d.d[13].d[1] ;
wire \out.v ;
reg \out.d.d[2].d[0] ;
wire \in.d.d[13].d[0] ;
wire \in.d.d[11].d[1] ;
wire \in.d.d[6].d[1] ;
reg \out.d.d[3].d[0] ;
reg \out.d.d[11].d[1] ;
reg \out.d.d[9].d[1] ;
wire \in.d.d[3].d[0] ;
reg _en;
reg \out.d.d[13].d[0] ;
reg \out.d.d[5].d[0] ;
reg \in.a ;
reg \out.d.d[14].d[0] ;
reg \out.d.d[4].d[0] ;
wire \in.d.d[8].d[1] ;
reg \out.d.d[13].d[1] ;
reg \out.d.d[8].d[1] ;
reg \out.d.d[14].d[1] ;
wire \in.d.d[2].d[1] ;
reg \out.d.d[6].d[0] ;
wire \in.d.d[4].d[0] ;
reg \out.d.d[1].d[1] ;
reg \_en_X_t[0] ;
wire \in.d.d[0].d[1] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_t (.in(_out_a_B), .\out[0] (\_out_a_BX_f[0] ), .vdd(vdd), .vss(vss));
A_3C_RB_X4 \inack_ctl (.y(\in.a ), .c1(_en), .c2(\in.v ), .c3(\out.v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \reset_bufarray (.in(_reset_BX), .\out[0] (\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
BUF_X4 \in_v_buf (.y(\in.v ), .a(_in_v), .vdd(vdd), .vss(vss));
INV_X1 \out_a_inv (.y(_out_a_B), .a(\out.a ), .vdd(vdd), .vss(vss));
_0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4 \vc (.\in.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d[14].d[1] (\in.d.d[14].d[1] ), .out(_in_v), .vdd(vdd), .vss(vss));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_f (.in(_out_a_B), .\out[0] (\_out_a_BX_t[0] ), .vdd(vdd), .vss(vss));
A_1C1P_X1 \en_ctl (.y(_en), .c1(\in.a ), .p1(\out.v ), .vdd(vdd), .vss(vss));
BUF_X1 \reset_buf (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_f (.in(_en), .\out[0] (\_en_X_f[0] ), .vdd(vdd), .vss(vss));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_t (.in(_en), .\out[0] (\_en_X_t[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[0] (.y(\out.d.d[0].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[0].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[1] (.y(\out.d.d[1].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[1].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[2] (.y(\out.d.d[2].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[2].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[3] (.y(\out.d.d[3].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[3].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[4] (.y(\out.d.d[4].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[4].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[5] (.y(\out.d.d[5].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[5].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[6] (.y(\out.d.d[6].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[6].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[7] (.y(\out.d.d[7].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[7].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[8] (.y(\out.d.d[8].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[8].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[9] (.y(\out.d.d[9].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[9].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[10] (.y(\out.d.d[10].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[10].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[11] (.y(\out.d.d[11].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[11].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[12] (.y(\out.d.d[12].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[12].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[13] (.y(\out.d.d[13].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[13].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[14] (.y(\out.d.d[14].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[14].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[0] (.y(\out.d.d[0].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[0].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[1] (.y(\out.d.d[1].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[1].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[2] (.y(\out.d.d[2].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[2].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[3] (.y(\out.d.d[3].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[3].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[4] (.y(\out.d.d[4].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[4].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[5] (.y(\out.d.d[5].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[5].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[6] (.y(\out.d.d[6].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[6].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[7] (.y(\out.d.d[7].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[7].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[8] (.y(\out.d.d[8].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[8].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[9] (.y(\out.d.d[9].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[9].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[10] (.y(\out.d.d[10].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[10].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[11] (.y(\out.d.d[11].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[11].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[12] (.y(\out.d.d[12].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[12].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[13] (.y(\out.d.d[13].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[13].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[14] (.y(\out.d.d[14].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[14].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
endmodule
//
// Verilog module for: buffer_15<>
//
module buffer__15(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v , vdd, vss);
input vdd;
input vss;
input \in.d.d[0].d[0] ;
input \in.d.d[0].d[1] ;
input \in.d.d[1].d[0] ;
input \in.d.d[1].d[1] ;
input \in.d.d[2].d[0] ;
input \in.d.d[2].d[1] ;
input \in.d.d[3].d[0] ;
input \in.d.d[3].d[1] ;
input \in.d.d[4].d[0] ;
input \in.d.d[4].d[1] ;
input \in.d.d[5].d[0] ;
input \in.d.d[5].d[1] ;
input \in.d.d[6].d[0] ;
input \in.d.d[6].d[1] ;
input \in.d.d[7].d[0] ;
input \in.d.d[7].d[1] ;
input \in.d.d[8].d[0] ;
input \in.d.d[8].d[1] ;
input \in.d.d[9].d[0] ;
input \in.d.d[9].d[1] ;
input \in.d.d[10].d[0] ;
input \in.d.d[10].d[1] ;
input \in.d.d[11].d[0] ;
input \in.d.d[11].d[1] ;
input \in.d.d[12].d[0] ;
input \in.d.d[12].d[1] ;
input \in.d.d[13].d[0] ;
input \in.d.d[13].d[1] ;
input \in.d.d[14].d[0] ;
input \in.d.d[14].d[1] ;
output \in.a ;
output \in.v ;
output \out.d.d[0].d[0] ;
output \out.d.d[0].d[1] ;
output \out.d.d[1].d[0] ;
output \out.d.d[1].d[1] ;
output \out.d.d[2].d[0] ;
output \out.d.d[2].d[1] ;
output \out.d.d[3].d[0] ;
output \out.d.d[3].d[1] ;
output \out.d.d[4].d[0] ;
output \out.d.d[4].d[1] ;
output \out.d.d[5].d[0] ;
output \out.d.d[5].d[1] ;
output \out.d.d[6].d[0] ;
output \out.d.d[6].d[1] ;
output \out.d.d[7].d[0] ;
output \out.d.d[7].d[1] ;
output \out.d.d[8].d[0] ;
output \out.d.d[8].d[1] ;
output \out.d.d[9].d[0] ;
output \out.d.d[9].d[1] ;
output \out.d.d[10].d[0] ;
output \out.d.d[10].d[1] ;
output \out.d.d[11].d[0] ;
output \out.d.d[11].d[1] ;
output \out.d.d[12].d[0] ;
output \out.d.d[12].d[1] ;
output \out.d.d[13].d[0] ;
output \out.d.d[13].d[1] ;
output \out.d.d[14].d[0] ;
output \out.d.d[14].d[1] ;
input \out.a ;
input \out.v ;
// -- signals ---
reg \out.d.d[2].d[1] ;
wire \in.d.d[10].d[0] ;
reg \out.d.d[1].d[0] ;
wire \in.d.d[10].d[1] ;
wire \in.d.d[4].d[0] ;
reg \out.d.d[10].d[1] ;
wire \in.d.d[13].d[0] ;
reg \out.d.d[13].d[0] ;
reg \out.d.d[9].d[1] ;
wire \in.d.d[2].d[1] ;
reg \out.d.d[2].d[0] ;
reg \out.d.d[0].d[0] ;
reg \out.d.d[14].d[0] ;
reg \out.d.d[5].d[0] ;
reg \in.a ;
reg _reset_B;
wire \out.v ;
wire \out.a ;
reg \out.d.d[4].d[0] ;
wire \in.d.d[9].d[1] ;
wire \in.d.d[3].d[0] ;
wire \in.d.d[11].d[0] ;
wire \in.d.d[2].d[0] ;
reg \out.d.d[6].d[0] ;
reg \out.d.d[13].d[1] ;
reg \out.d.d[10].d[0] ;
reg \out.d.d[7].d[1] ;
wire \in.d.d[12].d[1] ;
wire \in.d.d[6].d[1] ;
reg \out.d.d[7].d[0] ;
reg \out.d.d[3].d[0] ;
wire \in.d.d[1].d[0] ;
reg \out.d.d[14].d[1] ;
reg \out.d.d[8].d[0] ;
wire \in.d.d[13].d[1] ;
wire \in.d.d[7].d[0] ;
reg \out.d.d[12].d[0] ;
wire \in.d.d[8].d[1] ;
reg \out.d.d[4].d[1] ;
wire \in.d.d[14].d[0] ;
wire \in.d.d[5].d[1] ;
wire \in.d.d[1].d[1] ;
wire \in.d.d[9].d[0] ;
wire \in.d.d[14].d[1] ;
reg \out.d.d[11].d[0] ;
reg \out.d.d[6].d[1] ;
wire \in.d.d[12].d[0] ;
wire \in.d.d[7].d[1] ;
reg \out.d.d[0].d[1] ;
wire \in.d.d[11].d[1] ;
wire \in.d.d[8].d[0] ;
wire \in.d.d[5].d[0] ;
reg \out.d.d[1].d[1] ;
reg \in.v ;
wire \in.d.d[0].d[1] ;
wire \in.d.d[0].d[0] ;
reg \out.d.d[5].d[1] ;
reg \out.d.d[8].d[1] ;
reg \out.d.d[3].d[1] ;
wire \in.d.d[6].d[0] ;
reg \out.d.d[11].d[1] ;
wire \in.d.d[3].d[1] ;
reg \out.d.d[12].d[1] ;
wire \in.d.d[4].d[1] ;
reg \out.d.d[9].d[0] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4 \buffer_test (.\in.d.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d.d[14].d[1] (\in.d.d[14].d[1] ), .\in.a (\in.a ), .\in.v (\in.v ), .\out.d.d[0].d[0] (\out.d.d[0].d[0] ), .\out.d.d[0].d[1] (\out.d.d[0].d[1] ), .\out.d.d[1].d[0] (\out.d.d[1].d[0] ), .\out.d.d[1].d[1] (\out.d.d[1].d[1] ), .\out.d.d[2].d[0] (\out.d.d[2].d[0] ), .\out.d.d[2].d[1] (\out.d.d[2].d[1] ), .\out.d.d[3].d[0] (\out.d.d[3].d[0] ), .\out.d.d[3].d[1] (\out.d.d[3].d[1] ), .\out.d.d[4].d[0] (\out.d.d[4].d[0] ), .\out.d.d[4].d[1] (\out.d.d[4].d[1] ), .\out.d.d[5].d[0] (\out.d.d[5].d[0] ), .\out.d.d[5].d[1] (\out.d.d[5].d[1] ), .\out.d.d[6].d[0] (\out.d.d[6].d[0] ), .\out.d.d[6].d[1] (\out.d.d[6].d[1] ), .\out.d.d[7].d[0] (\out.d.d[7].d[0] ), .\out.d.d[7].d[1] (\out.d.d[7].d[1] ), .\out.d.d[8].d[0] (\out.d.d[8].d[0] ), .\out.d.d[8].d[1] (\out.d.d[8].d[1] ), .\out.d.d[9].d[0] (\out.d.d[9].d[0] ), .\out.d.d[9].d[1] (\out.d.d[9].d[1] ), .\out.d.d[10].d[0] (\out.d.d[10].d[0] ), .\out.d.d[10].d[1] (\out.d.d[10].d[1] ), .\out.d.d[11].d[0] (\out.d.d[11].d[0] ), .\out.d.d[11].d[1] (\out.d.d[11].d[1] ), .\out.d.d[12].d[0] (\out.d.d[12].d[0] ), .\out.d.d[12].d[1] (\out.d.d[12].d[1] ), .\out.d.d[13].d[0] (\out.d.d[13].d[0] ), .\out.d.d[13].d[1] (\out.d.d[13].d[1] ), .\out.d.d[14].d[0] (\out.d.d[14].d[0] ), .\out.d.d[14].d[1] (\out.d.d[14].d[1] ), .\out.a (\out.a ), .\out.v (\out.v ), .reset_B(_reset_B), .vdd(vdd), .vss(vss));
endmodule

47
test/unit_tests/buf_s_5/test.act
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@@ -1,47 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc buffer_s_5(avMx1of2<5> in; avMx1of2<5> out)
{
bool _reset_B;
prs {
Reset => _reset_B-
}
buffer_s<5> b(.in = in, .out = out);
b.supply.vdd = Vdd;
b.supply.vss = GND;
b.reset_B = _reset_B;
}
buffer_s_5 b;

66
test/unit_tests/buf_s_5/test.prsim
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@@ -1,66 +0,0 @@
watchall
set-qdi-channel-neutral "b.in" 5
set b.out.a 0
set b.out.v 0
# set b.in.a 1
# set b.in.v 1
set Reset 0
# Set output channel variables to all active (incorrect)
set b.out.d.d[0].t 1
set b.out.d.d[0].f 1
set b.out.d.d[1].t 1
set b.out.d.d[1].f 1
set b.out.d.d[2].t 1
set b.out.d.d[2].f 1
set b.out.d.d[3].t 1
set b.out.d.d[3].f 1
set b.out.d.d[4].t 1
set b.out.d.d[4].f 1
cycle
system "echo '[] set Reset 1'"
set Reset 1
cycle
system "echo '[] set Reset 0'"
set Reset 0
mode run
cycle
assert-qdi-channel-neutral "b.out" 5
system "echo '[] Reset finished, setting some inputs.'"
status X
set b.in.d.d[0].t 1
set b.in.d.d[1].t 1
set b.in.d.d[2].f 1
set b.in.d.d[3].f 1
cycle
system "echo '[] Setting final input'"
set b.in.d.d[4].t 1
cycle
system "echo '[] Receiving out val'"
set b.out.v 1
cycle
assert b.in.a 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "b.in" 5
cycle
system "echo '[] Receiving out ack'"
set b.out.a 1
cycle
assert-qdi-channel-neutral "b.out" 5

685
test/unit_tests/buff.v
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@@ -1,685 +0,0 @@
//
// Verilog module for: BUF_X6<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X6(y, a);
output y;
input a;
// -- signals ---
wire a;
reg y;
reg _y;
// --- instances
endmodule
//
// Verilog module for: sigbuf<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4(in, \out[0] );
input in;
output \out[0] ;
// -- signals ---
reg \out[0] ;
wire in;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X6 \buf6 (.y(\out[0] ), .a(in));
endmodule
//
// Verilog module for: A_3C_RB_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4(y, c1, c2, c3, pr_B, sr_B);
output y;
input c1;
input c2;
input c3;
input pr_B;
input sr_B;
// -- signals ---
wire pr_B;
wire c3;
wire c1;
wire sr_B;
wire c2;
reg _y;
reg y;
// --- instances
endmodule
//
// Verilog module for: BUF_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X4(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
reg _y;
// --- instances
endmodule
//
// Verilog module for: INV_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0INV__X1(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
// --- instances
endmodule
//
// Verilog module for: A_2C_B_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1(y, c1, c2);
output y;
input c1;
input c2;
// -- signals ---
wire c2;
wire c1;
reg y;
reg _y;
// --- instances
endmodule
//
// Verilog module for: A_3C_B_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1(y, c1, c2, c3);
output y;
input c1;
input c2;
input c3;
// -- signals ---
wire c1;
reg y;
reg _y;
wire c3;
wire c2;
// --- instances
endmodule
//
// Verilog module for: ctree<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4(\in[0] , \in[1] , \in[2] , \in[3] , \in[4] , \in[5] , \in[6] , \in[7] , \in[8] , \in[9] , \in[10] , \in[11] , \in[12] , \in[13] , \in[14] , out);
input \in[0] ;
input \in[1] ;
input \in[2] ;
input \in[3] ;
input \in[4] ;
input \in[5] ;
input \in[6] ;
input \in[7] ;
input \in[8] ;
input \in[9] ;
input \in[10] ;
input \in[11] ;
input \in[12] ;
input \in[13] ;
input \in[14] ;
output out;
// -- signals ---
wire \in[9] ;
wire \in[11] ;
reg \tmp[18] ;
reg \tmp[16] ;
reg \tmp[24] ;
wire \in[0] ;
reg \tmp[22] ;
reg out;
wire \in[7] ;
reg \tmp[23] ;
wire \in[4] ;
wire \in[3] ;
wire \in[12] ;
reg \tmp[20] ;
wire \in[2] ;
reg \tmp[19] ;
wire \in[14] ;
wire \in[6] ;
wire \in[10] ;
wire \in[5] ;
wire \in[8] ;
wire \in[13] ;
wire \in[1] ;
reg \tmp[21] ;
reg \tmp[17] ;
reg \tmp[15] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[0] (.y(\tmp[15] ), .c1(\in[0] ), .c2(\in[1] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[1] (.y(\tmp[16] ), .c1(\in[2] ), .c2(\in[3] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[2] (.y(\tmp[17] ), .c1(\in[4] ), .c2(\in[5] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[3] (.y(\tmp[18] ), .c1(\in[6] ), .c2(\in[7] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[4] (.y(\tmp[19] ), .c1(\in[8] ), .c2(\in[9] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[5] (.y(\tmp[20] ), .c1(\in[10] ), .c2(\in[11] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[6] (.y(\tmp[22] ), .c1(\tmp[15] ), .c2(\tmp[16] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[7] (.y(\tmp[23] ), .c1(\tmp[17] ), .c2(\tmp[18] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[0] (.y(\tmp[21] ), .c1(\in[12] ), .c2(\in[13] ), .c3(\in[14] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[1] (.y(\tmp[24] ), .c1(\tmp[19] ), .c2(\tmp[20] ), .c3(\tmp[21] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[2] (.y(out), .c1(\tmp[22] ), .c2(\tmp[23] ), .c3(\tmp[24] ));
endmodule
//
// Verilog module for: OR2_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0OR2__X1(y, a, b);
output y;
input a;
input b;
// -- signals ---
wire a;
wire b;
reg y;
reg _y;
// --- instances
endmodule
//
// Verilog module for: vtree<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4(\in.d[0].d[0] , \in.d[0].d[1] , \in.d[1].d[0] , \in.d[1].d[1] , \in.d[2].d[0] , \in.d[2].d[1] , \in.d[3].d[0] , \in.d[3].d[1] , \in.d[4].d[0] , \in.d[4].d[1] , \in.d[5].d[0] , \in.d[5].d[1] , \in.d[6].d[0] , \in.d[6].d[1] , \in.d[7].d[0] , \in.d[7].d[1] , \in.d[8].d[0] , \in.d[8].d[1] , \in.d[9].d[0] , \in.d[9].d[1] , \in.d[10].d[0] , \in.d[10].d[1] , \in.d[11].d[0] , \in.d[11].d[1] , \in.d[12].d[0] , \in.d[12].d[1] , \in.d[13].d[0] , \in.d[13].d[1] , \in.d[14].d[0] , \in.d[14].d[1] , out);
input \in.d[0].d[0] ;
input \in.d[0].d[1] ;
input \in.d[1].d[0] ;
input \in.d[1].d[1] ;
input \in.d[2].d[0] ;
input \in.d[2].d[1] ;
input \in.d[3].d[0] ;
input \in.d[3].d[1] ;
input \in.d[4].d[0] ;
input \in.d[4].d[1] ;
input \in.d[5].d[0] ;
input \in.d[5].d[1] ;
input \in.d[6].d[0] ;
input \in.d[6].d[1] ;
input \in.d[7].d[0] ;
input \in.d[7].d[1] ;
input \in.d[8].d[0] ;
input \in.d[8].d[1] ;
input \in.d[9].d[0] ;
input \in.d[9].d[1] ;
input \in.d[10].d[0] ;
input \in.d[10].d[1] ;
input \in.d[11].d[0] ;
input \in.d[11].d[1] ;
input \in.d[12].d[0] ;
input \in.d[12].d[1] ;
input \in.d[13].d[0] ;
input \in.d[13].d[1] ;
input \in.d[14].d[0] ;
input \in.d[14].d[1] ;
output out;
// -- signals ---
wire \in.d[2].d[1] ;
wire \in.d[14].d[1] ;
reg \ct.in[8] ;
wire \in.d[10].d[1] ;
wire \in.d[7].d[1] ;
reg \ct.in[14] ;
wire \in.d[3].d[0] ;
reg \ct.in[0] ;
wire \in.d[8].d[1] ;
wire \in.d[6].d[1] ;
reg out;
wire \in.d[14].d[0] ;
wire \in.d[6].d[0] ;
wire \in.d[10].d[0] ;
wire \in.d[5].d[1] ;
wire \in.d[7].d[0] ;
wire \in.d[3].d[1] ;
wire \in.d[2].d[0] ;
reg \ct.in[6] ;
reg \ct.in[4] ;
wire \in.d[5].d[0] ;
wire \in.d[1].d[1] ;
wire \in.d[0].d[1] ;
reg \ct.in[5] ;
reg \ct.in[1] ;
wire \in.d[9].d[0] ;
wire \in.d[0].d[0] ;
wire \in.d[4].d[1] ;
reg \ct.in[12] ;
wire \in.d[12].d[1] ;
wire \in.d[8].d[0] ;
reg \ct.in[2] ;
wire \in.d[13].d[0] ;
wire \in.d[4].d[0] ;
wire \in.d[12].d[0] ;
wire \in.d[11].d[0] ;
wire \in.d[13].d[1] ;
reg \ct.in[9] ;
reg \ct.in[3] ;
reg \ct.in[11] ;
wire \in.d[1].d[0] ;
reg \ct.in[7] ;
wire \in.d[11].d[1] ;
wire \in.d[9].d[1] ;
reg \ct.in[10] ;
reg \ct.in[13] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4 \ct (.\in[0] (\ct.in[0] ), .\in[1] (\ct.in[1] ), .\in[2] (\ct.in[2] ), .\in[3] (\ct.in[3] ), .\in[4] (\ct.in[4] ), .\in[5] (\ct.in[5] ), .\in[6] (\ct.in[6] ), .\in[7] (\ct.in[7] ), .\in[8] (\ct.in[8] ), .\in[9] (\ct.in[9] ), .\in[10] (\ct.in[10] ), .\in[11] (\ct.in[11] ), .\in[12] (\ct.in[12] ), .\in[13] (\ct.in[13] ), .\in[14] (\ct.in[14] ), .out(out));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[0] (.y(\ct.in[0] ), .a(\in.d[0].d[1] ), .b(\in.d[0].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[1] (.y(\ct.in[1] ), .a(\in.d[1].d[1] ), .b(\in.d[1].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[2] (.y(\ct.in[2] ), .a(\in.d[2].d[1] ), .b(\in.d[2].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[3] (.y(\ct.in[3] ), .a(\in.d[3].d[1] ), .b(\in.d[3].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[4] (.y(\ct.in[4] ), .a(\in.d[4].d[1] ), .b(\in.d[4].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[5] (.y(\ct.in[5] ), .a(\in.d[5].d[1] ), .b(\in.d[5].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[6] (.y(\ct.in[6] ), .a(\in.d[6].d[1] ), .b(\in.d[6].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[7] (.y(\ct.in[7] ), .a(\in.d[7].d[1] ), .b(\in.d[7].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[8] (.y(\ct.in[8] ), .a(\in.d[8].d[1] ), .b(\in.d[8].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[9] (.y(\ct.in[9] ), .a(\in.d[9].d[1] ), .b(\in.d[9].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[10] (.y(\ct.in[10] ), .a(\in.d[10].d[1] ), .b(\in.d[10].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[11] (.y(\ct.in[11] ), .a(\in.d[11].d[1] ), .b(\in.d[11].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[12] (.y(\ct.in[12] ), .a(\in.d[12].d[1] ), .b(\in.d[12].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[13] (.y(\ct.in[13] ), .a(\in.d[13].d[1] ), .b(\in.d[13].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[14] (.y(\ct.in[14] ), .a(\in.d[14].d[1] ), .b(\in.d[14].d[0] ));
endmodule
//
// Verilog module for: A_1C1P_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1(y, c1, p1);
output y;
input c1;
input p1;
// -- signals ---
wire c1;
wire p1;
reg y;
// --- instances
endmodule
//
// Verilog module for: BUF_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X1(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
reg _y;
// --- instances
endmodule
//
// Verilog module for: A_2C1N_RB_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4(y, c1, c2, n1, pr_B, sr_B);
output y;
input c1;
input c2;
input n1;
input pr_B;
input sr_B;
// -- signals ---
reg y;
wire n1;
wire sr_B;
wire pr_B;
wire c2;
wire c1;
reg _y;
// --- instances
endmodule
//
// Verilog module for: buffer<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v , reset_B);
input \in.d.d[0].d[0] ;
input \in.d.d[0].d[1] ;
input \in.d.d[1].d[0] ;
input \in.d.d[1].d[1] ;
input \in.d.d[2].d[0] ;
input \in.d.d[2].d[1] ;
input \in.d.d[3].d[0] ;
input \in.d.d[3].d[1] ;
input \in.d.d[4].d[0] ;
input \in.d.d[4].d[1] ;
input \in.d.d[5].d[0] ;
input \in.d.d[5].d[1] ;
input \in.d.d[6].d[0] ;
input \in.d.d[6].d[1] ;
input \in.d.d[7].d[0] ;
input \in.d.d[7].d[1] ;
input \in.d.d[8].d[0] ;
input \in.d.d[8].d[1] ;
input \in.d.d[9].d[0] ;
input \in.d.d[9].d[1] ;
input \in.d.d[10].d[0] ;
input \in.d.d[10].d[1] ;
input \in.d.d[11].d[0] ;
input \in.d.d[11].d[1] ;
input \in.d.d[12].d[0] ;
input \in.d.d[12].d[1] ;
input \in.d.d[13].d[0] ;
input \in.d.d[13].d[1] ;
input \in.d.d[14].d[0] ;
input \in.d.d[14].d[1] ;
output \in.a ;
output \in.v ;
output \out.d.d[0].d[0] ;
output \out.d.d[0].d[1] ;
output \out.d.d[1].d[0] ;
output \out.d.d[1].d[1] ;
output \out.d.d[2].d[0] ;
output \out.d.d[2].d[1] ;
output \out.d.d[3].d[0] ;
output \out.d.d[3].d[1] ;
output \out.d.d[4].d[0] ;
output \out.d.d[4].d[1] ;
output \out.d.d[5].d[0] ;
output \out.d.d[5].d[1] ;
output \out.d.d[6].d[0] ;
output \out.d.d[6].d[1] ;
output \out.d.d[7].d[0] ;
output \out.d.d[7].d[1] ;
output \out.d.d[8].d[0] ;
output \out.d.d[8].d[1] ;
output \out.d.d[9].d[0] ;
output \out.d.d[9].d[1] ;
output \out.d.d[10].d[0] ;
output \out.d.d[10].d[1] ;
output \out.d.d[11].d[0] ;
output \out.d.d[11].d[1] ;
output \out.d.d[12].d[0] ;
output \out.d.d[12].d[1] ;
output \out.d.d[13].d[0] ;
output \out.d.d[13].d[1] ;
output \out.d.d[14].d[0] ;
output \out.d.d[14].d[1] ;
input \out.a ;
input \out.v ;
input reset_B;
// -- signals ---
wire \in.d.d[9].d[0] ;
reg _out_a_B;
reg \out.d.d[1].d[0] ;
wire \in.d.d[4].d[0] ;
wire \in.d.d[14].d[0] ;
wire \in.d.d[10].d[1] ;
reg \out.d.d[14].d[1] ;
wire \in.d.d[8].d[1] ;
reg \out.d.d[7].d[0] ;
reg \out.d.d[2].d[1] ;
wire \in.d.d[3].d[1] ;
reg \out.d.d[10].d[0] ;
wire \in.d.d[9].d[1] ;
wire \in.d.d[5].d[0] ;
wire \out.v ;
reg \out.d.d[0].d[0] ;
reg \out.d.d[1].d[1] ;
wire \in.d.d[7].d[0] ;
reg \out.d.d[8].d[1] ;
reg \out.d.d[4].d[1] ;
reg _reset_BX;
reg \in.v ;
reg \out.d.d[6].d[0] ;
reg \out.d.d[8].d[0] ;
reg \out.d.d[12].d[0] ;
reg \out.d.d[5].d[0] ;
reg \out.d.d[10].d[1] ;
reg \out.d.d[9].d[1] ;
reg \out.d.d[7].d[1] ;
reg \out.d.d[3].d[0] ;
wire \in.d.d[8].d[0] ;
wire \in.d.d[6].d[0] ;
wire \in.d.d[5].d[1] ;
reg _en;
reg \_out_a_BX_f[0] ;
reg \out.d.d[9].d[0] ;
wire \in.d.d[13].d[1] ;
reg \out.d.d[11].d[0] ;
wire \in.d.d[12].d[0] ;
wire \in.d.d[11].d[0] ;
wire \in.d.d[1].d[1] ;
wire \in.d.d[1].d[0] ;
wire \in.d.d[14].d[1] ;
wire \in.d.d[4].d[1] ;
reg _in_v;
reg \out.d.d[13].d[0] ;
reg \out.d.d[2].d[0] ;
wire \in.d.d[13].d[0] ;
wire \in.d.d[3].d[0] ;
wire \in.d.d[2].d[1] ;
reg \in.a ;
reg \out.d.d[5].d[1] ;
reg \out.d.d[3].d[1] ;
reg \_out_a_BX_t[0] ;
wire \in.d.d[2].d[0] ;
reg \out.d.d[6].d[1] ;
reg \out.d.d[0].d[1] ;
wire \in.d.d[0].d[0] ;
reg \out.d.d[14].d[0] ;
reg \out.d.d[11].d[1] ;
reg \_en_X_t[0] ;
wire \in.d.d[10].d[0] ;
wire \out.a ;
reg \out.d.d[12].d[1] ;
wire reset_B;
wire \in.d.d[7].d[1] ;
wire \in.d.d[6].d[1] ;
wire \in.d.d[12].d[1] ;
wire \in.d.d[0].d[1] ;
wire \in.d.d[11].d[1] ;
reg \_reset_BXX[0] ;
reg \out.d.d[4].d[0] ;
reg \out.d.d[13].d[1] ;
reg \_en_X_f[0] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_t (.in(_out_a_B), .\out[0] (\_out_a_BX_f[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4 \inack_ctl (.y(\in.a ), .c1(_en), .c2(\in.v ), .c3(\out.v ), .pr_B(_reset_BX), .sr_B(_reset_BX));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \reset_bufarray (.in(_reset_BX), .\out[0] (\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X4 \in_v_buf (.y(\in.v ), .a(_in_v));
_0_0tmpl_0_0dataflow__neuro_0_0INV__X1 \out_a_inv (.y(_out_a_B), .a(\out.a ));
_0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4 \vc (.\in.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d[14].d[1] (\in.d.d[14].d[1] ), .out(_in_v));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_f (.in(_out_a_B), .\out[0] (\_out_a_BX_t[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1 \en_ctl (.y(_en), .c1(\in.a ), .p1(\out.v ));
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X1 \reset_buf (.y(_reset_BX), .a(reset_B));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_f (.in(_en), .\out[0] (\_en_X_f[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_t (.in(_en), .\out[0] (\_en_X_t[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[0] (.y(\out.d.d[0].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[0].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[1] (.y(\out.d.d[1].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[1].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[2] (.y(\out.d.d[2].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[2].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[3] (.y(\out.d.d[3].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[3].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[4] (.y(\out.d.d[4].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[4].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[5] (.y(\out.d.d[5].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[5].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[6] (.y(\out.d.d[6].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[6].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[7] (.y(\out.d.d[7].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[7].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[8] (.y(\out.d.d[8].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[8].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[9] (.y(\out.d.d[9].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[9].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[10] (.y(\out.d.d[10].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[10].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[11] (.y(\out.d.d[11].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[11].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[12] (.y(\out.d.d[12].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[12].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[13] (.y(\out.d.d[13].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[13].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[14] (.y(\out.d.d[14].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[14].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[0] (.y(\out.d.d[0].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[0].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[1] (.y(\out.d.d[1].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[1].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[2] (.y(\out.d.d[2].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[2].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[3] (.y(\out.d.d[3].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[3].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[4] (.y(\out.d.d[4].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[4].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[5] (.y(\out.d.d[5].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[5].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[6] (.y(\out.d.d[6].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[6].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[7] (.y(\out.d.d[7].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[7].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[8] (.y(\out.d.d[8].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[8].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[9] (.y(\out.d.d[9].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[9].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[10] (.y(\out.d.d[10].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[10].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[11] (.y(\out.d.d[11].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[11].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[12] (.y(\out.d.d[12].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[12].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[13] (.y(\out.d.d[13].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[13].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[14] (.y(\out.d.d[14].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[14].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
endmodule
//
// Verilog module for: buffer_15<>
//
module buffer__15(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v );
input \in.d.d[0].d[0] ;
input \in.d.d[0].d[1] ;
input \in.d.d[1].d[0] ;
input \in.d.d[1].d[1] ;
input \in.d.d[2].d[0] ;
input \in.d.d[2].d[1] ;
input \in.d.d[3].d[0] ;
input \in.d.d[3].d[1] ;
input \in.d.d[4].d[0] ;
input \in.d.d[4].d[1] ;
input \in.d.d[5].d[0] ;
input \in.d.d[5].d[1] ;
input \in.d.d[6].d[0] ;
input \in.d.d[6].d[1] ;
input \in.d.d[7].d[0] ;
input \in.d.d[7].d[1] ;
input \in.d.d[8].d[0] ;
input \in.d.d[8].d[1] ;
input \in.d.d[9].d[0] ;
input \in.d.d[9].d[1] ;
input \in.d.d[10].d[0] ;
input \in.d.d[10].d[1] ;
input \in.d.d[11].d[0] ;
input \in.d.d[11].d[1] ;
input \in.d.d[12].d[0] ;
input \in.d.d[12].d[1] ;
input \in.d.d[13].d[0] ;
input \in.d.d[13].d[1] ;
input \in.d.d[14].d[0] ;
input \in.d.d[14].d[1] ;
output \in.a ;
output \in.v ;
output \out.d.d[0].d[0] ;
output \out.d.d[0].d[1] ;
output \out.d.d[1].d[0] ;
output \out.d.d[1].d[1] ;
output \out.d.d[2].d[0] ;
output \out.d.d[2].d[1] ;
output \out.d.d[3].d[0] ;
output \out.d.d[3].d[1] ;
output \out.d.d[4].d[0] ;
output \out.d.d[4].d[1] ;
output \out.d.d[5].d[0] ;
output \out.d.d[5].d[1] ;
output \out.d.d[6].d[0] ;
output \out.d.d[6].d[1] ;
output \out.d.d[7].d[0] ;
output \out.d.d[7].d[1] ;
output \out.d.d[8].d[0] ;
output \out.d.d[8].d[1] ;
output \out.d.d[9].d[0] ;
output \out.d.d[9].d[1] ;
output \out.d.d[10].d[0] ;
output \out.d.d[10].d[1] ;
output \out.d.d[11].d[0] ;
output \out.d.d[11].d[1] ;
output \out.d.d[12].d[0] ;
output \out.d.d[12].d[1] ;
output \out.d.d[13].d[0] ;
output \out.d.d[13].d[1] ;
output \out.d.d[14].d[0] ;
output \out.d.d[14].d[1] ;
input \out.a ;
input \out.v ;
// -- signals ---
reg \out.d.d[2].d[0] ;
reg \out.d.d[14].d[1] ;
reg \out.d.d[4].d[0] ;
reg \out.d.d[0].d[1] ;
wire \in.d.d[8].d[1] ;
wire \in.d.d[7].d[0] ;
wire \in.d.d[1].d[0] ;
reg _reset_B;
reg \out.d.d[6].d[1] ;
reg \out.d.d[5].d[0] ;
reg \out.d.d[11].d[1] ;
reg \out.d.d[6].d[0] ;
reg \out.d.d[12].d[0] ;
wire \in.d.d[2].d[1] ;
wire \in.d.d[14].d[1] ;
wire \in.d.d[13].d[0] ;
wire \in.d.d[5].d[0] ;
wire \in.d.d[4].d[0] ;
reg \out.d.d[5].d[1] ;
reg \out.d.d[3].d[0] ;
wire \in.d.d[10].d[0] ;
wire \in.d.d[3].d[1] ;
wire \in.d.d[11].d[0] ;
reg \out.d.d[0].d[0] ;
reg \out.d.d[2].d[1] ;
wire \in.d.d[9].d[0] ;
wire \in.d.d[2].d[0] ;
wire \in.d.d[6].d[0] ;
wire \in.d.d[4].d[1] ;
wire \in.d.d[1].d[1] ;
reg \out.d.d[13].d[1] ;
reg \out.d.d[1].d[1] ;
reg \out.d.d[10].d[1] ;
wire \in.d.d[11].d[1] ;
wire \in.d.d[5].d[1] ;
reg \out.d.d[9].d[1] ;
wire \in.d.d[3].d[0] ;
wire \in.d.d[0].d[1] ;
wire \out.v ;
wire \in.d.d[12].d[0] ;
reg \out.d.d[3].d[1] ;
reg \out.d.d[7].d[1] ;
reg \out.d.d[14].d[0] ;
reg \out.d.d[11].d[0] ;
reg \out.d.d[4].d[1] ;
wire \in.d.d[9].d[1] ;
wire \in.d.d[7].d[1] ;
wire \out.a ;
reg \in.a ;
wire \in.d.d[13].d[1] ;
wire \in.d.d[10].d[1] ;
reg \out.d.d[12].d[1] ;
reg \out.d.d[10].d[0] ;
reg \out.d.d[1].d[0] ;
wire \in.d.d[6].d[1] ;
reg \in.v ;
wire \in.d.d[14].d[0] ;
reg \out.d.d[13].d[0] ;
wire \in.d.d[12].d[1] ;
reg \out.d.d[8].d[1] ;
reg \out.d.d[8].d[0] ;
reg \out.d.d[7].d[0] ;
reg \out.d.d[9].d[0] ;
wire \in.d.d[8].d[0] ;
wire \in.d.d[0].d[0] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4 \buffer_test (.\in.d.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d.d[14].d[1] (\in.d.d[14].d[1] ), .\in.a (\in.a ), .\in.v (\in.v ), .\out.d.d[0].d[0] (\out.d.d[0].d[0] ), .\out.d.d[0].d[1] (\out.d.d[0].d[1] ), .\out.d.d[1].d[0] (\out.d.d[1].d[0] ), .\out.d.d[1].d[1] (\out.d.d[1].d[1] ), .\out.d.d[2].d[0] (\out.d.d[2].d[0] ), .\out.d.d[2].d[1] (\out.d.d[2].d[1] ), .\out.d.d[3].d[0] (\out.d.d[3].d[0] ), .\out.d.d[3].d[1] (\out.d.d[3].d[1] ), .\out.d.d[4].d[0] (\out.d.d[4].d[0] ), .\out.d.d[4].d[1] (\out.d.d[4].d[1] ), .\out.d.d[5].d[0] (\out.d.d[5].d[0] ), .\out.d.d[5].d[1] (\out.d.d[5].d[1] ), .\out.d.d[6].d[0] (\out.d.d[6].d[0] ), .\out.d.d[6].d[1] (\out.d.d[6].d[1] ), .\out.d.d[7].d[0] (\out.d.d[7].d[0] ), .\out.d.d[7].d[1] (\out.d.d[7].d[1] ), .\out.d.d[8].d[0] (\out.d.d[8].d[0] ), .\out.d.d[8].d[1] (\out.d.d[8].d[1] ), .\out.d.d[9].d[0] (\out.d.d[9].d[0] ), .\out.d.d[9].d[1] (\out.d.d[9].d[1] ), .\out.d.d[10].d[0] (\out.d.d[10].d[0] ), .\out.d.d[10].d[1] (\out.d.d[10].d[1] ), .\out.d.d[11].d[0] (\out.d.d[11].d[0] ), .\out.d.d[11].d[1] (\out.d.d[11].d[1] ), .\out.d.d[12].d[0] (\out.d.d[12].d[0] ), .\out.d.d[12].d[1] (\out.d.d[12].d[1] ), .\out.d.d[13].d[0] (\out.d.d[13].d[0] ), .\out.d.d[13].d[1] (\out.d.d[13].d[1] ), .\out.d.d[14].d[0] (\out.d.d[14].d[0] ), .\out.d.d[14].d[1] (\out.d.d[14].d[1] ), .\out.a (\out.a ), .\out.v (\out.v ), .reset_B(_reset_B));
endmodule

29
test/unit_tests/buffer_token/run/prsim.out
View File

@@ -1,29 +0,0 @@
t.a._out_a_B t.in.r t.in.a t.out.r t.a._en t.a.inack_ctl._y t.out.a t.a.buf_func._y
[0] code starts
7093 t.in.r : 0
7093 t.out.a : 0
17560 t.a._out_a_B : 1 [by t.out.a:=0]
17560 Reset : 0
17562 t.a.reset_buf._y : 1 [by Reset:=0]
22315 t.a._reset_BX : 0 [by t.a.reset_buf._y:=1]
22429 t.a.inack_ctl._y : 1 [by t.a._reset_BX:=0]
23452 t.a.buf_func._y : 1 [by t.a._reset_BX:=0]
25178 t.out.r : 0 [by t.a.buf_func._y:=1]
87795 t.in.a : 0 [by t.a.inack_ctl._y:=1]
87834 t.a._en : 1 [by t.in.a:=0]
87834 Reset : 1
87849 t.a.reset_buf._y : 0 [by Reset:=1]
88340 t.a._reset_BX : 1 [by t.a.reset_buf._y:=0]
[1] reset done
----------------------------------------------------------------------------------------------------
88340 t.in.r : 1
88353 t.a.buf_func._y : 0 [by t.in.r:=1]
88393 t.out.r : 1 [by t.a.buf_func._y:=0]
88808 t.a.inack_ctl._y : 0 [by t.out.r:=1]
88828 t.in.a : 1 [by t.a.inack_ctl._y:=0]
94889 t.a._en : 0 [by t.in.a:=1]
94889 t.out.a : 1
94936 t.a._out_a_B : 0 [by t.out.a:=1]
94952 t.a.buf_func._y : 1 [by t.a._out_a_B:=0]
139050 t.out.r : 0 [by t.a.buf_func._y:=1]

43
test/unit_tests/buffer_token/test.act
View File

@@ -1,43 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc buffer_token_test(a1of1 in; a1of1 out)
{
buffer_t a(.in = in, .out = out);
a.supply.vdd = Vdd;
a.supply.vss = GND;
a.reset_B = Reset;
}
buffer_token_test t;

20
test/unit_tests/buffer_token/test.prsim
View File

@@ -1,20 +0,0 @@
watchall
system "echo '[0] code starts'"
set t.in.r 0
set t.out.a 0
cycle
set Reset 0
cycle
status X
mode run
set Reset 1
cycle
system "echo '[1] reset done'"
system "echo '----------------------------------------------------------------------------------------------------'"
set t.in.r 1
cycle
assert t.out.r 1
set t.out.a 1
cycle
assert t.in.a 1

4
test/unit_tests/ctree_15/run/prsim.out
View File

@@ -1,4 +0,0 @@
t.ctree_test.tmp[22] t.ctree_test.C2Els[0]._y t.ctree_test.tmp[17] t.in[14] t.in[4] t.in[2] t.in[8] t.in[13] t.ctree_test.tmp[21] t.ctree_test.tmp[23] t.out t.in[12] t.in[6] t.in[7] t.in[10] t.in[5] t.ctree_test.tmp[19] t.ctree_test.tmp[18] t.ctree_test.C3Els[0]._y t.in[3] t.ctree_test.tmp[24] t.ctree_test.C3Els[2]._y t.ctree_test.C2Els[4]._y t.in[0] t.in[1] t.ctree_test.tmp[15] t.ctree_test.tmp[16] t.in[11] t.ctree_test.tmp[20] t.ctree_test.C2Els[7]._y t.in[9] t.ctree_test.C2Els[2]._y t.ctree_test.C2Els[1]._y t.ctree_test.C2Els[6]._y t.ctree_test.C2Els[5]._y t.ctree_test.C2Els[3]._y t.ctree_test.C3Els[1]._y
[0] starting test all 1
[1] starting test all 0
[2] testing state holding

139
test/unit_tests/ctree_15/run/test.prs
View File

@@ -1,139 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
~"t.ctree_test.C2Els[0].c1"&~"t.ctree_test.C2Els[0].c2"->"t.ctree_test.C2Els[0]._y"+
"t.ctree_test.C2Els[0].c1"&"t.ctree_test.C2Els[0].c2"->"t.ctree_test.C2Els[0]._y"-
"t.ctree_test.C2Els[0]._y"->"t.ctree_test.C2Els[0].y"-
~("t.ctree_test.C2Els[0]._y")->"t.ctree_test.C2Els[0].y"+
~"t.ctree_test.C2Els[1].c1"&~"t.ctree_test.C2Els[1].c2"->"t.ctree_test.C2Els[1]._y"+
"t.ctree_test.C2Els[1].c1"&"t.ctree_test.C2Els[1].c2"->"t.ctree_test.C2Els[1]._y"-
"t.ctree_test.C2Els[1]._y"->"t.ctree_test.C2Els[1].y"-
~("t.ctree_test.C2Els[1]._y")->"t.ctree_test.C2Els[1].y"+
~"t.ctree_test.C2Els[2].c1"&~"t.ctree_test.C2Els[2].c2"->"t.ctree_test.C2Els[2]._y"+
"t.ctree_test.C2Els[2].c1"&"t.ctree_test.C2Els[2].c2"->"t.ctree_test.C2Els[2]._y"-
"t.ctree_test.C2Els[2]._y"->"t.ctree_test.C2Els[2].y"-
~("t.ctree_test.C2Els[2]._y")->"t.ctree_test.C2Els[2].y"+
~"t.ctree_test.C2Els[3].c1"&~"t.ctree_test.C2Els[3].c2"->"t.ctree_test.C2Els[3]._y"+
"t.ctree_test.C2Els[3].c1"&"t.ctree_test.C2Els[3].c2"->"t.ctree_test.C2Els[3]._y"-
"t.ctree_test.C2Els[3]._y"->"t.ctree_test.C2Els[3].y"-
~("t.ctree_test.C2Els[3]._y")->"t.ctree_test.C2Els[3].y"+
~"t.ctree_test.C2Els[4].c1"&~"t.ctree_test.C2Els[4].c2"->"t.ctree_test.C2Els[4]._y"+
"t.ctree_test.C2Els[4].c1"&"t.ctree_test.C2Els[4].c2"->"t.ctree_test.C2Els[4]._y"-
"t.ctree_test.C2Els[4]._y"->"t.ctree_test.C2Els[4].y"-
~("t.ctree_test.C2Els[4]._y")->"t.ctree_test.C2Els[4].y"+
~"t.ctree_test.C2Els[5].c1"&~"t.ctree_test.C2Els[5].c2"->"t.ctree_test.C2Els[5]._y"+
"t.ctree_test.C2Els[5].c1"&"t.ctree_test.C2Els[5].c2"->"t.ctree_test.C2Els[5]._y"-
"t.ctree_test.C2Els[5]._y"->"t.ctree_test.C2Els[5].y"-
~("t.ctree_test.C2Els[5]._y")->"t.ctree_test.C2Els[5].y"+
~"t.ctree_test.C2Els[6].c1"&~"t.ctree_test.C2Els[6].c2"->"t.ctree_test.C2Els[6]._y"+
"t.ctree_test.C2Els[6].c1"&"t.ctree_test.C2Els[6].c2"->"t.ctree_test.C2Els[6]._y"-
"t.ctree_test.C2Els[6]._y"->"t.ctree_test.C2Els[6].y"-
~("t.ctree_test.C2Els[6]._y")->"t.ctree_test.C2Els[6].y"+
~"t.ctree_test.C2Els[7].c1"&~"t.ctree_test.C2Els[7].c2"->"t.ctree_test.C2Els[7]._y"+
"t.ctree_test.C2Els[7].c1"&"t.ctree_test.C2Els[7].c2"->"t.ctree_test.C2Els[7]._y"-
"t.ctree_test.C2Els[7]._y"->"t.ctree_test.C2Els[7].y"-
~("t.ctree_test.C2Els[7]._y")->"t.ctree_test.C2Els[7].y"+
~"t.ctree_test.C3Els[0].c1"&~"t.ctree_test.C3Els[0].c2"&~"t.ctree_test.C3Els[0].c3"->"t.ctree_test.C3Els[0]._y"+
"t.ctree_test.C3Els[0].c1"&"t.ctree_test.C3Els[0].c2"&"t.ctree_test.C3Els[0].c3"->"t.ctree_test.C3Els[0]._y"-
"t.ctree_test.C3Els[0]._y"->"t.ctree_test.C3Els[0].y"-
~("t.ctree_test.C3Els[0]._y")->"t.ctree_test.C3Els[0].y"+
~"t.ctree_test.C3Els[1].c1"&~"t.ctree_test.C3Els[1].c2"&~"t.ctree_test.C3Els[1].c3"->"t.ctree_test.C3Els[1]._y"+
"t.ctree_test.C3Els[1].c1"&"t.ctree_test.C3Els[1].c2"&"t.ctree_test.C3Els[1].c3"->"t.ctree_test.C3Els[1]._y"-
"t.ctree_test.C3Els[1]._y"->"t.ctree_test.C3Els[1].y"-
~("t.ctree_test.C3Els[1]._y")->"t.ctree_test.C3Els[1].y"+
~"t.ctree_test.C3Els[2].c1"&~"t.ctree_test.C3Els[2].c2"&~"t.ctree_test.C3Els[2].c3"->"t.ctree_test.C3Els[2]._y"+
"t.ctree_test.C3Els[2].c1"&"t.ctree_test.C3Els[2].c2"&"t.ctree_test.C3Els[2].c3"->"t.ctree_test.C3Els[2]._y"-
"t.ctree_test.C3Els[2]._y"->"t.ctree_test.C3Els[2].y"-
~("t.ctree_test.C3Els[2]._y")->"t.ctree_test.C3Els[2].y"+
= "t.ctree_test.tmp[15]" "t.ctree_test.C2Els[6].c1"
= "t.ctree_test.tmp[15]" "t.ctree_test.C2Els[0].y"
= "t.ctree_test.tmp[16]" "t.ctree_test.C2Els[6].c2"
= "t.ctree_test.tmp[16]" "t.ctree_test.C2Els[1].y"
= "t.ctree_test.tmp[17]" "t.ctree_test.C2Els[7].c1"
= "t.ctree_test.tmp[17]" "t.ctree_test.C2Els[2].y"
= "t.ctree_test.tmp[18]" "t.ctree_test.C2Els[7].c2"
= "t.ctree_test.tmp[18]" "t.ctree_test.C2Els[3].y"
= "t.ctree_test.tmp[19]" "t.ctree_test.C3Els[1].c1"
= "t.ctree_test.tmp[19]" "t.ctree_test.C2Els[4].y"
= "t.ctree_test.tmp[20]" "t.ctree_test.C3Els[1].c2"
= "t.ctree_test.tmp[20]" "t.ctree_test.C2Els[5].y"
= "t.ctree_test.tmp[21]" "t.ctree_test.C3Els[1].c3"
= "t.ctree_test.tmp[21]" "t.ctree_test.C3Els[0].y"
= "t.ctree_test.tmp[22]" "t.ctree_test.C3Els[2].c1"
= "t.ctree_test.tmp[22]" "t.ctree_test.C2Els[6].y"
= "t.ctree_test.tmp[23]" "t.ctree_test.C3Els[2].c2"
= "t.ctree_test.tmp[23]" "t.ctree_test.C2Els[7].y"
= "t.ctree_test.tmp[24]" "t.ctree_test.C3Els[2].c3"
= "t.ctree_test.tmp[24]" "t.ctree_test.C3Els[1].y"
= "t.ctree_test.supply.vdd" "t.ctree_test.C3Els[2].vdd"
= "t.ctree_test.supply.vdd" "t.ctree_test.C3Els[1].vdd"
= "t.ctree_test.supply.vdd" "t.ctree_test.C3Els[0].vdd"
= "t.ctree_test.supply.vdd" "t.ctree_test.C2Els[7].vdd"
= "t.ctree_test.supply.vdd" "t.ctree_test.C2Els[6].vdd"
= "t.ctree_test.supply.vdd" "t.ctree_test.C2Els[5].vdd"
= "t.ctree_test.supply.vdd" "t.ctree_test.C2Els[4].vdd"
= "t.ctree_test.supply.vdd" "t.ctree_test.C2Els[3].vdd"
= "t.ctree_test.supply.vdd" "t.ctree_test.C2Els[2].vdd"
= "t.ctree_test.supply.vdd" "t.ctree_test.C2Els[1].vdd"
= "t.ctree_test.supply.vdd" "t.ctree_test.C2Els[0].vdd"
= "t.ctree_test.supply.vss" "t.ctree_test.C3Els[2].vss"
= "t.ctree_test.supply.vss" "t.ctree_test.C3Els[1].vss"
= "t.ctree_test.supply.vss" "t.ctree_test.C3Els[0].vss"
= "t.ctree_test.supply.vss" "t.ctree_test.C2Els[7].vss"
= "t.ctree_test.supply.vss" "t.ctree_test.C2Els[6].vss"
= "t.ctree_test.supply.vss" "t.ctree_test.C2Els[5].vss"
= "t.ctree_test.supply.vss" "t.ctree_test.C2Els[4].vss"
= "t.ctree_test.supply.vss" "t.ctree_test.C2Els[3].vss"
= "t.ctree_test.supply.vss" "t.ctree_test.C2Els[2].vss"
= "t.ctree_test.supply.vss" "t.ctree_test.C2Els[1].vss"
= "t.ctree_test.supply.vss" "t.ctree_test.C2Els[0].vss"
= "t.ctree_test.in[0]" "t.ctree_test.C2Els[0].c1"
= "t.ctree_test.in[0]" "t.ctree_test.tmp[0]"
= "t.ctree_test.in[1]" "t.ctree_test.C2Els[0].c2"
= "t.ctree_test.in[1]" "t.ctree_test.tmp[1]"
= "t.ctree_test.in[2]" "t.ctree_test.C2Els[1].c1"
= "t.ctree_test.in[2]" "t.ctree_test.tmp[2]"
= "t.ctree_test.in[3]" "t.ctree_test.C2Els[1].c2"
= "t.ctree_test.in[3]" "t.ctree_test.tmp[3]"
= "t.ctree_test.in[4]" "t.ctree_test.C2Els[2].c1"
= "t.ctree_test.in[4]" "t.ctree_test.tmp[4]"
= "t.ctree_test.in[5]" "t.ctree_test.C2Els[2].c2"
= "t.ctree_test.in[5]" "t.ctree_test.tmp[5]"
= "t.ctree_test.in[6]" "t.ctree_test.C2Els[3].c1"
= "t.ctree_test.in[6]" "t.ctree_test.tmp[6]"
= "t.ctree_test.in[7]" "t.ctree_test.C2Els[3].c2"
= "t.ctree_test.in[7]" "t.ctree_test.tmp[7]"
= "t.ctree_test.in[8]" "t.ctree_test.C2Els[4].c1"
= "t.ctree_test.in[8]" "t.ctree_test.tmp[8]"
= "t.ctree_test.in[9]" "t.ctree_test.C2Els[4].c2"
= "t.ctree_test.in[9]" "t.ctree_test.tmp[9]"
= "t.ctree_test.in[10]" "t.ctree_test.C2Els[5].c1"
= "t.ctree_test.in[10]" "t.ctree_test.tmp[10]"
= "t.ctree_test.in[11]" "t.ctree_test.C2Els[5].c2"
= "t.ctree_test.in[11]" "t.ctree_test.tmp[11]"
= "t.ctree_test.in[12]" "t.ctree_test.C3Els[0].c1"
= "t.ctree_test.in[12]" "t.ctree_test.tmp[12]"
= "t.ctree_test.in[13]" "t.ctree_test.C3Els[0].c2"
= "t.ctree_test.in[13]" "t.ctree_test.tmp[13]"
= "t.ctree_test.in[14]" "t.ctree_test.C3Els[0].c3"
= "t.ctree_test.in[14]" "t.ctree_test.tmp[14]"
= "t.ctree_test.out" "t.ctree_test.C3Els[2].y"
= "t.ctree_test.out" "t.ctree_test.tmp[25]"
= "Vdd" "t.ctree_test.supply.vdd"
= "GND" "t.ctree_test.supply.vss"
= "t.out" "t.ctree_test.out"
= "t.in[0]" "t.ctree_test.in[0]"
= "t.in[1]" "t.ctree_test.in[1]"
= "t.in[2]" "t.ctree_test.in[2]"
= "t.in[3]" "t.ctree_test.in[3]"
= "t.in[4]" "t.ctree_test.in[4]"
= "t.in[5]" "t.ctree_test.in[5]"
= "t.in[6]" "t.ctree_test.in[6]"
= "t.in[7]" "t.ctree_test.in[7]"
= "t.in[8]" "t.ctree_test.in[8]"
= "t.in[9]" "t.ctree_test.in[9]"
= "t.in[10]" "t.ctree_test.in[10]"
= "t.in[11]" "t.ctree_test.in[11]"
= "t.in[12]" "t.ctree_test.in[12]"
= "t.in[13]" "t.ctree_test.in[13]"
= "t.in[14]" "t.ctree_test.in[14]"

41
test/unit_tests/ctree_15/test.act
View File

@@ -1,41 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/treegates.act";
import globals;
open tmpl::dataflow_neuro;
defproc ctree_15 (bool? in[15]; bool! out){
ctree<15> ctree_test(.in=in, .out=out);
ctree_test.supply.vss = GND;
ctree_test.supply.vdd = Vdd;
}
ctree_15 t;

62
test/unit_tests/ctree_15/test.prsim
View File

@@ -1,62 +0,0 @@
system "echo '[0] starting test all 1'"
set t.in[0] 1
set t.in[1] 1
set t.in[2] 1
set t.in[3] 1
set t.in[4] 1
set t.in[5] 1
set t.in[6] 1
set t.in[7] 1
set t.in[8] 1
set t.in[9] 1
set t.in[10] 1
set t.in[11] 1
set t.in[12] 1
set t.in[13] 1
set t.in[14] 1
cycle
mode run
assert t.out 1
system "echo '[1] starting test all 0'"
set t.in[0] 0
set t.in[1] 0
set t.in[2] 0
set t.in[3] 0
set t.in[4] 0
set t.in[5] 0
set t.in[6] 0
set t.in[7] 0
set t.in[8] 0
set t.in[9] 0
set t.in[10] 0
set t.in[11] 0
set t.in[12] 0
set t.in[13] 0
set t.in[14] 0
cycle
mode run
assert t.out 0
system "echo '[2] testing state holding'"
set t.in[0] 0
set t.in[1] 0
set t.in[2] 0
set t.in[3] 0
set t.in[4] 0
set t.in[5] 1
set t.in[6] 0
set t.in[7] 0
set t.in[8] 0
set t.in[9] 0
set t.in[10] 0
set t.in[11] 0
set t.in[12] 0
set t.in[13] 0
set t.in[14] 0
cycle
mode run
assert t.out 0

47
test/unit_tests/decoder_2d_dly_8_16/test.act
View File

@@ -1,47 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import globals;
open tmpl::dataflow_neuro;
defproc decoder_2d_dly_8_16(avMx1of2<3+4> in; bool? outx[8], outy[16], dly_cfg[4])
{
bool _reset_B;
prs {
Reset => _reset_B-
}
decoder_2d_dly<3,4,8,16,4> b(.in = in, .outx = outx, .outy = outy, .dly_cfg = dly_cfg);
b.supply.vdd = Vdd;
b.supply.vss = GND;
b.reset_B = _reset_B;
}
decoder_2d_dly_8_16 b;

59
test/unit_tests/decoder_2d_dly_8_16/test.prsim
View File

@@ -1,59 +0,0 @@
watchall
set-qdi-channel-neutral "b.in" 7
set b.b.addr_buf.out.a 0
set Reset 0
# Set delay config lines
set b.dly_cfg[0] 1
set b.dly_cfg[1] 1
set b.dly_cfg[2] 1
set b.dly_cfg[3] 1
cycle
system "echo '[] set Reset 1'"
set Reset 1
cycle
system "echo '[] set Reset 0'"
set Reset 0
mode run
cycle
system "echo '[] Sending packet in'"
set-qdi-channel-valid "b.in" 7 127
cycle
assert b.in.a 1
assert b.in.v 1
# system "echo '[]' Setting ack from DLY high"
# set b.b.addr_buf.out.a 1
cycle
assert b.outx[0] 0
assert b.outx[1] 0
assert b.outx[2] 0
assert b.outx[3] 0
assert b.outx[4] 0
assert b.outx[5] 0
assert b.outx[6] 0
assert b.outx[7] 0
assert b.outy[0] 0
assert b.outy[1] 0
assert b.outy[2] 0
assert b.outy[3] 0
assert b.outy[4] 0
assert b.outy[5] 0
assert b.outy[6] 0
assert b.outy[7] 0
assert b.outy[8] 0
assert b.outy[9] 0
assert b.outy[10] 0
assert b.outy[11] 0
assert b.outy[12] 0
assert b.outy[13] 0
assert b.outy[14] 0
assert b.outy[15] 0

52
test/unit_tests/decoder_2d_dly_and_2_4/test.act
View File

@@ -1,52 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import globals;
open tmpl::dataflow_neuro;
defproc decoder_2d_dly_and_2_4(avMx1of2<1+2> in; bool? out[2*4], dly_cfg[4])
{
bool _reset_B;
prs {
Reset => _reset_B-
}
decoder_2d_dly<1,2,2,4,4> de(.in = in, .dly_cfg = dly_cfg);
de.supply.vdd = Vdd;
de.supply.vss = GND;
de.reset_B = _reset_B;
and_grid<2,4> ag(.inx = de.outx, .iny = de.outy, .out = out);
ag.supply.vdd = Vdd;
ag.supply.vss = GND;
}
decoder_2d_dly_and_2_4 t;

57
test/unit_tests/decoder_2d_dly_and_2_4/test.prsim
View File

@@ -1,57 +0,0 @@
watchall
set-qdi-channel-neutral "t.in" 3
set Reset 0
# Set delay config lines
set t.dly_cfg[0] 1
set t.dly_cfg[1] 1
set t.dly_cfg[2] 1
set t.dly_cfg[3] 1
cycle
system "echo '[] set Reset 1'"
set Reset 1
cycle
system "echo '[] set Reset 0'"
set Reset 0
mode run
cycle
system "echo '[] Sending packet in'"
set-qdi-channel-valid "t.in" 3 7
cycle
assert t.in.a 1
assert t.in.v 1
# system "echo '[]' Setting ack from DLY high"
# set b.b.addr_buf.out.a 1
# cycle
# assert b.outx[0] 0
# assert b.outx[1] 0
# assert b.outx[2] 0
# assert b.outx[3] 0
# assert b.outx[4] 0
# assert b.outx[5] 0
# assert b.outx[6] 0
# assert b.outx[7] 0
# assert b.outy[0] 0
# assert b.outy[1] 0
# assert b.outy[2] 0
# assert b.outy[3] 0
# assert b.outy[4] 0
# assert b.outy[5] 0
# assert b.outy[6] 0
# assert b.outy[7] 0
# assert b.outy[8] 0
# assert b.outy[9] 0
# assert b.outy[10] 0
# assert b.outy[11] 0
# assert b.outy[12] 0
# assert b.outy[13] 0
# assert b.outy[14] 0
# assert b.outy[15] 0

73
test/unit_tests/decoder_2d_hs/test.act
View File

@@ -1,73 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc decoder_2d_hs_2x4 (avMx1of2<3> in; a1of1 out[8]){
bool _reset_B;
prs {
Reset => _reset_B-
}
power supply;
supply.vdd = Vdd;
supply.vss = GND;
decoder_2d_hs<1,2,2,4> decoder(.in = in, .out = out,
.reset_B = _reset_B, .supply = supply);
// model the synapse as having automatic pulldown of ack.
INV_X1 synapses[8];
PULLDOWN_X4 synapses2[8];
(i:8:
synapses[i].a = decoder.out[i].r;
synapses2[i].a = synapses[i].y;
synapses2[i].y = decoder.out[i].a;
synapses[i].vss = supply.vss;
synapses[i].vdd = supply.vdd;
synapses2[i].vss = supply.vss;
synapses2[i].vdd = supply.vdd;
)
}
// fifo_decoder_neurons_encoder_fifo e;
decoder_2d_hs_2x4 e;

153
test/unit_tests/decoder_2d_hs/test.prsim
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@@ -1,153 +0,0 @@
watchall
set e.out[0].a 0
set e.out[1].a 0
set e.out[2].a 0
set e.out[3].a 0
set e.out[4].a 0
set e.out[5].a 0
set e.out[6].a 0
set e.out[7].a 0
set-qdi-channel-neutral "e.in" 3
set Reset 1
cycle
mode run
system "echo '[] Set reset 0'"
status X
set Reset 0
cycle
system "echo '[] Sending in a 7 packet'"
set-qdi-channel-valid "e.in" 3 7
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 1
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
system "echo '[] Synapse [7] gives ack'"
set e.out[7].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 0
assert e.in.v 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
system "echo '[] Sending in a 5 packet'"
set-qdi-channel-valid "e.in" 3 5
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 1
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
system "echo '[] Synapse [5] gives ack'"
set e.out[5].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 0
assert e.in.v 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
system "echo '[] Sending in a 1 packet'"
set-qdi-channel-valid "e.in" 3 1
cycle
assert e.out[0].r 0
assert e.out[1].r 1
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 1
assert e.in.v 1
system "echo '[] Synapse [5] gives ack'"
set e.out[1].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.out[0].a 0
assert e.out[1].a 0
assert e.out[2].a 0
assert e.out[3].a 0
assert e.out[4].a 0
assert e.out[5].a 0
assert e.out[6].a 0
assert e.out[7].a 0
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
cycle
assert e.in.a 0
assert e.in.v 0

104
test/unit_tests/decoder_2d_hybrid/test.act
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@@ -1,104 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc decoder_2d_hybrid_2x4 (avMx1of2<3> in; a1of1 out[8]; bool? dly_cfg[4], hs_en, ack_disable){
bool _reset_B;
prs {
Reset => _reset_B-
}
power supply;
supply.vdd = Vdd;
supply.vss = GND;
decoder_2d_hybrid<1,2,2,4,4> decoder(.in = in, .dly_cfg = dly_cfg, .hs_en = hs_en, .ack_disable = ack_disable,
.reset_B = _reset_B, .supply = supply);
// Dummy synapses to perform the handshaking.
// They consist of a grid of ANDs and pulldowns, and have the "synapses" exposed,\
// which would be the pulse extenders (which we thus short here)
decoder_2d_synapse_hs<2,4> syn_hs(.in_req_x = decoder.out_req_x, .in_req_y = decoder.out_req_y,
.out_ackB_decoder = decoder.in_ackB_decoder,
.to_pu = decoder.to_pu,
.synapses = out,
.supply = supply);
// (i:8: syn_hs.synapses[i].a = syn_hs.synapses[i].r;)
// // model the synapse as having automatic pulldown of ack.
// INV_X1 synapses[8];
// AND2_X1 req_and2s[8];
// pint index;
// PULLDOWN_X4 synapses2[8];
// (i:4:
// (j:2:
// index = i + 4*j;
// req_and2s[index].a = decoder.out_req_x[index];
// req_and2s[index].b = decoder.out_req_y[index];
// // synapses[index].a = decoder.out[index].r;
// synapses[index].a = req_and2s[index].y;
// synapses2[index].a = synapses[index].y;
// synapses2[index].y = decoder.out[index].a;
// synapses[index].vss = supply.vss;
// synapses[index].vdd = supply.vdd;
// synapses2[index].vss = supply.vss;
// synapses2[index].vdd = supply.vdd;
// req_and2s[index].vss = supply.vss;
// req_and2s[index].vdd = supply.vdd;
// )
// )
}
// fifo_decoder_neurons_encoder_fifo e;
decoder_2d_hybrid_2x4 e;

342
test/unit_tests/decoder_2d_hybrid/test.prsim
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@@ -1,342 +0,0 @@
watchall
set e.out[0].a 0
set e.out[1].a 0
set e.out[2].a 0
set e.out[3].a 0
set e.out[4].a 0
set e.out[5].a 0
set e.out[6].a 0
set e.out[7].a 0
cycle
set e.dly_cfg[0] 0
set e.dly_cfg[1] 0
set e.dly_cfg[2] 0
set e.dly_cfg[3] 0
set e.hs_en 1
set e.ack_disable 0
set-qdi-channel-neutral "e.in" 3
set Reset 1
cycle
mode run
system "echo '[] Set reset 0'"
status X
set Reset 0
cycle
system "echo '[] Sending in a 7 packet'"
set-qdi-channel-valid "e.in" 3 7
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 1
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
system "echo '[] Synapse [7] gives ack'"
set e.out[7].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 0
assert e.in.v 0
set e.out[0].a 0
set e.out[1].a 0
set e.out[2].a 0
set e.out[3].a 0
set e.out[4].a 0
set e.out[5].a 0
set e.out[6].a 0
set e.out[7].a 0
cycle
system "echo '[] Sending in a 5 packet'"
set-qdi-channel-valid "e.in" 3 5
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 1
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
system "echo '[] Synapse [5] gives ack'"
set e.out[5].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 0
assert e.in.v 0
set e.out[0].a 0
set e.out[1].a 0
set e.out[2].a 0
set e.out[3].a 0
set e.out[4].a 0
set e.out[5].a 0
set e.out[6].a 0
set e.out[7].a 0
cycle
system "echo '[] Sending in a 1 packet'"
set-qdi-channel-valid "e.in" 3 1
cycle
assert e.out[0].r 0
assert e.out[1].r 1
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 1
assert e.in.v 1
system "echo '[] Synapse [1] gives ack'"
set e.out[1].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
set e.out[0].a 0
set e.out[1].a 0
set e.out[2].a 0
set e.out[3].a 0
set e.out[4].a 0
set e.out[5].a 0
set e.out[6].a 0
set e.out[7].a 0
cycle
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input, enabling delays'"
set-qdi-channel-neutral "e.in" 3
cycle
assert e.in.a 0
assert e.in.v 0
system "echo '[] Enabling delays'"
cycle
set e.dly_cfg[0] 1
set e.dly_cfg[1] 1
set e.dly_cfg[2] 1
set e.dly_cfg[3] 1
system "echo '[] Sending in a 7 packet, with delays'"
set-qdi-channel-valid "e.in" 3 7
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 1
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
system "echo '[] Synapse [7] gives ack'"
set e.out[7].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 0
assert e.in.v 0
set e.out[0].a 0
set e.out[1].a 0
set e.out[2].a 0
set e.out[3].a 0
set e.out[4].a 0
set e.out[5].a 0
set e.out[6].a 0
set e.out[7].a 0
cycle
system "echo '[] Sending in a 5 packet'"
set-qdi-channel-valid "e.in" 3 5
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 1
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
system "echo '[] Synapse [5] gives ack'"
set e.out[5].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 0
assert e.in.v 0
set e.out[0].a 0
set e.out[1].a 0
set e.out[2].a 0
set e.out[3].a 0
set e.out[4].a 0
set e.out[5].a 0
set e.out[6].a 0
set e.out[7].a 0
cycle
system "echo '[] Sending in a 1 packet'"
set-qdi-channel-valid "e.in" 3 1
cycle
assert e.out[0].r 0
assert e.out[1].r 1
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
assert e.in.a 1
assert e.in.v 1
system "echo '[] Synapse [1] gives ack'"
set e.out[1].a 1
cycle
assert e.out[0].r 0
assert e.out[1].r 0
assert e.out[2].r 0
assert e.out[3].r 0
assert e.out[4].r 0
assert e.out[5].r 0
assert e.out[6].r 0
assert e.out[7].r 0
set e.out[0].a 0
set e.out[1].a 0
set e.out[2].a 0
set e.out[3].a 0
set e.out[4].a 0
set e.out[5].a 0
set e.out[6].a 0
set e.out[7].a 0
cycle
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input, disabling handshaking'"
set-qdi-channel-neutral "e.in" 3
cycle
assert e.in.a 0
assert e.in.v 0
set e.hs_en 0
cycle
system "echo '[] Sending in a 0, handshaking disabled'"
set-qdi-channel-valid "e.in" 3 0
cycle
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
cycle
assert e.in.a 0
assert e.in.v 0
system "echo '[] Sending in a 7, handshaking disabled'"
set-qdi-channel-valid "e.in" 3 7
cycle
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
cycle
assert e.in.a 0
assert e.in.v 0
system "echo '[] Sending in a 5, handshaking disabled'"
set-qdi-channel-valid "e.in" 3 5
cycle
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 3
cycle
assert e.in.a 0
assert e.in.v 0

41
test/unit_tests/delayprog_4/test.act
View File

@@ -1,41 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc delayprog_4 (bool? s[4], in; bool! out){
delayprog<4> dp(.in=in, .out=out, .s = s);
dp.supply.vss = GND;
dp.supply.vdd = Vdd;
}
delayprog_4 t;

42
test/unit_tests/delayprog_4/test.prsim
View File

@@ -1,42 +0,0 @@
watchall
system "echo '0'"
set t.in 0
set t.s[0] 1
set t.s[1] 1
set t.s[2] 1
set t.s[3] 1
cycle
mode run
# assert t.out 0
system "echo '[] setting high'"
set t.in 1
cycle
assert t.out 1
system "echo '[] setting low'"
set t.in 0
cycle
assert t.out 0
system "echo '[] setting configs low'"
set t.s[0] 0
set t.s[1] 0
set t.s[2] 0
set t.s[3] 0
cycle
assert t.out 0
system "echo '[] setting high'"
set t.in 1
cycle
assert t.out 1
system "echo '[] setting low'"
set t.in 0
cycle
assert t.out 0

49
test/unit_tests/demux_7/test.act
View File

@@ -1,49 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc demux_7 (avMx1of2<7> in; avMx1of2<7> out1; avMx1of2<7> out2; avMx1of2<1> cond){
demux<7> my_demux(.in=in, .out1=out1,.out2 = out2, .cond = cond);
//Low active Reset
bool _reset_B;
prs {
Reset => _reset_B-
}
my_demux.supply.vss = GND;
my_demux.supply.vdd = Vdd;
my_demux.reset_B = _reset_B;
}
demux_7 my_demux;

86
test/unit_tests/demux_7/test.prsim
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@@ -1,86 +0,0 @@
watchall
set-qdi-channel-neutral "my_demux.in" 7
set my_demux.out1.a 0
set my_demux.out1.v 0
set my_demux.out2.a 0
set my_demux.out2.v 0
set my_demux.cond.d.d[0].t 0
set my_demux.cond.d.d[0].f 0
cycle
system "echo 'System initialized'"
set Reset 0
cycle
system "echo 'System reset completed'"
status X
mode run
assert-qdi-channel-neutral "my_demux.out1" 7
assert-qdi-channel-neutral "my_demux.out2" 7
assert-qdi-channel-neutral "my_demux.in" 7
assert my_demux.cond.v 0
cycle
system "echo 'Output neutral checked'"
set my_demux.cond.d.d[0].t 0
set my_demux.cond.d.d[0].f 1
set-qdi-channel-valid "my_demux.in" 7 127
cycle
assert my_demux.in.v 1
assert my_demux.in.a 0
assert my_demux.cond.v 1
assert-qdi-channel-valid "my_demux.out1" 7 127
assert-qdi-channel-neutral "my_demux.out2" 7
set my_demux.out1.v 1
cycle
assert my_demux.in.a 1
set-qdi-channel-neutral "my_demux.in" 7
cycle
set my_demux.out1.a 1
system "echo 'First Cond Checked'"
set Reset 0
cycle
system "echo 'System reset completed'"
status X
mode run
assert-qdi-channel-neutral "my_demux.out1" 7
assert-qdi-channel-neutral "my_demux.out2" 7
assert-qdi-channel-neutral "my_demux.in" 7
cycle
system "echo 'Output neutral checked'"
set my_demux.cond.d.d[0].t 0
set my_demux.cond.d.d[0].f 0
set my_demux.out1.a 0
set my_demux.out1.v 0
set my_demux.out2.a 0
set my_demux.out2.v 0
cycle
set my_demux.cond.d.d[0].t 1
set my_demux.cond.d.d[0].f 0
set-qdi-channel-valid "my_demux.in" 7 100
cycle
assert my_demux.in.v 1
assert my_demux.in.a 0
assert my_demux.cond.v 1
assert-qdi-channel-valid "my_demux.out2" 7 100
set my_demux.out2.v 1
cycle
assert my_demux.in.a 1
set-qdi-channel-neutral "my_demux.in" 7
cycle
system "echo 'Second Cond Checked'"

49
test/unit_tests/demux_bit_7/test.act
View File

@@ -1,49 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc demux_bit_7 (avMx1of2<8> in; avMx1of2<7> out1; avMx1of2<7> out2){
demux_bit<7,0> my_demux(.in=in, .out1=out1,.out2 = out2);
//Low active Reset
bool _reset_B;
prs {
Reset => _reset_B-
}
my_demux.supply.vss = GND;
my_demux.supply.vdd = Vdd;
my_demux.reset_B = _reset_B;
}
demux_bit_7 my_demux;

77
test/unit_tests/demux_bit_7/test.prsim
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@@ -1,77 +0,0 @@
watchall
set-qdi-channel-neutral "my_demux.in" 8
set my_demux.out1.a 0
set my_demux.out1.v 0
set my_demux.out2.a 0
set my_demux.out2.v 0
set my_demux.in.d.d[0].t 0
set my_demux.in.d.d[0].f 0
cycle
system "echo 'System initialized'"
set Reset 0
cycle
system "echo 'System reset completed'"
status X
mode run
assert-qdi-channel-neutral "my_demux.out1" 7
assert-qdi-channel-neutral "my_demux.out2" 7
assert-qdi-channel-neutral "my_demux.in" 8
cycle
system "echo 'Output neutral checked'"
set-qdi-channel-valid "my_demux.in" 8 254
cycle
assert my_demux.in.v 1
assert my_demux.in.a 0
assert-qdi-channel-valid "my_demux.out1" 7 127
assert-qdi-channel-neutral "my_demux.out2" 7
set my_demux.out1.v 1
cycle
assert my_demux.in.a 1
set-qdi-channel-neutral "my_demux.in" 8
cycle
set my_demux.out1.a 1
system "echo 'First Cond Checked'"
set Reset 0
cycle
system "echo 'System reset completed'"
status X
mode run
assert-qdi-channel-neutral "my_demux.out1" 7
assert-qdi-channel-neutral "my_demux.out2" 7
assert-qdi-channel-neutral "my_demux.in" 8
cycle
system "echo 'Output neutral checked'"
set my_demux.out1.a 0
set my_demux.out1.v 0
set my_demux.out2.a 0
set my_demux.out2.v 0
cycle
set-qdi-channel-valid "my_demux.in" 8 101
cycle
assert my_demux.in.v 1
assert my_demux.in.a 0
assert-qdi-channel-valid "my_demux.out2" 7 50
set my_demux.out2.v 1
cycle
assert my_demux.in.a 1
set-qdi-channel-neutral "my_demux.in" 7
cycle
system "echo 'Second Cond Checked'"

54
test/unit_tests/demux_qdi2bd_1d/test.act
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@@ -1,54 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2024 University of Groningen - Ole Richter
* Copyright (c) 2024 University of Groningen - Paolo Gibertini
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc demux_qdi2bd_1d_test (avMx1of2<4> in; rbd<4> out[15]){
demux_qdi2bd_1d<15, 4> decoder_test(.in=in, .out=out);
//Low active Reset
bool _reset_B;
prs {
Reset => _reset_B-
}
decoder_test.supply.vss = GND;
decoder_test.supply.vdd = Vdd;
decoder_test.reset_B = _reset_B;
}
demux_qdi2bd_1d_test t;

73
test/unit_tests/demux_qdi2bd_1d/test.prsim
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@@ -1,73 +0,0 @@
set-qdi-channel-neutral "t.in" 4
set t.out[0].a 0
set t.out[1].a 0
set t.out[2].a 0
set t.out[3].a 0
set t.out[4].a 0
set t.out[5].a 0
set t.out[6].a 0
set t.out[7].a 0
set t.out[8].a 0
set t.out[9].a 0
set t.out[10].a 0
set t.out[11].a 0
set t.out[12].a 0
set t.out[13].a 0
set t.out[14].a 0
cycle
system "echo 'reset start'"
set Reset 0
cycle
system "echo 'reset completed'"
status X
mode run
assert-bd-channel-neutral "t.out[0]" 4
assert-bd-channel-neutral "t.out[1]" 4
assert-bd-channel-neutral "t.out[2]" 4
assert-bd-channel-neutral "t.out[3]" 4
assert-bd-channel-neutral "t.out[4]" 4
assert-bd-channel-neutral "t.out[5]" 4
assert-bd-channel-neutral "t.out[6]" 4
assert-bd-channel-neutral "t.out[7]" 4
assert-bd-channel-neutral "t.out[8]" 4
assert-bd-channel-neutral "t.out[9]" 4
assert-bd-channel-neutral "t.out[10]" 4
assert-bd-channel-neutral "t.out[11]" 4
assert-bd-channel-neutral "t.out[12]" 4
assert-bd-channel-neutral "t.out[13]" 4
assert-bd-channel-neutral "t.out[14]" 4
cycle
set-qdi-channel-valid "t.in" 4 5
cycle
assert t.in.v 1
assert-bd-channel-valid "t.out[0]" 4 0
set t.out[5].a 1
cycle
assert t.in.a 1
set-qdi-channel-neutral "t.in" 4
cycle
assert t.out[5].r 0
set t.in.a 0
cycle
assert-bd-channel-neutral "t.out[0]" 4
assert-bd-channel-neutral "t.out[1]" 4
assert-bd-channel-neutral "t.out[2]" 4
assert-bd-channel-neutral "t.out[3]" 4
assert-bd-channel-neutral "t.out[4]" 4
assert-bd-channel-neutral "t.out[5]" 4
assert-bd-channel-neutral "t.out[6]" 4
assert-bd-channel-neutral "t.out[7]" 4
assert-bd-channel-neutral "t.out[8]" 4
assert-bd-channel-neutral "t.out[9]" 4
assert-bd-channel-neutral "t.out[10]" 4
assert-bd-channel-neutral "t.out[11]" 4
assert-bd-channel-neutral "t.out[12]" 4
assert-bd-channel-neutral "t.out[13]" 4
assert-bd-channel-neutral "t.out[14]" 4
system "echo 'Finished'"

50
test/unit_tests/demux_td_2/test.act
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@@ -1,50 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc demux_2 (avMx1of2<2> in; avMx1of2<2> out; a1of1 token; avMx1of2<1> cond){
demux_td<2, false> my_demux(.in=in, .out=out,.token = token, .cond = cond);
//Low active Reset
bool _reset_B;
prs {
Reset => _reset_B-
}
my_demux.supply.vss = GND;
my_demux.supply.vdd = Vdd;
my_demux.reset_B = _reset_B;
}
demux_2 my_demux;

90
test/unit_tests/demux_td_2/test.prsim
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@@ -1,90 +0,0 @@
watchall
set-qdi-channel-neutral "my_demux.in" 2
set my_demux.out.a 0
set my_demux.out.v 0
set my_demux.token.a 0
set my_demux.token.r 0
set my_demux.cond.d.d[0].t 0
set my_demux.cond.d.d[0].f 0
cycle
system "echo '[]System initialized'"
set Reset 0
cycle
system "echo '[]System reset completed'"
status X
mode run
assert-qdi-channel-neutral "my_demux.out" 2
assert-qdi-channel-neutral "my_demux.in" 2
cycle
system "echo '[]Output neutral checked'"
set my_demux.cond.d.d[0].t 1
set my_demux.cond.d.d[0].f 0
set-qdi-channel-valid "my_demux.in" 2 3
cycle
assert my_demux.in.v 1
assert my_demux.in.a 0
assert-qdi-channel-valid "my_demux.out" 2 3
assert my_demux.token.a 0
set my_demux.out.v 1
cycle
assert my_demux.in.a 1
set-qdi-channel-neutral "my_demux.in" 2
cycle
set my_demux.out.a 1
cycle
set my_demux.out.v 0
assert my_demux.in.a 1
set-qdi-channel-neutral "my_demux.in" 2
system "echo '[]First Cond Checked'"
set my_demux.out.a 0
set my_demux.out.v 0
set my_demux.token.a 0
set my_demux.token.r 0
set my_demux.cond.d.d[0].t 0
set my_demux.cond.d.d[0].f 0
cycle
system "echo '[]System initialized'"
set my_demux.cond.d.d[0].t 0
set my_demux.cond.d.d[0].f 1
set-qdi-channel-valid "my_demux.in" 2 3
cycle
assert my_demux.in.v 1
assert my_demux.in.a 1
assert my_demux.token.r 1
set my_demux.token.a 1
cycle
assert my_demux.token.r 0
set my_demux.token.a 0
set-qdi-channel-neutral "my_demux.in" 2
cycle
assert my_demux.in.v 0
set my_demux.cond.d.d[0].t 0
set my_demux.cond.d.d[0].f 0
cycle
assert my_demux.in.a 0

50
test/unit_tests/demux_td_2_SIGN/test.act
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@@ -1,50 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc demux_2 (avMx1of2<2> in; avMx1of2<2> out; a1of1 token; avMx1of2<1> cond){
demux_td<2, true> my_demux(.in=in, .out=out,.token = token, .cond = cond);
//Low active Reset
bool _reset_B;
prs {
Reset => _reset_B-
}
my_demux.supply.vss = GND;
my_demux.supply.vdd = Vdd;
my_demux.reset_B = _reset_B;
}
demux_2 my_demux;

90
test/unit_tests/demux_td_2_SIGN/test.prsim
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@@ -1,90 +0,0 @@
watchall
set-qdi-channel-neutral "my_demux.in" 2
set my_demux.out.a 0
set my_demux.out.v 0
set my_demux.token.a 0
set my_demux.token.r 0
set my_demux.cond.d.d[0].t 0
set my_demux.cond.d.d[0].f 0
cycle
system "echo 'System initialized'"
set Reset 0
cycle
system "echo 'System reset completed'"
status X
mode run
assert-qdi-channel-neutral "my_demux.out" 2
assert-qdi-channel-neutral "my_demux.in" 2
cycle
system "echo 'Output neutral checked'"
set my_demux.cond.d.d[0].t 0
set my_demux.cond.d.d[0].f 1
set-qdi-channel-valid "my_demux.in" 2 3
cycle
assert my_demux.in.v 1
assert my_demux.in.a 0
assert-qdi-channel-valid "my_demux.out" 2 3
assert my_demux.token.a 0
assert my_demux.token.r 0
set my_demux.out.v 1
cycle
assert my_demux.in.a 1
set-qdi-channel-neutral "my_demux.in" 2
cycle
set my_demux.out.a 1
cycle
assert-qdi-channel-neutral "my_demux.out" 2
set my_demux.out.a 0
set my_demux.out.v 0
cycle
system "echo 'First Cond Checked'"
set my_demux.out.a 0
set my_demux.out.v 0
set my_demux.token.a 0
set my_demux.token.r 0
set my_demux.cond.d.d[0].t 0
set my_demux.cond.d.d[0].f 0
cycle
system "echo 'System initialized'"
set my_demux.cond.d.d[0].t 1
set my_demux.cond.d.d[0].f 0
set-qdi-channel-valid "my_demux.in" 2 3
cycle
assert my_demux.in.v 1
assert my_demux.in.a 1
assert my_demux.token.r 1
assert-qdi-channel-neutral "my_demux.out" 2
set my_demux.token.a 1
cycle
assert my_demux.token.r 0
set my_demux.token.a 0
set-qdi-channel-neutral "my_demux.in" 2
cycle
assert my_demux.in.v 0
set my_demux.cond.d.d[0].t 0
set my_demux.cond.d.d[0].f 0
cycle
assert my_demux.cond.v 0
assert my_demux.in.a 0

52
test/unit_tests/dropper_static/test.act
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@@ -1,52 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc dropper_static_7 (avMx1of2<7> in; avMx1of2<7> out; bool? drop){
bool _reset_B;
prs {
Reset => _reset_B-
}
power supply;
supply.vdd = Vdd;
supply.vss = GND;
dropper_static<7, true> b(.in = in, .out = out, .cond = drop, .supply = supply);
}
// fifo_decoder_neurons_encoder_fifo e;
dropper_static_7 b;

73
test/unit_tests/dropper_static/test.prsim
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@@ -1,73 +0,0 @@
watchall
set-qdi-channel-neutral "b.in" 7
set b.out.a 0
set b.out.v 0
set b.drop 0
cycle
mode run
system "echo '[] Set reset 0'"
status X
set Reset 0
cycle
status X
assert b.in.a 0
assert b.in.v 0
system "echo '[] Sending in valid data'"
set-qdi-channel-valid "b.in" 7 45
cycle
assert-qdi-channel-valid "b.out" 7 45
assert b.in.v 1
cycle
set b.out.a 1
cycle
assert b.in.a 1
assert b.in.v 1
system "echo '[] Removing data'"
set-qdi-channel-neutral "b.in" 7
cycle
assert-qdi-channel-neutral "b.out" 7
assert b.in.v 0
set b.out.a 0
cycle
assert b.in.a 0
system "echo '[] Sending in valid data'"
set-qdi-channel-valid "b.in" 7 37
cycle
assert-qdi-channel-valid "b.out" 7 37
assert b.in.v 1
cycle
set b.out.a 1
cycle
assert b.in.a 1
assert b.in.v 1
system "echo '[] Removing data'"
set-qdi-channel-neutral "b.in" 7
cycle
assert-qdi-channel-neutral "b.out" 7
assert b.in.v 0
set b.out.a 0
cycle
assert b.in.a 0
system "echo '[] Enabling drop'"
set b.drop 1
cycle
system "echo '[] Sending in valid data'"
set-qdi-channel-valid "b.in" 7 45
cycle
assert-qdi-channel-neutral "b.out" 7
assert b.in.v 1
assert b.in.a 1
system "echo '[] Removing data'"
set-qdi-channel-neutral "b.in" 7
cycle
assert-qdi-channel-neutral "b.out" 7
assert b.in.v 0
assert b.in.a 0

54
test/unit_tests/encoder1d_7/test.act
View File

@@ -1,54 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc encoder1d_simple_test(a1of1 in[7]; avMx1of2<3> out){
power supply;
supply.vss = GND;
supply.vdd = Vdd;
bool _reset_B;
prs {
Reset => _reset_B-
}
encoder1d_simple<3,7> e(.in = in, .supply = supply, .reset_B = _reset_B);
fifo<3, 5> fifo_post(.in = e.out, .out = out, .supply = supply, .reset_B = _reset_B);
}
encoder1d_simple_test e;

257
test/unit_tests/encoder1d_7/test.prsim
View File

@@ -1,257 +0,0 @@
watchall
system "echo '[] Set Reset 1'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.a 0
set e.out.v 0
set Reset 1
cycle
status X
system "echo '[] Set Reset 0'"
set Reset 0
cycle
status X
system "echo '[] Neuron 5 spikes'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 1
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 5
assert e.in[5].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.in[5].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 1 spikes'"
set e.in[0].r 0
set e.in[1].r 1
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 1
assert e.in[1].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.v 1
set e.out.a 1
cycle
assert e.in[1].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 5 spikes'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 1
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 5
assert e.in[5].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.in[5].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 1 spikes'"
set e.in[0].r 0
set e.in[1].r 1
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 1
assert e.in[1].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.v 1
set e.out.a 1
cycle
assert e.in[1].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 5 spikes'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 1
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 5
assert e.in[5].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.in[5].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 1 spikes'"
set e.in[0].r 0
set e.in[1].r 1
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 1
assert e.in[1].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.v 1
set e.out.a 1
cycle
assert e.in[1].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 6 spikes'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 1
cycle
assert-qdi-channel-valid "e.out" 3 6
assert e.in[6].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.in[6].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 1 spikes'"
set e.in[0].r 0
set e.in[1].r 1
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 1
assert e.in[1].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.v 1
set e.out.a 1
cycle
assert e.in[1].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0

61
test/unit_tests/encoder1d_bd/test.act
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@@ -1,61 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/primitives.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
pint N = 7;
pint Nc = std::ceil_log2(N);
pint N_BUFFERS = 5;
pint N_BD_DLY_CFG = 4;
defproc _encoder1d_bd (a1of1 in[N]; bd<Nc> out; bool? dly_cfg[N_BD_DLY_CFG]) {
bool _reset_B;
prs {
Reset => _reset_B-
}
power supply;
supply.vdd = Vdd;
supply.vss = GND;
encoder1d_bd<Nc, N, N_BUFFERS, N_BD_DLY_CFG> c(.in = in, .out = out, .dly_cfg = dly_cfg,
.reset_B = _reset_B, .supply = supply);
}
// fifo_decoder_neurons_encoder_fifo e;
_encoder1d_bd c;

82
test/unit_tests/encoder1d_bd/test.prsim
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@@ -1,82 +0,0 @@
watchall
set c.dly_cfg[0] 1
set c.dly_cfg[1] 1
set c.dly_cfg[2] 1
set c.dly_cfg[3] 1
set c.in[0].r 0
set c.in[1].r 0
set c.in[2].r 0
set c.in[3].r 0
set c.in[4].r 0
set c.in[5].r 0
set c.in[6].r 0
set c.out.a 0
set Reset 1
cycle
status X
system "echo '[] Set reset 0'"
mode run
set Reset 0
cycle
system "echo '[] Reset finished'"
status X
assert-bd-channel-neutral "c.out" 3
assert c.in[0].a 0
assert c.in[1].a 0
assert c.in[2].a 0
assert c.in[3].a 0
assert c.in[4].a 0
assert c.in[5].a 0
assert c.in[6].a 0
system "echo '[] Spiking 3'"
set c.in[3].r 1
cycle
assert c.in[3].a 1
set c.in[3].r 0
cycle
assert c.in[3].a 0
system "echo '[] Spiking 6'"
set c.in[6].r 1
cycle
assert c.in[6].a 1
set c.in[6].r 0
cycle
assert c.in[6].a 0
system "echo '[] Receive 3'"
assert-bd-channel-valid "c.out" 3 3
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 3
set c.out.a 0
cycle
system "echo '[] Receive 6'"
assert-bd-channel-valid "c.out" 3 6
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 6
set c.out.a 0
cycle

54
test/unit_tests/encoder2D_8x8/test.act
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@@ -1,54 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc encoder2d_2x2 (a1of1 x[8]; a1of1 y[8]; avMx1of2<6> out){
encoder2d_simple<3, 3, 8, 8, 0> e(.inx=x, .iny=y, .out=out);
e.to_pd_x = e.inx;
e.to_pd_y = e.iny;
bool _reset_B;
prs {
Reset => _reset_B-
}
e.supply.vss = GND;
e.supply.vdd = Vdd;
e.reset_B = _reset_B;
}
encoder2d_2x2 e;

238
test/unit_tests/encoder2D_8x8/test.prsim
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@@ -1,238 +0,0 @@
watchall
# mode run
system "echo '[] Set Out Ack/Valid Low'"
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Setting Neuron Req Low'"
set e.y[0].r 0
set e.y[1].r 0
set e.y[2].r 0
set e.y[3].r 0
set e.y[4].r 0
set e.y[5].r 0
set e.y[6].r 0
set e.y[7].r 0
set e.x[0].r 0
set e.x[1].r 0
set e.x[2].r 0
set e.x[3].r 0
set e.x[4].r 0
set e.x[5].r 0
set e.x[6].r 0
set e.x[7].r 0
set Reset 1
cycle
mode run
status X
status 0
set Reset 0
cycle
system "echo '[] Single Neuron Spikes (2,5), raise y[5].r'"
set e.y[5].r 1
# set e.x[2].r 1
cycle
assert e.y[5].a 1
system "echo '[] Asserted y[5].a 1'"
# assert e.e.Yarb.out.r 1
# assert e.e.Xarb.out.r 0
# assert e.e._x_v 0
system "echo '[] Raise x[2].r'"
# set e.y[5].r 1
set e.x[2].r 1
cycle
assert e.x[2].a 1
system "echo '[] Asserted x[2].a 1'"
# assert e.e.Yarb.out.r 1
# assert e.e.Xarb.out.r 1
# assert e.e._x_v 1
system "echo '[] Check Arbiter Acks'"
# assert e.e._x_a_B 1
assert e.y[0].a 0
assert e.y[1].a 0
assert e.y[2].a 0
assert e.y[3].a 0
assert e.y[4].a 0
assert e.y[5].a 1
assert e.y[6].a 0
assert e.y[7].a 0
# assert e.e.Yarb.out.a 1
assert e.x[0].a 0
assert e.x[1].a 0
assert e.x[2].a 1
assert e.x[3].a 0
assert e.x[4].a 0
assert e.x[5].a 0
assert e.x[6].a 0
assert e.x[7].a 0
# assert e.e.Xarb.out.a 1
assert-qdi-channel-valid "e.out" 6 42
system "echo '[] Asserted output encoding valid 42'"
set e.out.v 1
system "echo '[] Finish Neuron Handshake'"
set e.y[5].r 0
set e.x[2].r 0
cycle
assert e.y[0].a 0
assert e.y[1].a 0
assert e.y[2].a 0
assert e.y[3].a 0
assert e.y[4].a 0
assert e.y[5].a 0
assert e.y[6].a 0
assert e.y[7].a 0
assert e.x[0].a 0
assert e.x[1].a 0
assert e.x[2].a 0
assert e.x[3].a 0
assert e.x[4].a 0
assert e.x[5].a 0
assert e.x[6].a 0
assert e.x[7].a 0
system "echo '[] Asserted all in acks 0'"
set e.out.a 1
cycle
assert-qdi-channel-neutral "e.out" 6
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Neuron (2,5) Encoded'"
system "echo '[] Single Neuron Spikes (5,2), raise y[2].r'"
set e.y[2].r 1
# set e.x[2].r 1
cycle
assert e.y[2].a 1
system "echo '[] Asserted y[2].a 1'"
# assert e.e.Yarb.out.r 1
# assert e.e.Xarb.out.r 0
# assert e.e._x_v 0
system "echo '[] Raise x[5].r'"
# set e.y[5].r 1
set e.x[5].r 1
cycle
assert e.x[5].a 1
system "echo '[] Asserted x[5].a 1'"
# assert e.e.Yarb.out.r 1
# assert e.e.Xarb.out.r 1
# assert e.e._x_v 1
system "echo '[] Check Arbiter Acks'"
# assert e.e._x_a_B 1
assert e.y[0].a 0
assert e.y[1].a 0
assert e.y[2].a 1
assert e.y[3].a 0
assert e.y[4].a 0
assert e.y[5].a 0
assert e.y[6].a 0
assert e.y[7].a 0
# assert e.e.Yarb.out.a 1
assert e.x[0].a 0
assert e.x[1].a 0
assert e.x[2].a 0
assert e.x[3].a 0
assert e.x[4].a 0
assert e.x[5].a 1
assert e.x[6].a 0
assert e.x[7].a 0
# assert e.e.Xarb.out.a 1
assert-qdi-channel-valid "e.out" 6 21
system "echo '[] Asserted output encoding valid 21'"
set e.out.v 1
system "echo '[] Finish Neuron Handshake'"
set e.y[2].r 0
set e.x[5].r 0
cycle
assert e.y[0].a 0
assert e.y[1].a 0
assert e.y[2].a 0
assert e.y[3].a 0
assert e.y[4].a 0
assert e.y[5].a 0
assert e.y[6].a 0
assert e.y[7].a 0
assert e.x[0].a 0
assert e.x[1].a 0
assert e.x[2].a 0
assert e.x[3].a 0
assert e.x[4].a 0
assert e.x[5].a 0
assert e.x[6].a 0
assert e.x[7].a 0
system "echo '[] Asserted all in acks 0'"
set e.out.a 1
cycle
assert-qdi-channel-neutral "e.out" 6
set e.out.a 0
set e.out.v 0
cycle
system "echo '[] Neuron (5,2) Encoded'"

44
test/unit_tests/encoder_7/test.act
View File

@@ -1,44 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc encoder_7 (bool? in[7]; Mx1of2<3> out){
dualrail_encoder<3,7> e(.in=in, .out=out);
e.supply.vss = GND;
e.supply.vdd = Vdd;
}
encoder_7 e;

78
test/unit_tests/encoder_7/test.prsim
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@@ -1,78 +0,0 @@
watchall
system "echo '0'"
set e.in[0] 0
set e.in[1] 0
set e.in[2] 0
set e.in[3] 0
set e.in[4] 0
set e.in[5] 0
set e.in[6] 0
# set-bool-array "e.in" 7 0
cycle
mode run
# assert t.out 0
system "echo '[] setting input 0 high'"
set Reset 0
set e.in[0] 1
cycle
system "echo '[] removing inputs'"
set e.in[0] 0
cycle
system "echo '[] setting input 4 high'"
set e.in[4] 1
cycle
system "echo '[] removing inputs'"
set e.in[4] 0
cycle
system "echo '[] setting input 6 high'"
set e.in[6] 1
cycle
system "echo '[] removing inputs'"
set e.in[6] 0
cycle
# system "echo '[] setting input 6 high'"
# set e.in[4] 0
# set e.in[6] 1
# cycle
# assert t.out 0
# system "echo '[] setting all bits high'"
# set t.in[3] 1
# set t.in[4] 1
# cycle
# assert t.out 1
# system "echo '[] setting some low'"
# set t.in[0] 0
# set t.in[1] 0
# cycle
# assert t.out 0
# system "echo '[] setting all low'"
# set t.in[2] 0
# set t.in[3] 0
# set t.in[4] 0
# cycle
# assert t.out 0

77
test/unit_tests/fifo-decoder_dly-neurons-encoder-fifo/test.act
View File

@@ -1,77 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/primitives.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc fifo_decoder_neurons_encoder_fifo (avMx1of2<7> in; avMx1of2<7> out; bool? dly_cfg[6]){
bool _reset_B;
prs {
Reset => _reset_B-
}
power supply;
supply.vdd = Vdd;
supply.vss = GND;
pint NxC,NyC,Nx,Ny;
NxC = 4;
NyC = 3;
Nx = 1<<NxC;
Ny = 1<<NyC;
fifo<NxC + NyC,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);
decoder_2d_dly<NxC,NyC,Nx,Ny,6> decoder(.in = fifo_pre.out, .dly_cfg = dly_cfg,
.reset_B = _reset_B, .supply = supply);
and_grid<Nx, Ny> _and_grid(.inx = decoder.outx, .iny = decoder.outy, .supply = supply);
// Pretend that each "synapse" immediately makes its one neuron "spike".
// that is, connect the output of each encoder target to the decoder input.
nrn_hs_2d_array<Nx,Ny> neuron_grid(.reset_B = _reset_B, .supply = supply);
(i:Nx*Ny:
// Connect the output bool to the input req of each neuron handshaker
// Leave ack dangling.
neuron_grid.in[i].r = _and_grid.out[i];
)
encoder2d_simple<NxC,NyC,Nx,Ny,4> encoder(.inx = neuron_grid.outx, .iny = neuron_grid.outy,
.to_pd_x = neuron_grid.to_pd_x, .to_pd_y = neuron_grid.to_pd_y,
.reset_B = _reset_B, .supply = supply);
fifo<NxC + NyC,5> fifo_post(.in = encoder.out, .out = out, .reset_B = _reset_B, .supply = supply);
}
// fifo_decoder_neurons_encoder_fifo e;
fifo_decoder_neurons_encoder_fifo e;

101
test/unit_tests/fifo-decoder_dly-neurons-encoder-fifo/test.prsim
View File

@@ -1,101 +0,0 @@
watchall
set e.out.a 0
set e.out.v 0
set-qdi-channel-neutral "e.in" 7
set Reset 1
set e.dly_cfg[0] 1
set e.dly_cfg[1] 1
set e.dly_cfg[2] 1
set e.dly_cfg[3] 1
set e.dly_cfg[4] 1
set e.dly_cfg[5] 1
cycle
# assert e.decoder.outx[0] 0
# assert e.neuron_grid.outx[0].r 0
# assert e.encoder.pd_x[0].inv.y 1
# assert e.encoder.pd_x[0].pull_downR.n1 1
# assert e.encoder.pd_x[0].pull_downR.n2 1
# assert e.encoder.pd_x[0].pull_downR.y 0
# assert e.neuron_grid.neurons[0].pu_x.p1 1
# assert e.neuron_grid.neurons[0].pu_x.p2 1
# assert e.neuron_grid.neurons[0].pu_x.p3 1
# assert e.encoder.Xarb.in[0].a 0
mode run
system "echo '[] Set reset 0'"
system "echo '[] Asserting decoder req 0 0'"
status X
set Reset 0
cycle
system "echo '[] Sending in a packet'"
set-qdi-channel-valid "e.in" 7 75
cycle
assert-qdi-channel-valid "e.out" 7 75
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 7
cycle
assert e.in.a 0
assert e.in.v 0
system "echo '[] Sending in another packet'"
set-qdi-channel-valid "e.in" 7 22
cycle
# Output is still the first packet
assert-qdi-channel-valid "e.out" 7 75
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 7
cycle
assert e.in.a 0
assert e.in.v 0
system "echo '[] Giving out ack'"
set e.out.a 1
set e.out.v 1
cycle
assert-qdi-channel-neutral "e.out" 7
system "echo '[] Removing ack'"
set e.out.a 0
set e.out.v 0
cycle
assert-qdi-channel-valid "e.out" 7 22
system "echo '[] Giving out ack'"
set e.out.a 1
set e.out.v 1
cycle
assert-qdi-channel-neutral "e.out" 7
system "echo '[] Removing ack'"
set e.out.a 0
set e.out.v 0
cycle
assert-qdi-channel-neutral "e.out" 7

73
test/unit_tests/fifo-decoder_hs-neurons-encoder-fifo/test.act
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@@ -1,73 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/primitives.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc fifo_decoder_neurons_encoder_fifo (avMx1of2<7> in; avMx1of2<7> out){
bool _reset_B;
prs {
Reset => _reset_B-
}
power supply;
supply.vdd = Vdd;
supply.vss = GND;
pint NxC,NyC,Nx,Ny;
NxC = 4;
NyC = 3;
Nx = 1<<NxC;
Ny = 1<<NyC;
fifo<NxC + NyC,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);
decoder_2d_hs<NxC,NyC,Nx,Ny> decoder(.in = fifo_pre.out, .reset_B = _reset_B, .supply = supply);
// Pretend that each "synapse" immediately makes its one neuron "spike".
// that is, connect the output of each encoder target to the decoder input.
nrn_hs_2d_array<Nx,Ny> neuron_grid(.reset_B = _reset_B, .supply = supply);
(i:Nx*Ny:
neuron_grid.in[i].r = decoder.out[i].r;
neuron_grid.in[i].a = decoder.out[i].a;
)
encoder2d_simple<NxC,NyC,Nx,Ny,4> encoder(.inx = neuron_grid.outx, .iny = neuron_grid.outy,
.to_pd_x = neuron_grid.to_pd_x, .to_pd_y = neuron_grid.to_pd_y,
.reset_B = _reset_B, .supply = supply);
fifo<NxC + NyC,5> fifo_post(.in = encoder.out, .out = out, .reset_B = _reset_B, .supply = supply);
}
// fifo_decoder_neurons_encoder_fifo e;
fifo_decoder_neurons_encoder_fifo e;

74
test/unit_tests/fifo-decoder_hs-neurons-encoder-fifo/test.prsim
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@@ -1,74 +0,0 @@
watchall
set e.out.a 0
set e.out.v 0
set-qdi-channel-neutral "e.in" 7
set Reset 1
cycle
mode run
system "echo '[] Set reset 0'"
status X
set Reset 0
cycle
system "echo '[] Sending in a packet'"
set-qdi-channel-valid "e.in" 7 75
cycle
assert-qdi-channel-valid "e.out" 7 75
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 7
cycle
assert e.in.a 0
assert e.in.v 0
system "echo '[] Sending in another packet'"
set-qdi-channel-valid "e.in" 7 22
cycle
# Output is still the first packet
assert-qdi-channel-valid "e.out" 7 75
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 7
cycle
assert e.in.a 0
assert e.in.v 0
system "echo '[] Giving out ack'"
set e.out.a 1
set e.out.v 1
cycle
assert-qdi-channel-neutral "e.out" 7
system "echo '[] Removing ack'"
set e.out.a 0
set e.out.v 0
cycle
assert-qdi-channel-valid "e.out" 7 22
system "echo '[] Giving out ack'"
set e.out.a 1
set e.out.v 1
cycle
assert-qdi-channel-neutral "e.out" 7
system "echo '[] Removing ack'"
set e.out.a 0
set e.out.v 0
cycle
assert-qdi-channel-neutral "e.out" 7

90
test/unit_tests/fifo-decoder_hybrid-neurons-encoder-fifo/test.act
View File

@@ -1,90 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/primitives.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc fifo_decoder_neurons_encoder_fifo (avMx1of2<7> in; avMx1of2<7> out; bool? dly_cfg[4], hs_en, ack_disable){
bool _reset_B;
prs {
Reset => _reset_B-
}
power supply;
supply.vdd = Vdd;
supply.vss = GND;
pint NxC,NyC,Nx,Ny;
NxC = 4;
NyC = 3;
Nx = 1<<NxC;
Ny = 1<<NyC;
fifo<NxC + NyC,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);
decoder_2d_hybrid<NxC,NyC,Nx,Ny,4> decoder(.in = fifo_pre.out, .dly_cfg =dly_cfg,
.hs_en = hs_en, .ack_disable = ack_disable,
.reset_B = _reset_B, .supply = supply);
// // Pretend that each "synapse" immediately makes its one neuron "spike".
// // that is, connect the output of each encoder target to the decoder input.
// and_grid<Nx, Ny> _and_grid(.inx = decoder.out_req_x, .iny = decoder.out_req_y, .supply = supply);
// // Attach line end pull ups of decoder
// decoder.to_pu = decoder.
// Dummy synapse handshake circuits, to be removed for innovus
decoder_2d_synapse_hs<Nx, Ny> _synapses(
.in_req_x = decoder.out_req_x, .in_req_y = decoder.out_req_y,
.to_pu = decoder.to_pu,
.out_ackB_decoder = decoder.in_ackB_decoder,
.supply = supply);
nrn_hs_2d_array<Nx,Ny> neuron_grid(.in =_synapses.synapses,
.reset_B = _reset_B, .supply = supply);
encoder2d_simple<NxC,NyC,Nx,Ny,4> encoder(.inx = neuron_grid.outx, .iny = neuron_grid.outy,
.to_pd_x = neuron_grid.to_pd_x, .to_pd_y = neuron_grid.to_pd_y,
.reset_B = _reset_B, .supply = supply);
fifo<NxC + NyC,5> fifo_post(.in = encoder.out, .out = out, .reset_B = _reset_B, .supply = supply);
}
// fifo_decoder_neurons_encoder_fifo e;
fifo_decoder_neurons_encoder_fifo e;

149
test/unit_tests/fifo-decoder_hybrid-neurons-encoder-fifo/test.prsim
View File

@@ -1,149 +0,0 @@
watchall
# Use handshaking at first
set e.dly_cfg[0] 0
set e.dly_cfg[1] 0
set e.dly_cfg[2] 0
set e.dly_cfg[3] 0
set e.hs_en 1
set e.ack_disable 0
set e.out.a 0
set e.out.v 0
set-qdi-channel-neutral "e.in" 7
set Reset 1
cycle
mode run
system "echo '[] Set reset 0'"
status X
set Reset 0
cycle
system "echo '[] Sending in a packet'"
set-qdi-channel-valid "e.in" 7 75
cycle
assert-qdi-channel-valid "e.out" 7 75
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 7
cycle
assert e.in.a 0
assert e.in.v 0
system "echo '[] Sending in another packet'"
set-qdi-channel-valid "e.in" 7 22
cycle
# Output is still the first packet
assert-qdi-channel-valid "e.out" 7 75
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 7
cycle
assert e.in.a 0
assert e.in.v 0
system "echo '[] Giving out ack'"
set e.out.a 1
set e.out.v 1
cycle
assert-qdi-channel-neutral "e.out" 7
system "echo '[] Removing ack'"
set e.out.a 0
set e.out.v 0
cycle
assert-qdi-channel-valid "e.out" 7 22
system "echo '[] Giving out ack'"
set e.out.a 1
set e.out.v 1
cycle
assert-qdi-channel-neutral "e.out" 7
system "echo '[] Removing ack'"
set e.out.a 0
set e.out.v 0
cycle
assert-qdi-channel-neutral "e.out" 7
# Enable delays
set e.dly_cfg[0] 1
set e.dly_cfg[1] 1
set e.dly_cfg[2] 1
set e.dly_cfg[3] 1
set e.hs_en 0
cycle
mode run
system "echo '[] Set reset 0'"
status X
set Reset 0
cycle
system "echo '[] Sending in a packet WITH DELAYS'"
set-qdi-channel-valid "e.in" 7 75
cycle
assert-qdi-channel-valid "e.out" 7 75
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 7
cycle
assert e.in.a 0
assert e.in.v 0
system "echo '[] Sending in another packet'"
set-qdi-channel-valid "e.in" 7 22
cycle
# Output is still the first packet
assert-qdi-channel-valid "e.out" 7 75
assert e.in.a 1
assert e.in.v 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "e.in" 7
cycle
assert e.in.a 0
assert e.in.v 0
system "echo '[] Giving out ack'"
set e.out.a 1
set e.out.v 1
cycle
assert-qdi-channel-neutral "e.out" 7
system "echo '[] Removing ack'"
set e.out.a 0
set e.out.v 0
cycle
assert-qdi-channel-valid "e.out" 7 22
system "echo '[] Giving out ack'"
set e.out.a 1
set e.out.v 1
cycle
assert-qdi-channel-neutral "e.out" 7
system "echo '[] Removing ack'"
set e.out.a 0
set e.out.v 0
cycle
assert-qdi-channel-neutral "e.out" 7

59
test/unit_tests/fifo-register-fifo/test.act
View File

@@ -1,59 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/registers.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc fifo_reg_fifo_3x5x8 (avMx1of2<3+5+1> in; Mx1of2<5> data[8]; avMx1of2<8> out){
bool _reset_B;
prs {
Reset => _reset_B-
}
power supply;
supply.vdd = Vdd;
supply.vss = GND;
fifo<9,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);
// Make a register array with 3 bit address (-> 8 registers),
// each register holding 5 bits.
register_wr_array<3,5,8> reg(.in = fifo_pre.out, .data = data,
.reset_B = _reset_B, .supply = supply);
fifo<8,5> fifo_post(.in = reg.out, .out = out, .reset_B = _reset_B, .supply = supply);
}
// fifo_decoder_neurons_encoder_fifo e;
fifo_reg_fifo_3x5x8 b;

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