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e05196bb7e
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2c491a6e37
@ -270,9 +270,6 @@ export template<pint NxC, NyC, Nx, Ny, N_dly_cfg>
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defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg[N_dly_cfg], hs_en,
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defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg[N_dly_cfg], hs_en,
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reset_B; power supply) {
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reset_B; power supply) {
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bool hs_enB;
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INV_X4 hs_inv(.a = hs_en, .y = hs_enB, .vdd = supply.vdd, .vss = supply.vss);
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// Buffer to recieve concat(x,y) address packet
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// Buffer to recieve concat(x,y) address packet
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buffer<NxC+NyC> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
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buffer<NxC+NyC> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
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@ -326,11 +323,10 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
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// bc smaller
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// bc smaller
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// and bc the delay that an AND induces means that the pullup could
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// and bc the delay that an AND induces means that the pullup could
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// end up fighting a synapse pulldown, as both have the correct req sigs.
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// end up fighting a synapse pulldown, as both have the correct req sigs.
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A_2P_U_X4 pu[Nx]; // TODO probably replace this with variable strength PU
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A_1P_U_X4 pu[Nx]; // TODO probably replace this with variable strength PU
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A_1P_U_X4 pu_reset[Nx];
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A_1P_U_X4 pu_reset[Nx];
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(i:Nx:
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(i:Nx:
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pu[i].a = d_dr_xX[i].out[Ny];
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pu[i].a = d_dr_xX[i].out[Ny];
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pu[i].b = hs_enB;
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pu[i].y = _out_acksB[i];
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pu[i].y = _out_acksB[i];
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pu[i].vdd = supply.vdd;
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pu[i].vdd = supply.vdd;
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pu[i].vss = supply.vss;
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pu[i].vss = supply.vss;
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@ -358,15 +354,17 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
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// _only_ once _both_ ackB has been reset, _and_ its output data
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// _only_ once _both_ ackB has been reset, _and_ its output data
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// has been fully invalidated.
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// has been fully invalidated.
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// Otherwise run into the issue that ack is removed before data is invalid.
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// Otherwise run into the issue that ack is removed before data is invalid.
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A_2C_B_X1 buf_ack_Cel(.c1 = _ortree.out, .c2 = valid_Cel.y,
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A_2C_B_X1 buf_ack_Cel(.c1 = _ortree.out, .c2 = valid_Cel.y, .y = addr_buf.out.a,
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.vdd = supply.vdd, .vss = supply.vss);
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.vdd = supply.vdd, .vss = supply.vss);
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// Mux to switch between acks from handshake or delay
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MUX2_X1 ack_mux(.s = hs_en, .a = valid_Cel.y, .b = buf_ack_Cel.y,
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.vdd = supply.vdd, .vss = supply.vss);
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// Programmable delay
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// Programmable delay
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delayprog<N_dly_cfg> dly(.in = ack_mux.y, .out = addr_buf.out.a, .s = dly_cfg, .supply = supply);
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delayprog<N_dly_cfg> dly(.s = dly_cfg, .supply = supply);
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dly.out = addr_buf.out.a;
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}
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}
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@ -741,7 +739,7 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
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// y_req pull up
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// y_req pull up
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NAND2_X1 nand_y(.a = _y_a_B, .b = _req, .vdd = supply.vdd, .vss = supply.vss);
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NAND2_X1 nand_y(.a = _y_a_B, .b = _req, .vdd = supply.vdd, .vss = supply.vss);
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A_1P_U_X4 pu_y(.a = nand_y.y, .y = outy.r, .vdd = supply.vdd, .vss = supply.vss);
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A_1P_U_X4 pu_y(.a = nand_y.y, .y = outy.r, .vdd = supply.vdd, .vss = supply.vss);
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// x_req pull up
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// x_req pull up
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NAND3_X1 nand_x(.a = _x_a_B, .b = _req, .c = outy.a, .vdd = supply.vdd, .vss = supply.vss);
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NAND3_X1 nand_x(.a = _x_a_B, .b = _req, .c = outy.a, .vdd = supply.vdd, .vss = supply.vss);
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A_1P_U_X4 pu_x(.a = nand_x.y, .y = outx.r, .vdd = supply.vdd, .vss = supply.vss);
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A_1P_U_X4 pu_x(.a = nand_x.y, .y = outx.r, .vdd = supply.vdd, .vss = supply.vss);
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Load Diff
@ -1,74 +0,0 @@
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/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library.
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* It's the testing facility for cell_lib_std.act
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/coders.act";
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import "../../dataflow_neuro/primitives.act";
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import "../../dataflow_neuro/cell_lib_async.act";
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import "../../dataflow_neuro/cell_lib_std.act";
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import globals;
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import std::data;
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open std::data;
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open tmpl::dataflow_neuro;
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defproc decoder_2d_hybrid_2x4 (avMx1of2<3> in; a1of1 out[8]; bool? dly_cfg[4], hs_en){
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bool _reset_B;
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prs {
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Reset => _reset_B-
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}
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power supply;
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supply.vdd = Vdd;
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supply.vss = GND;
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decoder_2d_hybrid<1,2,2,4,4> decoder(.in = in, .out = out, .dly_cfg = dly_cfg, .hs_en = hs_en,
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.reset_B = _reset_B, .supply = supply);
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// model the synapse as having automatic pulldown of ack.
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INV_X1 synapses[8];
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PULLDOWN_X4 synapses2[8];
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(i:8:
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synapses[i].a = decoder.out[i].r;
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synapses2[i].a = synapses[i].y;
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synapses2[i].y = decoder.out[i].a;
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synapses[i].vss = supply.vss;
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synapses[i].vdd = supply.vdd;
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synapses2[i].vss = supply.vss;
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synapses2[i].vdd = supply.vdd;
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)
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}
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// fifo_decoder_neurons_encoder_fifo e;
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decoder_2d_hybrid_2x4 e;
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@ -1,341 +0,0 @@
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watchall
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set e.out[0].a 0
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set e.out[1].a 0
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set e.out[2].a 0
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set e.out[3].a 0
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set e.out[4].a 0
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set e.out[5].a 0
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set e.out[6].a 0
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set e.out[7].a 0
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set e.dly_cfg[0] 0
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set e.dly_cfg[1] 0
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set e.dly_cfg[2] 0
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set e.dly_cfg[3] 0
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set e.hs_en 1
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set-qdi-channel-neutral "e.in" 3
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set Reset 1
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cycle
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mode run
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system "echo '[] Set reset 0'"
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status X
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set Reset 0
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cycle
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system "echo '[] Sending in a 7 packet'"
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set-qdi-channel-valid "e.in" 3 7
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cycle
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assert e.out[0].r 0
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assert e.out[1].r 0
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assert e.out[2].r 0
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assert e.out[3].r 0
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assert e.out[4].r 0
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assert e.out[5].r 0
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assert e.out[6].r 0
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assert e.out[7].r 1
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assert e.in.a 1
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assert e.in.v 1
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "e.in" 3
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system "echo '[] Synapse [7] gives ack'"
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set e.out[7].a 1
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cycle
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assert e.out[0].r 0
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assert e.out[1].r 0
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assert e.out[2].r 0
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assert e.out[3].r 0
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assert e.out[4].r 0
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assert e.out[5].r 0
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assert e.out[6].r 0
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assert e.out[7].r 0
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assert e.in.a 0
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assert e.in.v 0
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assert e.out[0].a 0
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assert e.out[1].a 0
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assert e.out[2].a 0
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assert e.out[3].a 0
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assert e.out[4].a 0
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assert e.out[5].a 0
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assert e.out[6].a 0
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assert e.out[7].a 0
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system "echo '[] Sending in a 5 packet'"
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set-qdi-channel-valid "e.in" 3 5
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cycle
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assert e.out[0].r 0
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assert e.out[1].r 0
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assert e.out[2].r 0
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assert e.out[3].r 0
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assert e.out[4].r 0
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assert e.out[5].r 1
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assert e.out[6].r 0
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assert e.out[7].r 0
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assert e.in.a 1
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assert e.in.v 1
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "e.in" 3
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system "echo '[] Synapse [5] gives ack'"
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set e.out[5].a 1
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cycle
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assert e.out[0].r 0
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assert e.out[1].r 0
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assert e.out[2].r 0
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assert e.out[3].r 0
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assert e.out[4].r 0
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assert e.out[5].r 0
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assert e.out[6].r 0
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assert e.out[7].r 0
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assert e.in.a 0
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assert e.in.v 0
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assert e.out[0].a 0
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assert e.out[1].a 0
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assert e.out[2].a 0
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assert e.out[3].a 0
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assert e.out[4].a 0
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assert e.out[5].a 0
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assert e.out[6].a 0
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assert e.out[7].a 0
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system "echo '[] Sending in a 1 packet'"
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set-qdi-channel-valid "e.in" 3 1
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cycle
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assert e.out[0].r 0
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assert e.out[1].r 1
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assert e.out[2].r 0
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assert e.out[3].r 0
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assert e.out[4].r 0
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assert e.out[5].r 0
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assert e.out[6].r 0
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assert e.out[7].r 0
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assert e.in.a 1
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assert e.in.v 1
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system "echo '[] Synapse [1] gives ack'"
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set e.out[1].a 1
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cycle
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assert e.out[0].r 0
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assert e.out[1].r 0
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assert e.out[2].r 0
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assert e.out[3].r 0
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assert e.out[4].r 0
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assert e.out[5].r 0
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assert e.out[6].r 0
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assert e.out[7].r 0
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assert e.out[0].a 0
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assert e.out[1].a 0
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assert e.out[2].a 0
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assert e.out[3].a 0
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assert e.out[4].a 0
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assert e.out[5].a 0
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assert e.out[6].a 0
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assert e.out[7].a 0
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assert e.in.a 1
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assert e.in.v 1
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system "echo '[] Removing input, enabling delays'"
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set-qdi-channel-neutral "e.in" 3
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cycle
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assert e.in.a 0
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assert e.in.v 0
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system "echo '[] Enabling delays'"
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cycle
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set e.dly_cfg[0] 1
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set e.dly_cfg[1] 1
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set e.dly_cfg[2] 1
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set e.dly_cfg[3] 1
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system "echo '[] Sending in a 7 packet, with delays'"
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set-qdi-channel-valid "e.in" 3 7
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cycle
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assert e.out[0].r 0
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assert e.out[1].r 0
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assert e.out[2].r 0
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assert e.out[3].r 0
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assert e.out[4].r 0
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assert e.out[5].r 0
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assert e.out[6].r 0
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assert e.out[7].r 1
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assert e.in.a 1
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assert e.in.v 1
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "e.in" 3
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system "echo '[] Synapse [7] gives ack'"
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set e.out[7].a 1
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cycle
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assert e.out[0].r 0
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assert e.out[1].r 0
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assert e.out[2].r 0
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assert e.out[3].r 0
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assert e.out[4].r 0
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assert e.out[5].r 0
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assert e.out[6].r 0
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assert e.out[7].r 0
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assert e.in.a 0
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assert e.in.v 0
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assert e.out[0].a 0
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assert e.out[1].a 0
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assert e.out[2].a 0
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assert e.out[3].a 0
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assert e.out[4].a 0
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assert e.out[5].a 0
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assert e.out[6].a 0
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assert e.out[7].a 0
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|
||||||
system "echo '[] Sending in a 5 packet'"
|
|
||||||
set-qdi-channel-valid "e.in" 3 5
|
|
||||||
cycle
|
|
||||||
assert e.out[0].r 0
|
|
||||||
assert e.out[1].r 0
|
|
||||||
assert e.out[2].r 0
|
|
||||||
assert e.out[3].r 0
|
|
||||||
assert e.out[4].r 0
|
|
||||||
assert e.out[5].r 1
|
|
||||||
assert e.out[6].r 0
|
|
||||||
assert e.out[7].r 0
|
|
||||||
assert e.in.a 1
|
|
||||||
assert e.in.v 1
|
|
||||||
|
|
||||||
system "echo '[] Removing input'"
|
|
||||||
set-qdi-channel-neutral "e.in" 3
|
|
||||||
|
|
||||||
|
|
||||||
system "echo '[] Synapse [5] gives ack'"
|
|
||||||
set e.out[5].a 1
|
|
||||||
cycle
|
|
||||||
assert e.out[0].r 0
|
|
||||||
assert e.out[1].r 0
|
|
||||||
assert e.out[2].r 0
|
|
||||||
assert e.out[3].r 0
|
|
||||||
assert e.out[4].r 0
|
|
||||||
assert e.out[5].r 0
|
|
||||||
assert e.out[6].r 0
|
|
||||||
assert e.out[7].r 0
|
|
||||||
assert e.in.a 0
|
|
||||||
assert e.in.v 0
|
|
||||||
assert e.out[0].a 0
|
|
||||||
assert e.out[1].a 0
|
|
||||||
assert e.out[2].a 0
|
|
||||||
assert e.out[3].a 0
|
|
||||||
assert e.out[4].a 0
|
|
||||||
assert e.out[5].a 0
|
|
||||||
assert e.out[6].a 0
|
|
||||||
assert e.out[7].a 0
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
system "echo '[] Sending in a 1 packet'"
|
|
||||||
set-qdi-channel-valid "e.in" 3 1
|
|
||||||
cycle
|
|
||||||
assert e.out[0].r 0
|
|
||||||
assert e.out[1].r 1
|
|
||||||
assert e.out[2].r 0
|
|
||||||
assert e.out[3].r 0
|
|
||||||
assert e.out[4].r 0
|
|
||||||
assert e.out[5].r 0
|
|
||||||
assert e.out[6].r 0
|
|
||||||
assert e.out[7].r 0
|
|
||||||
assert e.in.a 1
|
|
||||||
assert e.in.v 1
|
|
||||||
|
|
||||||
|
|
||||||
system "echo '[] Synapse [1] gives ack'"
|
|
||||||
set e.out[1].a 1
|
|
||||||
cycle
|
|
||||||
assert e.out[0].r 0
|
|
||||||
assert e.out[1].r 0
|
|
||||||
assert e.out[2].r 0
|
|
||||||
assert e.out[3].r 0
|
|
||||||
assert e.out[4].r 0
|
|
||||||
assert e.out[5].r 0
|
|
||||||
assert e.out[6].r 0
|
|
||||||
assert e.out[7].r 0
|
|
||||||
|
|
||||||
assert e.out[0].a 0
|
|
||||||
assert e.out[1].a 0
|
|
||||||
assert e.out[2].a 0
|
|
||||||
assert e.out[3].a 0
|
|
||||||
assert e.out[4].a 0
|
|
||||||
assert e.out[5].a 0
|
|
||||||
assert e.out[6].a 0
|
|
||||||
assert e.out[7].a 0
|
|
||||||
|
|
||||||
assert e.in.a 1
|
|
||||||
assert e.in.v 1
|
|
||||||
|
|
||||||
system "echo '[] Removing input, disabling handshaking'"
|
|
||||||
set-qdi-channel-neutral "e.in" 3
|
|
||||||
cycle
|
|
||||||
assert e.in.a 0
|
|
||||||
assert e.in.v 0
|
|
||||||
|
|
||||||
set e.hs_en 0
|
|
||||||
cycle
|
|
||||||
|
|
||||||
system "echo '[] Sending in a 0, handshaking disabled'"
|
|
||||||
set-qdi-channel-valid "e.in" 3 0
|
|
||||||
cycle
|
|
||||||
assert e.in.a 1
|
|
||||||
assert e.in.v 1
|
|
||||||
|
|
||||||
system "echo '[] Removing input'"
|
|
||||||
set-qdi-channel-neutral "e.in" 3
|
|
||||||
cycle
|
|
||||||
assert e.in.a 0
|
|
||||||
assert e.in.v 0
|
|
||||||
|
|
||||||
system "echo '[] Sending in a 7, handshaking disabled'"
|
|
||||||
set-qdi-channel-valid "e.in" 3 7
|
|
||||||
cycle
|
|
||||||
assert e.in.a 1
|
|
||||||
assert e.in.v 1
|
|
||||||
|
|
||||||
system "echo '[] Removing input'"
|
|
||||||
set-qdi-channel-neutral "e.in" 3
|
|
||||||
cycle
|
|
||||||
assert e.in.a 0
|
|
||||||
assert e.in.v 0
|
|
||||||
|
|
||||||
|
|
||||||
system "echo '[] Sending in a 5, handshaking disabled'"
|
|
||||||
set-qdi-channel-valid "e.in" 3 5
|
|
||||||
cycle
|
|
||||||
assert e.in.a 1
|
|
||||||
assert e.in.v 1
|
|
||||||
|
|
||||||
system "echo '[] Removing input'"
|
|
||||||
set-qdi-channel-neutral "e.in" 3
|
|
||||||
cycle
|
|
||||||
assert e.in.a 0
|
|
||||||
assert e.in.v 0
|
|
||||||
|
|
||||||
|
|
||||||
|
|
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
@ -1,73 +0,0 @@
|
|||||||
/*************************************************************************
|
|
||||||
*
|
|
||||||
* This file is part of ACT dataflow neuro library.
|
|
||||||
* It's the testing facility for cell_lib_std.act
|
|
||||||
*
|
|
||||||
* Copyright (c) 2022 University of Groningen - Ole Richter
|
|
||||||
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
|
|
||||||
* Copyright (c) 2022 University of Groningen - Michele Mastella
|
|
||||||
* Copyright (c) 2022 University of Groningen - Madison Cotteret
|
|
||||||
*
|
|
||||||
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
|
|
||||||
*
|
|
||||||
* You may redistribute and modify this documentation and make products
|
|
||||||
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
|
|
||||||
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
|
|
||||||
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
|
|
||||||
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
|
|
||||||
* for applicable conditions.
|
|
||||||
*
|
|
||||||
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
|
|
||||||
*
|
|
||||||
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
|
|
||||||
* these sources, You must maintain the Source Location visible in its
|
|
||||||
* documentation.
|
|
||||||
*
|
|
||||||
**************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
import "../../dataflow_neuro/coders.act";
|
|
||||||
import "../../dataflow_neuro/primitives.act";
|
|
||||||
|
|
||||||
import globals;
|
|
||||||
import std::data;
|
|
||||||
|
|
||||||
open std::data;
|
|
||||||
|
|
||||||
open tmpl::dataflow_neuro;
|
|
||||||
|
|
||||||
defproc fifo_decoder_neurons_encoder_fifo (avMx1of2<7> in; avMx1of2<7> out; bool? dly_cfg[4], hs_en){
|
|
||||||
bool _reset_B;
|
|
||||||
prs {
|
|
||||||
Reset => _reset_B-
|
|
||||||
}
|
|
||||||
power supply;
|
|
||||||
supply.vdd = Vdd;
|
|
||||||
supply.vss = GND;
|
|
||||||
|
|
||||||
pint NxC,NyC,Nx,Ny;
|
|
||||||
NxC = 4;
|
|
||||||
NyC = 3;
|
|
||||||
Nx = 1<<NxC;
|
|
||||||
Ny = 1<<NyC;
|
|
||||||
|
|
||||||
fifo<NxC + NyC,5> fifo_pre(.in = in, .reset_B = _reset_B, .supply = supply);
|
|
||||||
decoder_2d_hybrid<NxC,NyC,Nx,Ny,4> decoder(.in = fifo_pre.out, .dly_cfg =dly_cfg, .hs_en = hs_en,
|
|
||||||
.reset_B = _reset_B, .supply = supply);
|
|
||||||
// Pretend that each "synapse" immediately makes its one neuron "spike".
|
|
||||||
// that is, connect the output of each encoder target to the decoder input.
|
|
||||||
nrn_hs_2D_array<Nx,Ny,10> neuron_grid(.reset_B = _reset_B, .supply = supply);
|
|
||||||
(i:Nx*Ny:
|
|
||||||
neuron_grid.in[i].r = decoder.out[i].r;
|
|
||||||
neuron_grid.in[i].a = decoder.out[i].a;
|
|
||||||
)
|
|
||||||
|
|
||||||
encoder2D<NxC,NyC,Nx,Ny,4> encoder(.inx = neuron_grid.outx, .iny = neuron_grid.outy,
|
|
||||||
.reset_B = _reset_B, .supply = supply);
|
|
||||||
fifo<NxC + NyC,5> fifo_post(.in = encoder.out, .out = out, .reset_B = _reset_B, .supply = supply);
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
// fifo_decoder_neurons_encoder_fifo e;
|
|
||||||
fifo_decoder_neurons_encoder_fifo e;
|
|
@ -1,149 +0,0 @@
|
|||||||
watchall
|
|
||||||
|
|
||||||
|
|
||||||
# Use handshaking at first
|
|
||||||
set e.dly_cfg[0] 0
|
|
||||||
set e.dly_cfg[1] 0
|
|
||||||
set e.dly_cfg[2] 0
|
|
||||||
set e.dly_cfg[3] 0
|
|
||||||
set e.hs_en 1
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
set e.out.a 0
|
|
||||||
set e.out.v 0
|
|
||||||
set-qdi-channel-neutral "e.in" 7
|
|
||||||
set Reset 1
|
|
||||||
|
|
||||||
cycle
|
|
||||||
|
|
||||||
|
|
||||||
mode run
|
|
||||||
system "echo '[] Set reset 0'"
|
|
||||||
status X
|
|
||||||
set Reset 0
|
|
||||||
cycle
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
system "echo '[] Sending in a packet'"
|
|
||||||
set-qdi-channel-valid "e.in" 7 75
|
|
||||||
cycle
|
|
||||||
assert-qdi-channel-valid "e.out" 7 75
|
|
||||||
assert e.in.a 1
|
|
||||||
assert e.in.v 1
|
|
||||||
|
|
||||||
system "echo '[] Removing input'"
|
|
||||||
set-qdi-channel-neutral "e.in" 7
|
|
||||||
cycle
|
|
||||||
assert e.in.a 0
|
|
||||||
assert e.in.v 0
|
|
||||||
|
|
||||||
system "echo '[] Sending in another packet'"
|
|
||||||
set-qdi-channel-valid "e.in" 7 22
|
|
||||||
cycle
|
|
||||||
# Output is still the first packet
|
|
||||||
assert-qdi-channel-valid "e.out" 7 75
|
|
||||||
assert e.in.a 1
|
|
||||||
assert e.in.v 1
|
|
||||||
|
|
||||||
system "echo '[] Removing input'"
|
|
||||||
set-qdi-channel-neutral "e.in" 7
|
|
||||||
cycle
|
|
||||||
assert e.in.a 0
|
|
||||||
assert e.in.v 0
|
|
||||||
|
|
||||||
system "echo '[] Giving out ack'"
|
|
||||||
set e.out.a 1
|
|
||||||
set e.out.v 1
|
|
||||||
cycle
|
|
||||||
assert-qdi-channel-neutral "e.out" 7
|
|
||||||
|
|
||||||
system "echo '[] Removing ack'"
|
|
||||||
set e.out.a 0
|
|
||||||
set e.out.v 0
|
|
||||||
cycle
|
|
||||||
assert-qdi-channel-valid "e.out" 7 22
|
|
||||||
|
|
||||||
system "echo '[] Giving out ack'"
|
|
||||||
set e.out.a 1
|
|
||||||
set e.out.v 1
|
|
||||||
cycle
|
|
||||||
assert-qdi-channel-neutral "e.out" 7
|
|
||||||
|
|
||||||
system "echo '[] Removing ack'"
|
|
||||||
set e.out.a 0
|
|
||||||
set e.out.v 0
|
|
||||||
cycle
|
|
||||||
assert-qdi-channel-neutral "e.out" 7
|
|
||||||
|
|
||||||
|
|
||||||
# Enable delays
|
|
||||||
set e.dly_cfg[0] 1
|
|
||||||
set e.dly_cfg[1] 1
|
|
||||||
set e.dly_cfg[2] 1
|
|
||||||
set e.dly_cfg[3] 1
|
|
||||||
set e.hs_en 0
|
|
||||||
cycle
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
mode run
|
|
||||||
system "echo '[] Set reset 0'"
|
|
||||||
status X
|
|
||||||
set Reset 0
|
|
||||||
cycle
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
system "echo '[] Sending in a packet WITH DELAYS'"
|
|
||||||
set-qdi-channel-valid "e.in" 7 75
|
|
||||||
cycle
|
|
||||||
assert-qdi-channel-valid "e.out" 7 75
|
|
||||||
assert e.in.a 1
|
|
||||||
assert e.in.v 1
|
|
||||||
|
|
||||||
system "echo '[] Removing input'"
|
|
||||||
set-qdi-channel-neutral "e.in" 7
|
|
||||||
cycle
|
|
||||||
assert e.in.a 0
|
|
||||||
assert e.in.v 0
|
|
||||||
|
|
||||||
system "echo '[] Sending in another packet'"
|
|
||||||
set-qdi-channel-valid "e.in" 7 22
|
|
||||||
cycle
|
|
||||||
# Output is still the first packet
|
|
||||||
assert-qdi-channel-valid "e.out" 7 75
|
|
||||||
assert e.in.a 1
|
|
||||||
assert e.in.v 1
|
|
||||||
|
|
||||||
system "echo '[] Removing input'"
|
|
||||||
set-qdi-channel-neutral "e.in" 7
|
|
||||||
cycle
|
|
||||||
assert e.in.a 0
|
|
||||||
assert e.in.v 0
|
|
||||||
|
|
||||||
system "echo '[] Giving out ack'"
|
|
||||||
set e.out.a 1
|
|
||||||
set e.out.v 1
|
|
||||||
cycle
|
|
||||||
assert-qdi-channel-neutral "e.out" 7
|
|
||||||
|
|
||||||
system "echo '[] Removing ack'"
|
|
||||||
set e.out.a 0
|
|
||||||
set e.out.v 0
|
|
||||||
cycle
|
|
||||||
assert-qdi-channel-valid "e.out" 7 22
|
|
||||||
|
|
||||||
system "echo '[] Giving out ack'"
|
|
||||||
set e.out.a 1
|
|
||||||
set e.out.v 1
|
|
||||||
cycle
|
|
||||||
assert-qdi-channel-neutral "e.out" 7
|
|
||||||
|
|
||||||
system "echo '[] Removing ack'"
|
|
||||||
set e.out.a 0
|
|
||||||
set e.out.v 0
|
|
||||||
cycle
|
|
||||||
assert-qdi-channel-neutral "e.out" 7
|
|
||||||
|
|
Loading…
Reference in New Issue
Block a user